ECAD DEE30071

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 9
Right Click and select simulate graph or click at the graph until it turn red and
press space bar.

 Setting start time = 1ms & Stop time =1ms for Vout
Step 7:
Use Graph Mode and select Frequency graph to investigate the frequency
response for this circuit and use Voltage probe mode to check the output voltage
for this amplifier, drag the probe mode into the graph.

96 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 9
Right Click and select simulate graph or click at the graph until it turn red and
press space bar.

97 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 10:
From the Frequency response you can check the Bandwidth, fCL, and Avmax

98 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 11:

Edit Frequecy graph and set Y scale to dB, simulate the graph and maximize the
graph to analyze the frequency response. From the graph Avmax=0dB , so the
Cutt-off freq = -3dB. so. fCL=153Hz

Low Cutoff frequency , fCL = 153Hz

RESULT :

Vin Vin
AMP=6
OFFSET=0 Vout
FREQ=1kHz
PHASE=0 R1
THETA=0
Vout
Vin 1k

C1

1u

GND

99 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Lesson 3.8
Title Inverting Amplifier Design And Frequency Response

Op-amp Inverting Amplifier
Step 1:
Create new project or open schematic capture

100 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 2:
Design a schematic using LM741 Op-Amp IC

Step 3:
Insert Vin with 1v amplitude and 1kHz frequency by using DC generator mode.

101 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 4:
By using instrument mode connect oscilloscope Channel A to Vin and Channel
B to Vout to measure the gain.

Step 5:
Run the simulation and compare the output voltage and input voltage, from the
simulation we can see that the voltage gain = 1 to make the voltage gain =10, we
need to change the R2 =1K, Av = -Rf/Rin.

102 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 6:
Run the simulation again, compare the output voltage and input voltage, the
voltage gain now is 10.

Step 7:
Change the input frequency to 100 kHz, compare the voltage gain. The gain drop
to 1.5 and the waveform changed to triangle that’s mean the input frequency
already beyond the cut-off frequency of the amplifier.

103 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 8:
To investigate the frequency response of the amplifier, use frequency response
graph mode.

Step 9:
Use voltage probe mode to measure the output voltage, drag the Vout probe into
the graph and edit the frequency graph.

104 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 10:
Simulate the frequency response by click on the graph until it change to red and
press space bar.

Step 11:
Analyze the frequency response by maximize the graph, The Cut-off frequencies
are the “corner points” of the frequency response plot, usually the point where
the response is down -3dB (or 0.5 of max power gain or 0.707 of max voltage
gain) compared to the mid-band signal level. From the response max gain =20dB
so -3dB = 17dB and the cutoff frequency now is =91.8kHz.

105 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Lesson 3.9
Title Transistor Biased Analysis Using Proteus VSM

Transistor Biased Analysis
Step 1:
Open Schematic capture or create New ISIS project and construct the schematic
as shown in figure.

Step 2:
By using DC generator mode set VCC supply for 12V and click OK.

106 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 3:
Use Sine generator mode to give an input signal for the amplifier, set Amplitude
to 1V and frequency to 50Hz and click OK.

Step 4:
By using Instrument Mode, select an oscilloscope to measure the input and
output signal by connecting it to IN and OUT terminal .

107 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 5:
Run the Simulation and adjust the oscilloscope to get the proper waveform
output.

Step 6:
By increasing and decreasing the RV1 value you can see the what happen when
biased is too high and when biased is too low.

Biased too High
108 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Biased too low
Step 7:
Use Graph Mode and select Frequency graph to investigate the frequency
response for this circuit and use Voltage probe mode to check the output voltage
for this amplifier, drag the probe mode into the graph.

109 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 8:
Edit Frequency graph by double click on the graph, set the reference to input
signal, start frequency at 0.01, stop frequency at 100MHz, interval by decades,
set option to always simulate and click OK.

Step 9
Right Click and select simulate graph or click at the graph until it turn red and
press space bar.

110 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 10:
From the Frequency response you can check the Bandwidth, fCL, fCH, Avmid,
and roll-off rates near fCL and fCH

111 | ECAD

3.0 Simulation of Analogue Circuits / Analogue System CHAPTER 3

Step 11:

Edit Frequecy graph and set Y scale to dB, simulate the graph and maximize the
graph to analyze the frequency response.From the graph Avmid =14.5dB -3dB =
11.5dB, so the Cutt-off freq = 11.5dB. so. fCL=430mHz and fCH=4.06MHz

fCL= 430mHz fCH= 4.06Mhz
112 | ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

CHAPTER 4
SIMULATION OF DIGITAL CIRCUITS

In This chapter, you‘ll learn more about:
 Apply the simulation result for digital simulation
analysis using the Truth Table.
 Construct the digital schematics circuit and simulate
the circuits using a particular simulation packages.

113 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

INPUT

4.1 Introduction To Simulation Of Digital Circuits

A digital circuit simulation is an event-driven, time-domain simulation.
You can define an arbitrary time step for your live digital simulation and
increment the simulation time discretely, one step at a time, and manually
change the state of the input(s) at each time step.

Through the experiment, students can learn the concept of digital circuit
simulation, applications of logic level simulation for combinational and sequential
logic circuits. Logic inputs can be represented as Digital Clocks and output can
be obtained by performing Time Domain Analysis. The analysis produced is
displayed as a timing diagram and later can be represented into a Truth Table.

Lesson 4.1
Title Combinational Logic Gate Circuit

U4 U1

A
NOT

AND U3

y
B

U2 OR

U5

AND

NOT

FIGURE 4.1: Combinational Logic Gate

114 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 1:
Open Proteus Schematic Capture create a new project name and save it in your
desired path and folder, click next.

Click 1
Click 2

 Starting or setup Proteus VSM Schematic Capture:

Click 1

115 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 2:
Open Schematic capture and pick an ACTIVE AND, NOT and OR gate from
component library, construct Combinational Logic Gate circuit in figure 4.1. Use
terminal mode to create a connector for each terminal.

Click Write the Double click
component
name

Step 3:
Pick Logic State from components library and Use Logic State to create input
logic to the circuit.

116 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 4:
Pick Logic Probe from components library Use logic probe to analyse the output
for the circuit.

Write the Double click
component
Click name

Step 5:
Draw the circuit in figure 4.1 on schematic capture.

Step 6:
Set the input A and B value manually using Logic state according to truth table
and monitor the output, y using Logic probe (Big).

117 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Logic probe (Big) Logic state
and check the output at logic
Step 7:
Run the simulation by pressing button,
probe.

Theory Simulation

Input Output Input Output

AB y AB y

00 0 00 0

01 1 01 1

10 1 10 1

11 0 11 0

TABLE 4.1 : Results for combinational logic gate 1

118 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 2:
Use logic probe to analyse the input and output for the circuit.

Step 3:
Use Dpattern Generator mode to create input logic to the circuit. Set generator A
to pattern type , initial state to 0,pulse width to 2 second, transition to continuous
sequence of pulse and bit pattern to standard high low pulse train.

119 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 4:
Use D pattern Generator mode to create input logic to the circuit. Set generator
B to pattern type, initial state to 0,pulse width to 4 second( multiply by 2),
transition to continuous sequence of pulse and bit pattern to standard high low
pulse train.

Step 5: and check the ouput at logic
Run the simulation by pressing button,
probe.

120 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 6:
By using graph mode, the analysis for this Logic circuit can be done by using
measuring the input and output voltage using probe mode, drag all the
measuring probe into the graph and start time to 0 and stop time to 10 second.

Double
click

Step 7:
Maximixe the graph to analyze the input and output of the Logic circuit 1.

121 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 8:
This circuit also can be analyze using oscilloscope, connect all the
measurement probe to Channel A, B, and y.

Step 9:
Run the simulation and set the voltage/division and Time/division to a suitable
value to analyze the circuit.

122 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Lesson 4.2
Title Half Adder Circuit

FIGURE 4.2: Half Adder Circuit

U2 S

A U1

B
XOR

C

AND

FIGURE 4.3 : Half Adder Circuit

123 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 1:
Open Schematic capture and pick an ACTIVE AND and XOR gate from
component library, construct Half adder circuit in figure 4.3. Use terminal mode
to create a connector for each terminal.

Step 2:
Use logic probe to analyse the input and output for the circuit.

124 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 3:
Use Dpattern Generator mode to create input logic to the circuit. Set generator A
to pattern type , initial state to 0,pulse width to 2 second, transition to continuous
sequence of pulse and bit pattern to standard high low pulse train.

125 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 4:
Use Dpattern Generator mode to create input logic to the circuit. Set generator B
to pattern type , initial state to 0,pulse width to 4 second( multiply by 2),
transition to continuous sequence of pulse and bit pattern to standard high low
pulse train.

126 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 5: and check the ouput at logic
Run the simulation by pressing button,
probe.

Step 6:
By using graph mode, the analysis for this half adder can be done by using
measuring the input and output voltage using probe mode, drag all the
measuring probe into the graph and start time to 0 and stop time to 10 second.

127 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 7:
Maximixe the graph to analyze the input and output of the Half adder circuit.

128 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 8:
This circuit also can be analyze using oscilloscope, connect all the measurement
probe to Channel A, B, C and D.

Step 9:
Run the simulation and set the voltage/division and Time/division to a suitable
value to analyze the circuit.

129 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Lesson 4.3
Title Full Adder Circuit- Using Sub Circuit Mode

FIGURE 4.4 : Full-adder Circuit

Step 1:
Open Schematic capture or create a new project and select sub circuit mode and
draw a block on schematic windows. Rename the block as FULL ADDER by
double click the block.

130 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 2:
Use Sub-circuit mode INPUT and OUTPUT to set input terminal and output
terminal for the block.

Step 3:
Right click on the block and select Go to Child Sheet or Ctrl+C.

131 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 4:
Construct the Full adder circuit using active AND, OR and XOR gate from
Component library. Use terminal mode to create input and output terminal and
make sure the terminal at the child sheet have a same name as the parent sheet.

Step 5:
Right click on the windows and select Exit to parent Sheet.

132 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 6:
Use Default terminal mode to set input and output connection to Logic Probe.
Use Dpattern Generator mode to create input logic to the circuit. Set generator
Cin to pattern type , initial state to 0,pulse width to 2 second, transition to
continuous sequence of pulse and bit pattern to standard high low pulse train.

Step 7:
Use Dpattern Generator mode to create input logic to the circuit. Set generator B
to pattern type , initial state to 0,pulse width to 4 second( multiply by 2), and A
to 8 second transition to continuous sequence of pulse and bit pattern to
standard high low pulse train by double click on generator terminal.

133 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 8: pressing button,and check the ouput at logic
Run the simulation by
probe.

Step 9:
By using graph mode, the analysis for this full adder can be done by using
measuring the input and output voltage using probe mode.

134 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 10:
Drag all the measuring probe into the graph and start time to 0 and stop time to
10 second. Simulate the graph by click on the graph until it turn red and press
space bar.

Step 11:
Maximize the graph to analyze the input and output of the Half adder circuit.

135 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

136 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Lesson 4.4
Title 4-2 Encoder Circuit- Using Sub Circuit Mode

FIGURE 4.5: 4-2 Encoder Circuit
Step 1:
Open Schematic capture or create a new project and select sub circuit mode
and draw a block on schematic windows. Rename the block as 4-2 ENCODER
by double click the block.

137 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 2:
Use Sub-circuit mode INPUT and OUTPUT to set input terminal and output
terminal for the block.

Step 3:
Right click on the block and select Goto Child Sheet or Ctrl+C. Construct the
Full adder circuit using active AND and NOT gate from Component library. Use
terminal mode to create input and output terminal and make sure the terminal
at the child sheet have a same name as the parent sheet.

138 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 4:
Right click on the windows and select Exit to parent Sheet.

Step 5:
Use logic state and logic probe to check input and output logic for this circuit
by typing it in the component library.

139 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 6:
Run the simulation by pressing button, Set the input value manually according
to encoder truth table and monitor the output using logic probe.

140 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Lesson 4.5
Title 2 – 4 Decoder Circuit- Using Sub Circuit Mode

Figure 4.6: 4-2 Encoder Circuit
Step 1:
Open Schematic capture or create a new project and select sub circuit mode
and draw a block on schematic windows. Rename the block as 2-4 DECODER
by double click the block.

141 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 2:
Use Sub-circuit mode INPUT and OUTPUT to set input terminal and output
terminal for the block.

Step 3:
Right click on the block and select Goto Child Sheet or Ctrl+C. Construct the
Full adder circuit using active AND and NOT gate from Component library. Use
terminal mode to create input and output terminal and make sure the terminal
at the child sheet have a same name as the parent sheet.

142 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 4:
Right click on the windows and select Exit to parent Sheet.

Step 5:
Use logic state and logic probe to check input and output logic for this circuit
by typing it in the component library.

Step 6:
Run the simulation by pressing button, Set the input value manually according to
encoder truth table and monitor the output using logic probe.

143 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 7:
To run the circuit Automatically Use D-pattern Generator mode to create input
logic to the circuit. Set generator A0 to pattern type , initial state to 0, pulse width
to 2 second, and generator A1 to 4 second transition to continuous sequence of
pulse and bit pattern to standard high low pulse train.

Step 8:
Run the simulation by pressing button, and check the ouput at logic probe.
Suppose you will get the same output as the manual input.

144 |ECAD

4.0 Simulation of Digital Circuits CHAPTER 4

Step 9:
By using Digital graph mode, the analysis for this full adder can be done by
using measuring the input and output voltage using probe mode.

Step 10:
Drag all the measuring probe into the graph and start time to 0 and stop time
to 10 second.

145 |ECAD