Tutorial for FPGA Beginners

Tutorial for FPGA Beginners Implemented by STEP FPGA Cloud-based IDE Included

i An Experimental Discovery of Digital Circuits Implemented by FPGA Copyright © 2022 by EVO-IN-MOTION Technology Ltd. All rights reserved. No part of this publication may be reproduced, distributed, or transmitted in any form or by any means, including photocopying, recording, or other electronic or mechanical methods, without the prior written permission of the publisher, except in the case of brief quotations embodied in critical reviews and certain other noncommercial uses permitted by copyright law. For permission requests, write to the publisher at the contact method below. Ordering Information: Quantity sales of the published workpiece. Special discounts are available on quantity purchases by schools, academic institutions, corporations, associations, and others. For details, contact the publisher at the information below. EIM Technology 180-6660 Graybar Rd, Richmond, BC, V6W 1H9 [email protected] www.eimtechnology.com EIM Technology is a registered trademark of EVO-IN-MOTION Technology Ltd.

ii PREFACE As one of the most demanding technology in electronics hardware engineering, FPGAs serve all purposes for digital design and play a key role in many advanced applications such as video & image processing, IC design function validation, aerospace & defense, telecom communications… However, one major challenge we face now is that most FPGAs including various types of FPGA development boards are designed for advanced users. Beginners often find extremely challenging or simply get lost when dealing with all sorts of hardware configurations and environmental setup for the boards. If my statistics was correct, most people first heard of FPGAs in colleges while learning computer architecture or digital circuit design. Regardless the invisible high technology behind, FPGA is just a tool and the essence of learning is more about digital design. To take our first step, we always start from the basic concepts of Logic Gates and can eventually go with complex techniques such as Direct Digital Synthesis, digital modulation/demodulation, microprocessor design. Having undergone a painful learning process in school where a team of guys sitting in front of an expensive and complex FPGA board with no idea how it is related to the concepts taught in the lecture, I realized that an efficient way of learning is by examples and people do need to get things work first before throwing them with lots of equations and theories. With this philosophy, we designed a neat and compact FPGA board, along with this illustrative tutorial with a big emphasis on the practical engineering experiments and project building. The goal of this learning kit aims to help beginners take their first baby step to uncover the beauty behind digital design. I am sure there are lots of rooms to improve on this project, and mistakes or imperfections may occur here and there in this book. But I would acknowledge the great value and efforts invested on this whole project by EIM and STEP, particularly the FPGA engineers who contributed so many tested Verilog codes, the IT developers who designed and maintained the operation of WebIDE tool and the Graphics designers who managed the style and formatting of the book. As a growing team with sense of missions, we plan to publish a series of more diverse tutorials and projects covering different applications and levels of complexity. By the moment you read this book, our team sincerely wish you enjoy a pleasant learning experience with this STEPFPGA board. Daniel Cao Founder of EIM Technology July 2022 All Verilog codes in this book including the implementation test files can be found in our Github resource at: https://github.com/eimtechnology

iii Table of Contents Chapter 1: Review of Digital Circuits Fundamentals ..................................................................... 1 1.1 Basic Concepts ...................................................................................................................... 1 1.2 Logic Gate Circuits................................................................................................................ 9 1.3 Combinational Logic Circuits.............................................................................................. 13 1.4 Sequential Logic Circuit...................................................................................................... 19 1.5 State Machine ...................................................................................................................... 24 1.6 Digital Analog Conversions ................................................................................................ 28 Chapter 2: Tools for Digital Circuit Experiments......................................................................... 35 2.1 Circuit Simulation Tools...................................................................................................... 35 2.2 Digital Logic ICs................................................................................................................. 38 2.3 Digital Module Implementation via FPGA.......................................................................... 42 2.4 Building Digital Modules with 74 series chips.................................................................... 49 Chapter 3: FPGA Implementation of Digital Modules................................................................. 53 3.1 Implement a 3-input XOR circuit ........................................................................................ 53 3.2 Implement a 1-bit Full Adder .............................................................................................. 58 3.3 Implement a 2-4 Decoder .................................................................................................... 61 3.4 Implement a 3-8 Decoder .................................................................................................... 65 3.5 Drive a 7-segment display ................................................................................................... 70 3.6 Implement a Decimal Counter............................................................................................. 74 3.7 Implement a Frequency Divider.......................................................................................... 81 Chapter 4: Build 74xx Chips with FPGA ....................................................................................... 87 4.1 Implement a 74HC08 Quad 2-input AND gate ................................................................... 87 4.2 Implement a 74HCF283 4-bit Binary Full Adder................................................................ 89 4.3 Implement a 74HC138 3-8 Decoder.................................................................................... 91 4.4 Implement a 74HC74 Dual Positive Edge Triggered D-Flipflop ........................................ 93 4.5 Implement a 74HC165 8-bit Parallel-load Shift Registers.................................................. 96 4.6 Implement a 74HC393 Dual 4-Stage Binary Counter......................................................... 97 Chapter 5: Some Projects with FPGAs......................................................................................... 101 5.1 An 8-bit LED Chaser..........................................................................................................101 5.2 A Simple Traffic Light Control System .............................................................................103

iv 5.3 A More Complex Traffic System.......................................................................................107 5.4 FPGA for Elevator Control.................................................................................................119 5.5 Implement a Digital Locker................................................................................................135 5.6 A Simple Electronic Piano .................................................................................................144 5.7 A More Complex Electronic Piano ....................................................................................155 5.8 Sending data through UART..............................................................................................165

Chapter 1 1 Chapter 1: Review of Digital Circuits Fundamentals 1.1 Basic Concepts Numbers are the abstractions of the real world. In human civilization, we express, describe, and understand the world with decimal numbers. In electronics, digital circuits are built upon the concepts of binary numbers and only deal with number zeros and ones. This section reviews the fundamental knowledge of digital circuits, starting from digital signals, binary numbers then gradually go over concepts such as modules, Truth Tables, and Boolean algebra. Analog Signals and Digital Signals A signal is a carrier that conveys information. In electronics, signals may be divided into analog signals and digital signals. An analog signal is a continuous signal in time domain, such as a sine wave, triangular wave, or even noise to some extent all belong to analog signals. For digital circuits, all analog values are quantified into high-level (H) and low-level (L), which means digital signals are discrete and only jump between High and Low levels. Figure 1.1.1 compares the two signal types. Figure 1.1.1 Comparison of Analog and Digital Signals Physically, digital signals are generated by digital circuits, particularly by the Integrated Circuits (IC) which often referred as chips. There are two major technologies being used to fabricate digital ICs: Transistor-Transistor Logic (TTL), and Complementary Metal Oxide Semiconductor (CMOS). Figure 1.1.2 shows an example of the internal structure of the gate circuit for the two architectures. Figure 1.1.2 Logic Gate Designed with TTL and CMOS Technologies

A Tutorial for FPGA beginners 2 Compared with TTL technology, CMOS is the mainstream to fabricate high-density integrated circuits and low-power design due to its smaller unit size and higher power efficiency. This part belongs to the field of microelectronics design thus not covered in this book. Number System Most digital circuits use 5V and 3.3V to power. Chips using different manufacturing processes may have different ‘understandings’ for High and Low levels. For example, when the power supply is 5V, a TTL based chip may treat input signal exceeding 2.0V as a High, while a CMOS based chip may treat the level above 2.5V as a High. Figure 1.1.3 shows a rough range to determine logic levels for different power supply voltages. Figure 1.1.3: Logic level standards used in TTL and CMOS processes Regardless of the fabrication technology, we always define the High as 1 and Low as 0. In this way, we can use binary numbers as an abstraction of digital signals. Another commonly used number system in digital circuits and computing system is Hexadecimal. Table 1.1 compares these two number systems with our familiar decimal system. Table 1.1: Conversions between several common number systems Binary Hexadecimal Decimal 0 0 0 1 1 1 10 2 2 11 3 3 100 4 4 101 5 5 110 6 6 111 7 7 1000 8 8 1001 9 9 1010 A 10 1011 B 11 1100 C 12 1101 D 13 1110 E 14 1111 F 15

Chapter 1 3 Practically, we can simply use a programmer calculator to convert numbers, as shown in Figure 1.1.4. Where HEX stands for hexadecimal, DEC for decimal, OCT for octal (not commonly used in this book), and BIN for binary. In this example, a decimal number 856 is equivalent to binary number of 001101011000 or hexadecimal number of 358. Figure 1.1.4: Using Windows calculator to compute decimal to binary number Digital Signals and Data All signals should contain specific information. In a digital system, the smallest unit of information or data is called bit. In terms of data size, a 1-bit size data contains one binary number, thus have 21 combinations (0/1); a 2-bit size data may have 22 or 4 combinations. By analogy, N-bit data can contain a combination of 2N combinations of binary numbers. In Table 1.2 you may realize that the maximum possible information contained in different bit-width data goes up dramatically. Table 1.2: Maximum possible information stored in different bit-size data Bit-size Information size 2 4 4 16 8 256 10 1,024 12 4,096 16 65,535 24 16,777,215 For complex digital circuit systems (such as a computer), it is obviously inefficient to describe data size in bits, so people came up with Bytes. By definition, 1 Byte contains 8 bits of data. The relationship between a Byte and bit is shown in Figure 1.1.5.

A Tutorial for FPGA beginners 4 Figure 1.1.5: Relationship between a Byte and Bit Depending on the order arranged of the bits, the Most Significant Bit (MSB) indicates the bit of largest value whereas Least Signiant Bit (LSB) has the least effect on the value of the binary. To convert the above binary number into decimal number we get: () + () + () + () + () + () + () + () = The combination of binary numbers corresponds to the maximum amount of information in which a data may possibly contain, and this size is also referred as data capacity. The data capacity in one byte is 28 =256. In addition to bytes, other units include KB, MB, GB, etc. are commonly used to describe larger capacity, as listed in Table 1.3. Table 1.3: Digital unit conversions Bit as unit Byte as unit Other units 210 bit 1024 B = KB (Kilobyte) 220 bit (1024) 2 B = 1024 KB = MB (Megabyte) 230 bit (1024) 3 B =1024 MB = GB (Gigabyte) 240 bit (1024) 4 B =1024 GB = TB (Terabyte) For example, in an Operating System, we have heard about 32-bit or 64-bit Operating Systems. A 32- bit Operating System may handle 232 ≈ 4.3×109 amount of data information and thus the maximum memory capacity is 4GB. The 64-bit operating system can handle 264 ≈ 1.8×1019 of data information which is almost equivalent to an infinite data storage capacity though in practice you do not need that much information. Digital Modules In digital electronics, any circuit with specific functionalities can be regarded as a Module. Figure 1.1.6 shows a Module represented by a block diagram with inputs, outputs and internal structure. In block diagram notation, input ports are usually placed on the left and output ports are placed on the right.

Chapter 1 5 Figure 1.1.6: Basic elements of a digital circuit module Modules can be interconnected in the circuit. A digital system may compose only one module or many sub-modules (you may also call them sub-entities). As shown in Figure 1.1.7, a large Module with many sub-modules could be more complex, however, regardless of its functionality and complexity, a Module should always contain inputs, outputs, and the internal structure. Figure 1.1.7: Combination of Modules The input and output ports of the Module can be 1-bit or multi-bits in size. As shown in Figure 1.1.8, the input and output of this module are multi-bits. If the number of bits at the input end is m, and the number of bits at the output end is n, then for the purpose of describing this Module, we can write "mn module" for which the inputs are usually placed in front. For example, a "3-8 Decoder" is a module with a Decoder function, which contains three input and eight output signals. Figure 1.1.8: Block diagram with Multi-bit Input and Multi-bit Output Regardless of how exactly the internal structure being made, the basic definition of all digital circuit Modules must have the following three parameters to be recognized:

A Tutorial for FPGA beginners 6 1. The name of the Module 2. The input(s) of the Module 3. The output(s) of the Module We will repetitively emphasize this concept since Chapter 3 in this book while we begin to write the code for FPGA experiments. Truth Table Truth Table is often used to describe the logic functions of a Module. A Truth Table is a tabular form that lists the expected output results corresponding to each binary combination of all input signals. It presents a quick overview or summary of the logic functions of the Module. For example, Table 1.4 is a Truth Table for a custom-defined 2 inputs - 3 outputs module. Table 1.4: Example Truth Table for a 2-input 3-output module Inputs Outputs A B Y2 Y1 Y0 0 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 The Truth Table uses binary number system, so the number of rows is determined by the input bitwidth of the Module. Reasonably, a Truth Table is only suitable for Modules with few input signals, usually four or less inputs. For example, a 4-inputs Module has 24 =16 lines if a Truth Table is constructed. For Modules with more input bit-width, e.g., 8 inputs, it is obviously not practical to write all 28 =256 rows for the Truth Table. Boolean Algebra Truth Tables can be further simplified in equational forms, and therefore some knowledge background from Boolean Algebra is needed. Boolean Algebra is a branch of algebra that performs logical operations of binary numbers only. In Boolean Algebra, there are three fundamental operations: NOT operation, AND operation, OR operation: = � NOT operation. Also written as Y=A’, which means the output Y is opposite to the input A = () AND operation. When all inputs are 1, the output is 1; otherwise, the output is 0 = + OR operation. When either of the input is 1, the output result is 1

Chapter 1 7 To convert the Truth Table into Boolean Algebra expression, as shown in Figure 1.1.9, we need to pick out all rows for which the outputs contain ones. In the example below we need to pick row 1 and row 3 since these rows have output one. Figure 1.1.9: Conversion from Truth Table to logical expression To start, we OR all different rows which gives Y = (row1) + (row3). Then we AND each row, therefore having Y = (A’B’) + (AB’). The Boolean expressions for Table 1.3 can be written as: = � = �� + � + = � + Note that the above expressions are not in the simplest form since the above expressions can be further reduced to: = � = � + = A simplified logical expression can optimize the hardware structure, improve the propagation speed among Modules and reduce the hardware cost due to less components. In next section, we will briefly introduce Karnaugh map to simplify logic expressions in a graphical approach. Karnaugh Map Karnaugh map, or K-map, was a method firstly proposed by the American engineer M. Karnaugh. It is an efficient way to simplify logic expressions by means of graphics. Normally, K-map may include two, three, or four variables, as shown in Figure 1.1.10.

A Tutorial for FPGA beginners 8 Figure 1.1.10: Three Karnaugh maps with different inputs In this example, we will illustrate the method of using K-map to simplify formula (1): = � + � + � + � (1) Step 1: Determine the number of variables contained in the logic expression. Since it has variables A, B, C, we use three-variable K-map, therefore draw the table as below: Step 2: You need to fill some ones. Let us start from AC’. In Figure 1.1.11 ❶: since A is true, so we highlight the entire row for A is 1; and for C’ which indicate false, we only highlight the two columns corresponding for C is 0 (thus C’ will be 1). If the two highlights are intersected, we fill a 1 there. Figure 1.1.11: Fill the Karnaugh map with logical expressions

Chapter 1 9 For ❷ is the same: highlight the entire row for A is false, and the two columns for C is true, then we get two more 1s filled. For ❸, we get a single 1 to fil since it has to meet condition where A is true, B is true and C is false. And you will be figuring out ❹ by your own. Once you got all 1(s) filled the final K-map is shown in Figure 1.1.12: Figure 1.1.12: Expression of formula (1) by way of Karnaugh map Step 3: Now comes to simplifications. To do so, we will circle all largest adjacent rectangles containing multiple of 2 numbers of 1(s), and that corresponding to circle1 and circle2 in the figure below. If by the end you have a single 1 left, it means no further simplifications can be done, and you must circle this term as well, which is circle3. Circle 1 can be written as AB’ because it is located at ‘A is 1, B is 0 and C is do-not-care’. Circle 2 can be written as A’C as it locates at ‘A is 0, C is 1, B is do-not-care’. You will complete circle3 by yourself. Be aware that K-map is not unique. For example, the simplified K-map below is logically equivalent as the previous. In this book we only show a quick review of the K-map technique, and the main idea is to understand a graphical way to simplify Boolean expressions containing more input variables. You can find plenty of great examples and in-depth theories in textbooks or technical articles online. 1.2 Logic Gate Circuits Logic Gates usually carry specific logic functions which serve as the fundamental building blocks in digital circuits. There are many types of Gates, here we introduce some commonly used types: AND, OR, NOT, NAND, NOR, XOR.

A Tutorial for FPGA beginners 10 AND Gate AND Gate is one of the most common Gates. It has two symbolic expressions: American Standard (left) and IEEE (right) standard as shown in Figure 1.2.1. A basic AND Gate contains 2 inputs and 1 output. Figure 1.2.1: AND Gate Table 1.5 is the Boolean expression and Truth Table for an AND Gate. Table 1.5: Truth Table of AND gate = Inputs Output A B Y 0 0 0 0 1 0 1 0 0 1 1 1 There are also 3-inputs and 4-inputs AND Gates being used which are essential combinations of the basic 2-inputs ANG Gate. Unless otherwise specified, all AND Gates has a single output signal. OR Gate The OR Gate is another commonly seen Gate, and its electrical symbol is shown in Figure 1.2.2. The basic OR Gate also has 2 inputs and 1 output. Figure 1.2.2: OR Gate Table 1.6 is the Boolean expression and Truth Table for OR Gate. Table 1.6: Truth Table of the OR gate = + Inputs Output A B Y 0 0 0 0 1 1 1 0 1 1 1 1

Chapter 1 11 NOT Gate NOT Gate, also known as Logic Inverter, is the only gate containing 1 input and 1 output. The symbol of the NOT gate is shown in Figure 1.2.3. For convenience, NOT gates are often represented by only a circle in digital circuits and can be combined with other Gates. Figure 1.2.3: NOT Gate Table 1.7 below is the logic expression and Truth Table of the NOT Gate. Table 1.7: Truth Table of NOT gate = � A Y 0 1 1 0 NAND Gate The NAND gate is essentially the combination of an AND Gate and NOT Gate, and its symbol is shown in Figure 1.2.4. The small circle placed at the output port in the figure is equivalent to a NOT gate. The basic NAND gate has 2 inputs and 1 output. NAND gate is extremely important in digital circuits since any Boolean function can be implemented by using a combination of NAND gates. For example, the flash memory in computers is realized essentially by huge amount of NAND Gates only. Figure 1.2.4: NAND Gate The Boolean expression and Truth Table of the NAND Gate can be found in Table 1.8. The output is the opposite value of the AND Gate. Table 1.8: Truth Table of NAND gate = ���� Inputs Output A B Y 0 0 1 0 1 1 1 0 1 1 1 0

A Tutorial for FPGA beginners 12 NOR Gate A NOR Gate combines an OR Gate and a NOT Gate. Its expression symbol can refer to Figure 1.2.5. Likewise, the basic NOR Gate has 2 inputs and 1 output. Figure 1.2.5: NOR Gate The Boolean expression and Truth Table of NOR Gate are shown in Table 1.9. Table 1.9: Truth Table of the NOR gate = ���+���� � Inputs Output A B Y 0 0 1 0 1 0 1 0 0 1 1 0 XOR Gate XOR Gates are often used in arithmetic operations such as addition, subtraction, multiplication and division. The symbol of the XOR Gate is shown in Figure 1.2.6. Figure 1.2.6: XOR Gate For XOR gates, when the two input signals are different, the output result is 1, otherwise the output is 0. The Boolean expressions and Truth Table are shown in Table 1.10. The mathematical operator for XOR Gate operation is ⊕, which is equivalent to Y=A’B+B’A. Table 1.10: Truth Table of XOR gates = ⊕ Inputs Outputs A B Y 0 0 0 0 1 1 1 0 1 1 1 0

Chapter 1 13 XNOR Gate The XNOR Gate is the opposite of the XOR gate. The output is 1 when the two inputs are the same, otherwise, the output is 0. See Figure 1.2.7 for the expression symbol of the XNOR gate. Figure 1.2.7: XNOR Gates The logical expression and Truth Table of the XNOR gate can be found in Table 1.11. The symbol for the XNOR gate is ⊙. Table 1.11: Truth Table of XNOR gates = ⊕�������� � = ⊙ Inputs Output A B Y 0 0 1 0 1 0 1 0 0 1 1 1 1.3 Combinational Logic Circuits Combinational circuits are made from basic AND, OR, NOT, NAND Gates that are interconnected to produce more complicated circuits such as Decoders, Adders or Multiplexers. Combinational circuits are also featured as memoryless circuits whose outputs at any instants depend only on the combination of its inputs. Combinational circuits are time independent. Comparators A Comparator is a simple Module in combinational logic, and it compares the magnitude between two binary numbers. For two binary numbers A and B, we may have A greater than B, A less than B or A equals to B. Using 3 output channels to represent the 3 conditions gives: • When A=B, Y0 (A=B) is true • When A>B, Y1 (A>B) is true • When A<B, Y2 (A<B) is true Writing the above conditions in a Truth Table as shown in Table 1.12,

A Tutorial for FPGA beginners 14 Table 1.12: Truth Table for binary comparators Inputs Outputs A B Y2 (A<B) Y1 (A>B) Y0 (A=B) 0 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 Binary Adders The Adder is the fundamental unit of all arithmetic circuits. They can be divided into 1-bit Adders and multi-bit Adders. A 1-bit Adder adds two 1-bit binary numbers, and the operation process can be divided into four cases, as shown in Figure 1.3.1: Figure 1.3.1: Four cases when adding two 1-bit binary numbers When adding binary numbers, in addition to the sum, you may also get a carry bit, so the output port needs to contain two signals, sum and carry. Table 1.13 is the Truth Table for adding two 1-bit binary numbers. Table 1.13: Truth Table for the addition of two 1-bit binary numbers Input Output A B sum Co 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Table 1.13 shows the logic of a Half Adder, which neglects the carry generated from lower bit. Thus a Half Adder only has 2 input signals for the two binary addends, A and B. According to the above Truth Table, the logical expression of sum and carry (Co) can be written: = ⊕ = Figure 1.3.2 is a block diagram of a 1-bit Half Adder. It contains two input signals and two output signals.

Chapter 1 15 Figure 1.3.2: Block diagram and structure of a 1-bit half-adder A Full Adder is more useful in practice. A Full Adder takes account of the carry bit generated from the addition of previous Full Adders, therefore has 3 input signals. Figure 1.3.3 shows a cascaded connection of four 1-bit Full Adder. You should not be surprised that this is also called a 4-bit Full Adder. Figure 1.3.3: Addition mechanism of a 4-bit Full Adder The Truth Table of a 1-bit Full Adder is shown in Table 1.14. Table 1.14: Truth Table for a 1-bit Full Adder Input Output CIN A B Sum CO 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 The logic expressions of sum and carry (Co) can be derived from the Truth Table of the Full Adder. In Section 3.2, we will also verify the logic function of the Full Adder with actual FPGA experiments.

A Tutorial for FPGA beginners 16 = ⊕ ⊕ = ( ⊕ ) + Figure 1.3.4: Block diagram and logic expression of 1-bit Full Adder Encoders An Encoder converts data from many bits to fewer bits. For binary Encoders, a piece of information containing 2N input signals can be encoded with only N output signals. The naming of the Encoder usually follows the convention of 2N-N, such as 8-3 Encoder, 16-4 Encoder and so on. For a simple 4- 2 binary Encoder, its Truth Table is given in Table 1.15. Table 1.15: Truth Table for binary 4-2 Encoder Input Output I3 I2 I1 I0 Y1 Y0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 As seen from the Truth Table, a binary Encoder does not allow for condition where the multiple inputs are logic high simultaneously, otherwise the system will report an error because no corresponding output can be found. To overcome this disadvantage of strict requirements on the input side, priority Encoders were more often used. The Truth Table of a 4-2 priority Encoder is seen in Table 1.16. Table 1.16: Truth Table for priority 4-2 Encoders Input Output I3 I2 I1 I0 Y1 Y0 0 0 0 1 0 0 0 0 1 X 0 1 0 1 X X 1 0 1 X X X 1 1 The ‘X’ in Truth Table means Do-not-care thus can be 0 or 1. For a 4-2 priority Encoder, the output is only affected by the MSB of the input thus reduces the complexity of hardware design. Figure 1.3.5 is an internal structure of a 4-2 priority Encoder, which only contains two OR Gates.

Chapter 1 17 Figure 1.3.5: Structure of 4-2 priory Encoder Decoders Opposite to the Encoder, a Decoder ‘decompresses’ data. The data mapping of a Decoder also follows N-2N mechanism, so we have 2-4 Decoders, 3-8 Decoders, 4-16 Decoders and so on. The simplest 2- 4 Decoder contains 2 inputs and 4 outputs. The Truth Table of a 2-4 Decoder is given in Table 1.17. Table 1.17: Truth Table for 2-4 Decoder Inputs Outputs A1 A0 Y3 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 = �� = � = � = According to the above logic expression, Figure 1.3.6 shows the hardware structure of the 2-4 Decoder. Figure 1.3.6: Structure of 2-4 Decoder Multiplexer Multiplexer (MUX) is also a commonly seen module in digital circuits. A Multiplexer has a special input port called input selection signals which allows only the selected inputs to pass through. Figure 1.3.7 shows a module representation of a 2 channel Multiplexer, or MUX2. When the selection signal

A Tutorial for FPGA beginners 18 S is 0, whatever signal connected on D0 channel will pass to the output Y. When S becomes to 1, the other channel connected to D1 is active. Figure 1.3.7: Illustration of a MUX2 operation Therefore, a MUX4 has 4 input channels with 2 selection signals, a MUX8 has 8 input channels and uses 3 selection signals, etc. The Truth Table of a MUX4 is listed in Table 1.18. Table 1.18: Truth Table for MUX4 Inputs Output X S0 S1 Y D0 0 0 D0 D1 0 1 D1 D2 1 0 D2 D3 1 1 D3 Beside the Truth Table, we can also derive the Boolean expression of the output and each input variable: = ( ′ ′ ) + ( ′ ) + ( ′ ) + () According to the Boolean expression above, the structure of a MUX4 is drawn in Figure 1.3.8. Figure 1.3.8: Structure of MUX4

Chapter 1 19 1.4 Sequential Logic Circuit In comparison to combinational logic circuits learned in the previous section, sequential logic circuit is a type of logic circuit whose outputs depend not only on the present value of its input signals but also on the sequence of past inputs, therefore sequential circuits are time dependent. The well-known and commonly used sequential logic circuits include Flip-Flops, Registers and Counters. RS Latch Latch is a level triggered module in which its output value is dependent not only the input signals, but also the previous output result. Figure 1.4.1 is a block diagram of a RS Latch, which is constructed with NOR Gates. This way of connecting the output signal back to the input is called feedback. Having a feedback connection in the hardware design is a flag to determine whether a circuit is sequential, since this mechanism allows output signal further influences the inputs time by time. Figure 1.4.1: Structure of the RS latch The hardware connection of a RS Latch helps us analyze the logic behavior. We often describe a sequential logic using a State Table. In comparison to a Truth Table, the output in a State Table has current state, noted as Q, and next state, noted as Qnext. Table 1.19 uses a Sequential Table to describe the logic behavior of a RS Latch. Table 1.19: State table of the RS Latch Inputs Current Output Next Output Actions S R Q Qnext 0 0 0 0 LATCH 1 1 0 1 0 0 RESET 1 0 1 0 0 1 SET 1 1 1 1 0 ? Invalid 1 ? The above State Table can be literally described in the following texts: • If S=1, R=0, then Qnext = 1, this action is called Set, indicating the output will become High

A Tutorial for FPGA beginners 20 • If S=0, R=1, then Qnext = 0, this action is called Reset, indicating the output will become Low • If S=0, R=0, then Qnext = Q, this action is called Latch, indicating the current output is Held However, we should avoid the condition when both R and S equal to 1 since the output result is uncertain. Further improvements to avoid getting into uncertain or Invalid conditions are made on other types of latches such as D Latch, T Latch, JK Latch…Nevertheless, latch is not widely used in the context of this book therefore we will emphasize anther of its variant, Flip-Flop. RS Flip-Flop Flip-Flops are edge triggered and the triggering signal is usually periodical square waves called clock signals. Figure 1.4.2 shows the structure of a RS Flip-Flop, which is essentially built on top of a RS Latch with additional AND Gates to enable clock triggering. Figure 1.4.2: Clock-triggered RS Flip-Flop structure The State Table to describe a RS Flip-Flop is given in Table 1.20. For edge triggered Modules, the symbol ↑ represents the rising edge of the clock whereas ↓ represents the falling edge of the clock. Observing the internal structure of a RS Flip-flop, we see that the input signals can only pass to the circuit and take effective when the clock signal has been edge triggered. Table 1.20: RS Flip-Flop state diagram Inputs Current Output Next Output Actions CLK S R Q Qnext ↑ 0 0 0 0 LATCH 1 1 ↑ 0 1 0 0 RESET 1 0 ↑ 1 0 0 1 SET 1 1 ↑ 1 1 0 ? Invalid 1 ? Still, we need to avoid the Invalid condition when both R and S is High in a RS Flip-Flop, but this disadvantage has been overcome in the D Flip-Flop.

Chapter 1 21 D Flip-flop D Flip-Flop solved the disadvantage of system uncertainty caused by S and R being simultaneously set to 1 in a RS Flip-Flop, so it is also one of the most used Flip-Flops in digital circuits. Table 1.21 is the State Table for a D-type Flip-Flop. Table 1.21: State Table for a D Flip-flop Inputs Current Output Next Output Actions CLK D Q Qnext ↑ 0 0 0 Hold 1 0 ↑ 1 0 1 Write 1 1 The working principle of D Flip-Flop is described as: • When clock is edge triggered and D = 0, then Qnext = 0, meaning to Hold the data • When clock is edge triggered and D = 1, then Qnext = D, meaning to Write the data Figure 1.4.3 shows the structure of a D Flip-Flop. We can see a D Flip-Flop is similar to the RS FlipFlop but some modifications are made at the input side so that only a single data input D is available. This design eliminates the trouble where both R and S in the previous RS Flip-Flop were set to High simultaneously. Figure 1.4.3: Structure of D Flip-Flop Registers A Register is an often-heard sequential logic circuit which can temporarily store data. A Register is essentially composed of Flip-Flops. Each Flip-Flop can store 1-bit data, thus a Register to store an Nbit width is composed of number of N Flip-flops. You may come back to this again when working with experiments in Section 3.6 and Section 3.7. Figure 1.4.4 is an example of a 4-bit Register which is made of four D Flip-Flops that are all edge trigger by a same clock signal (also called synchronized).

A Tutorial for FPGA beginners 22 Figure 1.4.4: Structure of a 4-bit Register Cascading the Flip-Flops can create a path in which the written data can traffic to the succussing FlipFlops, thus we will get a Shift Register. Figure 1.4.5 shows the structure of a 4-bit Shift Register: the input port is connected to the DIN signal, and the data is shifted to the right after each clock trigger. If the final output is obtained on each Flip-Flop, it is called Parallel Output; otherwise it is called Serial Output if the output data is acquired at the final Flip-Flop. Figure 1.4.5: Structure of a 4-bit Shift Register Counters For a Register, if the written data exceeds its capacity, the last input data will be lost due to overflow. A Counter simply connects the final Flip-Flop on the last bit to the initial Flip-Flip on the first bit, and this way forms a loop. Figure 1.4.6 gives the structure of a Ring Counter, which looks very similar to a 4-bit Shift Register except the Counter has no other inputs other than the clock signal. Figure 1.4.6: Structure of Ring Counter The number of different output states in which a Counter can produce is called the Modulus of the counter, or MOD. For example, the MOD of the Ring Counter in Figure 1.4.6 has MOD-4. By drawing the State Diagram as shown in Figure 1.4.7, we see that if it has an initial value of Q0Q1Q2Q3 = 1000, the entire loop will go through four different output states:

Chapter 1 23 Figure 1.4.7: State Diagram of a MOD-4 Ring Counter with initial state 1000 Theoretically, the maximum MOD for an N-bit Counter is 2N, which indicates that a perfectly designed 4-bit Counter should have 16 unique output states, or MOD-16. Obviously, the structure of a 4-bit Ring Counter has incurred lots of ‘MOD waste’. If we slightly modify the Ring Counter and connects the input to the inverted output of Q3, as shown in Figure 1.4.8, this forms a new Counter called Twisted Ring Counter. Figure 1.4.8: Structure of Twisted Ring Counter Surprisingly, this slight change results in MOD-8 for a 4-bit Twisted Ring Counter. As seen in the State Diagram shown in Figure 1.4.9, assuming an initial state of Q0Q1Q2Q3 = 1000 was given, a complete loop of the new Counter undergoes eight unique output states. Thus, a Twisted Ring Counter has MOD of 8. Figure 1.4.9: State Diagram of a MOD-4 Twisted Ring Counter with initial state 1000 In practical implementations, it is extremely difficult to fix the initial output states to a certain value for each operation, and this may result in startup failures. Taking the Ring Counter as example, if the initial output state is 0000 or 1111, the Counter will simply stay at this state forever. Or if the initial

A Tutorial for FPGA beginners 24 output states are 1010 or 0101, then the Counter only has MOD2, as illustrated in the State Diagram shown in Figure 1.4.10. Figure 1.4.10: State diagram of the ring counter with other initial states To solve the issue of uncertain initial output states, a self-starting circuit is often designed to ensure that the Counter will eventually return to the desired initial state after a number of clock triggering cycles, and thus the structure utilizes feedback mechanism as shown in 1.4.11. We will try out different Counters in FPGA experiments in Section 3.6. Figure 1.4.11: Self-starting of the counter by adding a feedback circuit 1.5 State Machine The State Machine is an important concept in sequential circuits, and it is also a commonly used hardware design tool. In this section we review the basic concepts of a state machine, and you will see lot of State Machine practices while working on the actual projects in Chapter 5. State Machines and Flowcharts Finite State Machine (FSM) is a mathematical model that visually describes the rules of how things work. While describing a sequence of related events or rules, FMS chart presentation is usually more concise than textual descriptions. For example, Figure 1.5.1 describes the general process of obtaining a driver’s license by means of an FSM.

Chapter 1 25 Figure 1.5.1: Process of getting a driver's license through an FSM chart Here we divide the process of getting a driver's license into four states: • No license • Paper Test • Road Test • Obtaining the license The transition between each state depends on the corresponding trigger conditions. For example, if you do not have a driver license and not preparing for a test, then you will stay at the No License state forever; once you enrolled for a test, the process takes you to the next state of Paper Test. Unless you passed the test and thus move forward to another state of Road Test, you will stay in this condition for good. Since there is no direct connection between No License and Road Test, you cannot skip the Paper Test, at least in British Columbia, Canada. Binary Representation of State Machines The diagram in Figure 1.5.1 can be furthered simplified in a binary encoded State Machine diagram in which all states are uniquely represented in sequenced binary numbers, as shown in Figure 1.5.2. Figure 1.5.2: Binarizing the state machine of the driving test process

A Tutorial for FPGA beginners 26 The four possible states can be fully represented by a total of 22 =4 binary numbers listed in Table 1.22. Table 1.22: Conversion of the four states into the corresponding binary codes State Binary Code No Licence 00 Paper Test 01 Road Test 10 With Licence 11 Table 1.23 lists the triggering conditions for each state. Table 1.23: Trigger jumps between states Current State Trigger Condition Next State 00 enroll = 1 01 01 pass = 1 10 10 pass = 1 11 11 legal = 0 00 And Table 1.24 specifies the corresponding output results when the current process stays in different states. Table 1.24: Corresponding outputs in each state States Output 00 driver = 0 01 driver = 0 10 driver = 0 11 driver = 1 State Machine Design Ideas To construct a state machine, we should divide the whole process or event of a system into a finite number of states. A valid state machine must meet the following three criteria: • The entire process can be divided into finite number of states (at least two) • Each state must be triggerable, meaning an action has to be taken for different input conditions • There exists only one state corresponding to the event that occurs at any given moment Using the above criteria, we try to describe some commonly seen processes or events with state machine design as seen in Table 1.25. Note that not all events can be described via an FSM.

Chapter 1 27 Table 1.25: Descriptions of the events with FSM Event Description State machine design The process of traffic signal Can be described via a FSM The entire process can be breakdown into certain number of states correpsonding to the waiting time of different lights; triggering condition is time; at any moment, the traffic light only entires into a single unique state A vending machine with 4 types of running mechanisms Can be described via a FSM The entire process can be breakdown into certain number of states correpsonding to the 4 types of running mechamisms such as vending, money collection, user promotion message…; triggering conditions could be time or the sensor feedback signals or user inputs; at any moment, the vending machine only entires into a unique state, e.g. either it is vending or promoting user information Changes in the height of the sun over the course of a day Cannot be described via a FSM The height of the sun is changing continuously thus cannot be divided finite number of states Operation of a three-story elevator Can be described as a FSM The entire process can be breakdown into certain number of states corresponding to the actions such as ascending, decending, halt...; triggering conditions could be time or sensor feedback signals or user inputs; at any moment, the elevator only entires into a unique state, e.g. either descending or hault or an action specified in the elevator design

A Tutorial for FPGA beginners 28 1.6 Digital Analog Conversions A modern complex electronics system usually contains both analog and digital circuits. Analog circuits deal with the real physical world thus often seen in power, sensors, RF related designs. Digital circuits are smart and good at handling logical and mathematical computations so they are more capable for signal processing and logic control tasks. To have analog and digital circuits interface with each other, the two parts: Analog to Digital Converters (ADC) and Digital to Analog Converters (DAC) play a crucial role. We will study the fundamental principle of the two components and follow up with some real projects in Chapter 5. The realization circuits of ADC and DAC belong to microelectronics field thus are not covered in this book. Analog to Digital Converter An electronics system senses the physical quantities in nature such as sound, light, force, electromagnetic fields with sensors. In electronics, a sensor may refer to a type of engineered material which converts the physical quantities such as sound, light intensity, pressure into analog signals. For example, Figure 1.6.1 is a pressure sensor which makes use of the piezoelectric properties of quartz or ceramics to generate analog output signal. Figure 1.6.1: Illustration of the piezoelectric effect on a pressure sensor An ADC convertsthe analog circuit into digital data. Before talking about ADC, we need to understand the concept of sampling. In signal processing, sampling is a process to convert a continuous-time signal into discrete-time signal using limited number of sample points. The accuracy of the sampled discrete signal is largely dependent on the number of sampling points and bit depth. Figure 1.6.2 is a sampling processing using only 2 bits.

Chapter 1 29 Figure 1.6.2: Sampling with 16 points and 2-bit depth resolution Though we have 16 sampling points, a bit depth of 2 indicates that we can only resolve the analog signal with 4 quantizers, 00, 01, 10 and 11. Therefore the actual sampled points can only lie on the positions where these 4 points intersect with the actual analog signal. Obviously using 2-bit depth has poor resolution and the sampling error produced is unacceptable. In Figure 1.6.3, we used the same 16 sample points but increase the bit depth to 3 and 4 respectively where you will observe a significant improvement on sampling accuracy. Figure 1.6.3: Sampling the same analog signal with 4-bit depth and 3-bit depth The bit size of an ADC applies the same concept of the bit depth in a sampling process. The commonly used ADCs we see may have 8bits, 10bits, 12bits and 14bits, which corresponding to 255, 1024, 4096 and 16384 quantization levels. A higher bit ADC gives higher resolution and smaller sampling error. Besides the bit depth, the sampling rate is another important parameter to evaluate the performance of an ADC. Figure 1.6.4 is a comparison of the sampling results using 8 points and 4 points at a certain time interval. The number of sampling points within a time unit is measured as sampling rate. A slow sampling rate may also cause sampling error, and this effect is more prominent at positions when the analog signal has dramatic changes in amplitude.

A Tutorial for FPGA beginners 30 Figure 1.6.4: Sampled results at different sampling rates Knowing the mechanism of a sampling process, we know two important technical parameters for ADCs are: Bit width and Sampling Rate. For example, if we use a 10-bit ADC to sample a signal of which the amplitude is within 0V to 3.3V, the resolution of this ADC is calculated as: Resolution = 3.3V 210 = 3.3V 1024 ≈ 3.2mV Theoretically, the smallest voltage change that can be possibly detected by this 10-bit ADC is 3.2mV. In real world, there is always some noise on the hardware that may downgrade the performance of an ADC, so you also need to consider the Signal to Noise Ratio (SNR) while designing for applications that require precise measurement results. Sampling Rate refers to the number of sampling points within a unit of time. The basic unit for Sampling Rate is SPS (Samples per second) but most of the time we use Ksps and Msps, which stand for Kilo samples per second and Mega samples per second. Digital to Analog Converter Digital to Analog Converter, DAC, namely is to convert discrete digital bits into a time-continuous analog signal. The operation of a DAC is exactly opposite to an ADC, and the process to convert digital signals to analog signal is called reconstruction. Two important parameters that determining the accuracy of a reconstruction process (also the quality of a DAC) are Bit depth and Conversion Rate. Let us first examine the Bit depth. A higher bits DAC gives a higher signal reconstruction accuracy. In Figure 1.6.5, the reconstructed signal by a 4-bit DAC only has 16 quantization levels, therefore any change in bits, even the least significant bit, will introduce a large jump on the converted analog signal. In comparison, an 8-bit DAC has 256 quantization levels which generate a smoother output.

Chapter 1 31 Figure 1.6.5: Signal reconstruction with 4-bit DAC and 8-bit DAC The resolution for an N bit DAC is 1/2N, which indicates the smallest amplitude change of the converted analog signal when the least significant bit of the data varies. Table 1.26 lists the minimum resolvable voltage for different bit depth. Table 1.26: Resolvable analog voltage for different bit depth of a DAC DAC Bit depth Resolution Resolvable Voltage (3.3V Reference) 8 1/256 12.9mV 10 1/1024 3.2mV 12 1/4096 0.81mV 14 1/16384 0.2mV Another important parameter for a DAC is the Conversion Rate. As shown in Figure 1.6.6, a higher Conversion Rate is capable to generate higher frequency output of the analog signal. The unit of Conversion Rate is also SPS, meaning the number of samples to by converted within 1 second.

A Tutorial for FPGA beginners 32 Figure 1.6.6: Signal reconstruction of 4-bit DAC at different conversion rates Choosing ADCs and DACs ADCs or DACs of high bit depth and high sampling (conversion) rates may exist but would be very expensive, unless there are no concerns with budget or the application does require for extreme performances, you should always consider the tradeoffs between the sampling (conversion) rates and bit depth, which indicate for speed and accuracy. Many applications that require high processing speed will not pursuing for high bit depth of the ADCs and DACs. For example, all digital oscilloscopes will specify their analog bandwidth and sampling rate. For example, the one shown in Figure 1.6.7 may sample 1 Giga (109 ) samples per second and it can capture and display waveforms within 200MHz frequencies. Figure 1.6.7: All digital oscilloscopes should specify the sampling rate and analog bandwidth Since five sampling points are practically the minimum number to identify a complete cycle of sine wave which explains why the maximum bandwidth is usually 1/5 of the sampling rate. The bit-depths of most oscilloscopes are 8, 10 and 12 bits. In 2021 we designed and launched a multifunctional circuit testing device Zoolark has both oscilloscope and function generation, as shown in Figure 1.6.8. The ADC of the oscilloscope has 12-bit depth rated as 1MHz bandwidth and 5Msps sampling rate. The DAC of the function generator has 12-bit depth rated at 15Msps.

Chapter 1 33 Figure 1.6.8: The oscilloscope mode of Zoolark is rated for 5Msps sampling rate On the other hand, most audio applications do not require very high sampling (conversion) rate since human ears can only hear audio signals within 20kHz. According to the famous Nyquist Theorem, the sampling rate must be at least twice the maximum frequency of the signal for a decent sampled result, therefore many modern-day audio recording still use 44.1kHz sample rate, though 96kHz and 192kHz are also available. For example, we have 60 minutes CD which was recorded with 16 bit depth, 44.1kHz sampling rate, then the actual information stored in this CD is as: × . × = , , , = In fact, modern electronics system for audio applications, the high bit depth of ADCs or DACs are implemented with a technique called Sigma-delta modulation, which gives very high bit depth by trading off the sampling or conversion speed. You will see the actual implementation of Sigma-delta modulation in Chapter 5.

A Tutorial for FPGA beginners 34

Chapter 2 35 Chapter 2: Tools for Digital Circuit Experiments 2.1 Circuit Simulation Tools Circuit simulation analyzes the behavior of a circuit based on computations instead of building the physical circuit, therefore it is very useful tool in the beginning phase of circuit design and produce development. Simulation can help designers evaluate a design or idea in a fast and cost-effective manner. Be aware that simulation results may have discrepancies to actual physical results since it is difficult to take account of all physical parameters into computations, thus actual experimental setup is always needed to further validate the design. Simulation Tool CircuitJS There are many high-quality simulation tools on the market. We choose CircuitJS in this book based on three advantages of the software: 1. The software is web-based thus no need for installations and widely accessible 2. The software has many built-in circuit modules, suitable for beginners for a quick start 3. The software is open-source and free to use CircuitJS is simple to use. You may visit the website: https://www.falstad.com/circuit/circuitjs.html. Giving the full credit to the Circuit JS development team, we also embedded the tool (permission based on GNU license) on the website of EIM Technology: www.eimtechnology.com for simpler access: click CircuitJS in the homepage, as shown in Figure 2.1.1. Figure 2.1.1: CircuitJS circuit simulation software

A Tutorial for FPGA beginners 36 Basic Introduction of CircuitJS As shown in Figure 2.1.2, the interface of CircuitJS consists of a function menu area, a circuit drawing area, a waveform display area, and a simulation parameter area. Here we mainly introduce the basic functions such as finding routines, drawing circuits, and analyzing waveforms. Figure 2.1.2: CircuitJS's operation interface home page Draw the circuit – The software has a plenty of prebuilt examples for beginners to start quickly. As shown in Figure 2.1.3, these examples include hundreds of classic circuit models, including analog, digital, and mixed circuits. A new circuit can be created directly by clicking on ‘Blank Circuits’ in the last row of this directory. Figure 2.1.3: Searching for a circuit case that comes with the software Draw the circuit – To draw a circuit on an existing routine or a blank document, right-click on the circuit drawing area, as shown in Figure 2.1.4. Note that when drawing a circuit, if a node is red, it means that there is an error at the junction.

Chapter 2 37 Figure 2.1.4: Drawing a new circuit diagram Table 2.1 also lists the shortcut keys for common symbols and components used in drawing digital circuits, which helps designers to improve their efficiency. In the ‘Options’ section of the function menu, user-defined shortcut keys are also available. Table 2.1: Common shortcuts for CircuitJS Elements Hotkeys Conductors W Resistance R input port I output port O NOT gate 1 AND gate 2 OR gate 3 XOR gate 4 NAND gate @ NOR gate # Analysis of waveforms – The waveform display area is located at the bottom of the interface and can be used to display the voltage at each node and the current in each path of the circuit. In addition to the basic voltage and current information, a user may right-click on the waveform display area to set more parameters such as frequency, power, peak, RMS, etc. for further analysis. Figure 2.1.5: Waveform display

A Tutorial for FPGA beginners 38 An Example Figure 2.1.6 shows a circuit consisting of any combination of Gates. In the simulation software, all the basic modules relating to Gate circuits can be found in the ‘Logic Gates, Inputs and Outputs’ area, see Figure 2.1.6 (right). Y = ((A� + B)C) ⊕ (B��� +��� C�) Figure 2.1.6: Drawing a new digital circuit in CircuitJS When drawing the circuit nodes, ensure all wires are connected end-to-end otherwise the wire connection terminals will turn red and become an error. Figure 2.1.7 shows the complete circuit with all the wire nodes in white, meaning the connection is functional. Figure 2.1.7: Structure of a complete digital circuit module 2.2 Digital Logic ICs FPGA stands for Field Programmable Gate Array, which has a programmable internal hardware to implement digital circuits with all levels of complexity. The actual FPGA implementations are covered in Chapter 3, 4, 5. Before jumping into FPGA work, it is also worthy to know other types of digital logic ICs existed in the market. One famous branch is the family of 74 logic chips which covered almost all commonly used simpleto-medium digital modules and being extremely popular in last century digital electronics. However, the rapid technological development makes the 74 series chips unsuitable for large and complex modern electronics design therefore gradually fainting out from the market. Another often heard type of digital IC is called CPLD, standing for Complex Programmable Logic Device. CPLDs are more versatile than 74 chips and serve good purposes in simple logic control but are far less competitive than FPGAs in terms of the capability to handle complex system design. We

Chapter 2 39 will not specifically mention CPLDs in this book but it is good to know that the programming method for FPGAs and CPLDs are same. 74 Series Integrated Circuits The 74 series of logic chips is one of the most widely used logic chips in history, originally manufactured by Texas Instruments and used in the 1960s and 1970s to build computer motherboards for small architectures. They are still seen in simple gate circuits, computing systems, or memory devices used in some computers. The naming of 74 chips follows certain conventions so that we can easily identify their fabrication technology, as classified in Figure 2.2.2. For example, 74HC08 means it is made of high-speed CMOS technology whereas 08 represents the function code for an AND gate. Figure 2.2.2 74 chip naming conventions Image Source: https://www.nutsvolts.com/magazine/article/understanding_digital_logic_ics_part_2 In addition, many semiconductor manufacturers will also add the manufacturer's prefix for the parts number 74. Two of the more common codes are SN (Texas Instruments) and CD (formerly RCA Semiconductor). Therefore, part number of SN74HC08 indicates it is manufactured by Texas Instruments. Field Programmable Gate Array - FPGA Think of FPGAs as LEGOs. You can use LEGO blocks to build bridges, castles or vessels. In the world of LEGOs all building blocks can be repeatedly disassemble and reassemble to form a completely new object. Same idea applies to an FPGA chip, where you can use the building blocks in the chip to implement simple logic gates or a complex digital computing system.

A Tutorial for FPGA beginners 40 Figure 2.2.3 shows the analogy between a LEGO module and the internal structure of an FPGA. Figure 2.2.3: LEGO blocks and FPGA structure FPGAs are mainly composed of three parts: • A configurable logic block (CLB) • A switch matrix (SM) • An I/O block (IOB) A CLB is essentially a module that can implement any logic function using a huge Look-up Table (LUT). Once the function of the circuit is defined, the switch matrix can be programmed to connect CLBs for achieving desired logic functions. Ultimately, the programmed internal structure interacts with outside world through the IOB. STEPFPGA-MXO2Core Learning Board There are three world's leading FPGA manufactures: Xilinx (acquired by AMD), Altera (acquired by Intel), and Lattice. The STEPFPGA MXO2Core learning board in this book uses Lattice MXO2-4000 FPGA chip, where the suffix 4000 means it contains at least 4000 logic cells. Figure 2.2.4 gives a graphical illustration of the pin overview of the STEPFPGA board.

Chapter 2 41 Figure 2.2.4: STEPFPGA MXO2-4000 TYPE-C Board For educational and experimental purposes, FPGAs are usually come in forms of development boards. The internal structure of FPGA chip is very complicated and getting the chip working involves many hardware design techniques such as power management, hardware configurations, differential wires for high-speed signals and PCB layout skills. A development board usually has all above concerns solved thus we can focus on the digital logic and design part for FPGA development. Hardware Description Language The field programmable feature is the key advantage for FPGAs. Learning how to design or program its internal hardware is the essential skill you may expect from this book. To program FPGAs, we use Hardware Description Language, or HDL. The current mainstream HDL include Verilog and VHDL, which were first released in 1984 and 1987, respectively. Regardless of their differences in design ideas and coding styles, both can be used to perfectly describe and implement digital circuits fully compatible with most FPGAs. Figure 2.2.5 shows the codes of the two languages: VHDL is relatively more hierarchical and rigorous, while Verilog looks more like high level programming language such as C/C++ which is more like our natural language. In this book we use Verilog.

A Tutorial for FPGA beginners 42 Figure 2.2.5: Comparison of the coding style for VHDL and Verilog Though Verilog looks similar to programming languages such as C/C++ in terms of code style and syntax, their fundamental difference is that a programming language sends instructions that are sequentially fed into the system’s processor for executions. In other words, the programming language tells the circuit ‘What to do’ in a sequential order. On the other hand, HDL is a textual description of the circuit structure which essentially tells the FPGA ‘how to build a digital circuit’ based on the codes. 2.3 Digital Module Implementation via FPGA Developing FPGA projects is highly relied on Electronic Design Automation (EDA) tools. Designers can define and describe the hardware through higher-level abstraction methods, such as code or graphical connections. The lower-level circuit implementation, such as the logic synthesis of the code, the layout and wiring inside the chip, and the final machine-readable binary code are all done by EDA tools. FPGA Operation A typical process to develop FPGA projects is outlined in Figure 2.3.1. The most challenging step is to convert design specifications into hardware design, which asks designers to clearly definite the architecture of the module by specifying the inputs, outputs and internal logic relationship. Once the circuit structure is outlined, we describe the hardware structure using Verilog which can be understood by the EDA tool. Chapter 3 will go through this process multiple times.

Chapter 2 43 Figure 2.3.1: General flow of FPGA project development Cloud-based IDE The environment which have all necessary EDA tools integrated for hardware and software development is called Integrated Development Environment tool, known as IDE tool. The IDE tool is important for carrying outany FPGA projects. For FPGA beginners, we recommend using our WebIDE tool designed for STEPFPGA boards that allows most of the functions to be implemented on the browser-based platform without downloading any software or installing drivers. To start, go to: www.eimtechnology.com and select for WebIDE as instructed in Figure 2.3.2. Figure 2.3.2: Acessing the WebIDE tool for STEPFPGA MXO2-Core board

A Tutorial for FPGA beginners 44 Figure 2.3.3 shows the project creation page for which you need to name your project and select the hardware board used. Currently the IDE supports MXO2-Core (the one used in this tutorial) and MXO2-C (previous version that has no UART port). Figure 2.3.3: Creating a project on WebIDE A detailed instruction of the WebIDE tool can be found at the top right ‘instructions’ canvas page, here we simply go over some important steps that converts a Verilog code into actual implementation file for STEPFPGA boards to execute. ❶ Create the project file and complete the Verilog design code for the decoder38 module

Chapter 2 45 ❷ If the code is correct, the compiler will be shown as successful. ❸ Assign the input and output pins defined in the module to the corresponding ports of the smallpinma FPGA. Click Save after finishing the pin assignment. ❹ Map the above configurations into the corresponding FPGA internal alignments.