A Tutorial for FPGA beginners 146 Type of Power Amplifiers Theoretical Efficiency Signal Reproduction Class A up to 25% Excellent Class B up to 78.5% Average Class AB 65% Good Class C 80% Poor Figure 5.6.4: Comparison of different classes of power amplifiers Once we finalized the solutions for amplifier and speaker, the main challenge will be producing audio signals. We know that audio signals are analog signals, recalling from Section 1.6, a DAC is needed to reconstruct the ones and zeros coming from FPGA output into a time-continuous signal. Since STEPFPGA board has a plenty of GPIOs, the most feasible solution is to build a R-2R DAC. Figure 5.6.5 shows the schematic of a 10-bit R-2R DAC where D0 is the LSB and D9 is the MSB. For convenience, the Kit has included a pre-built 10-bit DAC for direct plug and play. Please note that the analog output on this board has low output current capability, so this AO pin must connect to devices with high input impedance, e.g. the inputs of an Amplifier. Figure 5.6.5: Schematic of a 10-bit R-2R DAC A complete hardware setup for a 13 key piano is given in Figure 5.6.6. All pushbuttons are in pull-up structure so the FPGA can determine a button being pressed when reads a logic 0 on the GPIO. The 10 digital inputs on the DAC are connected to 10 GPIOs of the FPGA, and the converted analog output is sent to the audio amplifier to play sounds. The AIN pin of the speaker module has high input impedance thus you may connect it directly to the DAC output.
Chapter 5 147 Figure 5.6.6: Building the entire hardware on a breadboard This hardware layout completes a basic audio system with user interface, in next contents we will work on the digital design inside FPGA to realize the core of the project: digital synthesis of audio signals. Direct Digital Synthesis In digital circuits, is it possible to generate arbitrary shaped waveforms rather than square shaped clock signals? The answer is yes, and to do this we will use an advanced and practical technique called Direct Digital Synthesis (DDS). A generic block diagram for which a DDS module being used to generate is given in Figure 5.6.7, and we will explain its working principle in details. Figure 5.6.7: Block diagram of a DDS circuitry with DAC to generate analog output signal
A Tutorial for FPGA beginners 148 Unlike analog signals, the digital world does not have sense about time and amplitude, so we will use a Phase Accumulator (PA) to setup for time in a digital world. A PA is essentially an N-bit counter with 2N digital states where each state may correspond to a position on the cycle of a digital signal. Figure 5.6.8 explains the process to construct digital signals such as sawtooth, triangular and square waves with a small PA. Figure 5.6.8: Construction process of different digital signals from a PA Obviously the constructed signal can be smoother if the PA contains more digital states. The Look-up Table for these signals are straight forward: • A sawtooth signal is one-by-one mapping to each digital state on the PA • A triangular signal has a turning point at the 2N/2 state • A square signal simply flips around thus only requires two states. Now it is time to investigate the construction process of sinusoidal waves. In 1822, the French mathematician Joseph Fourier discovered that sinusoidal waves can be used as fundamental building blocks to reconstruct any periodic waveforms. If you still recall from a math class, the period of a sin (or cosine) wave is 2π (or 360 degrees). Figure 5.6.9 indicates that you can always construct a sin wave out of a circle, and the smoothness depends on the number of segmentations on the circle. Figure 5.7.9: Drawing a (not very smooth) sine wave out of a circle
Chapter 5 149 To construct sine waves with a PA, we think of a digital circle which has been equally divided into 2N digital states. The table in Figure 5.6.10. gives you a sense for the number of states at different PA bitwidth. In the picture you notice the parameter denoted as M, also known as Frequency Controlled Word (FCW), determines the size of increment of the states. Tuning this M allows the output frequency to be precisely controlled. N Number of Points = 2N 4 16 8 256 12 4,096 16 65,536 20 1,048,576 24 16,777,216 28 268,435,456 32 4,294,967,296 Figure 5.6.10: Segmentations of a PA at different bit depths To be more illustrative, Figure 5.6.11 shows the process to construct a digital sin wave using PA with bit-width of 3, 4, 5 respectively. Figure 5.6.11: Constructing sine waves from a PA with different bit depths and jump sizes For example, at N=3, the PA has 8 states each representing a point on a cycle of the sin wave. With N=4, we got 16 states to outline a cycle of sin wave. As a result, the constructed wave looks finer but frequency is halved. To maintain the same frequency, we can increase the jump size M to 2 to get the same result. Depending on the frequency and smoothness of the curve, you need to seek for a balance between the number of states and jump size. The output frequency fout generated by the phase accumulator can be calculated as:
A Tutorial for FPGA beginners 150 = × Where, fc, the reference clock frequency, which is 12MHz for STEPFGPA board N, the bit width of the PA, and we use 32-bit (which is insignificant to STEPFPGA resources) M, the jump size, or the closest integer multiplier to reach desired output frequency By substituting the constants into the above equation, we get: = × . which indicates the resolution of frequency by a 32-bit PA synchronized to a 12MHz system clock is 0.0028Hz, so you can get fairly accurate output frequency. This equation also suggests that M = 358fout that to be used for calculating the tuning parameter M for different music tones, see Table 5.x. Table 5.5: Corresponding Frequency Control Word M for different base frequencies Simple Tone Frequency (Hz) M C4 261.63 93664 C4# 277.18 99230 D4 293.66 105130 D4# 311.13 111385 E4 329.63 118008 F4 349.23 125024 F4# 369.99 132456 G4 392 140336 G4# 415.3 148677 A4 440 157520 A4# 466.16 166885 B4 493.88 176809 C5 523.25 187324 C5# 554.37 198464 D5 587.33 210264 D5# 622.25 222766 E5 659.25 236012 F5 698.46 250049 F5# 739.99 264916 G5 783.99 280668 Generating a Sine Wave with DDS With enough theoretical background, now it is the time to implement the hardware in real world. Figure 5.6.12 shows the block diagram of a simplified DDS circuitry. The circuit is synchronized to system clock, and the parameter M is fed into the system to control the frequency of the output digital signal. Inside the DDS circuitry, we have a PA and a Look-up Table (LUT) for a sine wave.
Chapter 5 151 Figure 5.6.12: Generate sine wave using DDS technique The output of this module has multi bits carrying the information of the constructed digital signal, which is a sine wave in this case. Since we used a 10-bit R-2R DAC for the audio signal reconstruction, it makes sense that this DDS module has a 10-bit data for the output. In Verilog design, the basic definition of this DDS module is drawn in Figure 5.6.13, which we call it sin_anyfreq indicating the output frequency is adjustable by changing the parameter #M. Figure 5.6.13: Basic definition of module sin_anyfreq The inside of the module is shown in Figure 5.6.14. For the phase accumulator module phase_acc, it is simply a 32-bit counter which increments at each clock cycle. We can always use different parameter M to change incremental size to obtain for different frequencies. Figure 5.6.14: Internal structure of the arbitrary frequency generator module The sine LUT module lookup_tables maps the digital states of the PA to the positions of a sine wave. You definitely do not need all 4 billion states of the 32-bit PA to draw a sine wave. Observing from the previous Figure 5.6.11, with 8 states we can draw an identifiable sine wave, and the shape looks much smoother with 32 states. In practice, using 256 states is enough to draw a decent sine which suggests that the sine LUT only takes 8-bit signals out of the 32-bit PA. The last step is to construct the LUT. We know this LUT should generate a 10-bit data for each digital state, thus an option is to assign corresponding 10-bit data for all 256 states, as indicated in Figure 5.6.12 (a). This option is
A Tutorial for FPGA beginners 152 straightforward but the drawback is obvious: it occupies 2560 logic resources to store the LUT of the sine wave. (a) Method 1 (b) Method 2 Figure 5.6.12: Building a SINE Lookup Table with two methods As a sine wave is highly symmetric, an economical way to construct a complete curve is shown in Figure 5.6.12 (b). The LUT only stores a quarter of the waveform and then use mathematical operations to ‘smartly copy’ the LUT data that constitutes the entire signal. This method uses only 1/4 of the logic resources comparing the first method. In Verilog, the ‘smart copy’ algorithm is implemented with this block statement shown below. always @(sel or sine_table_out) begin case(sel) 2'b00: begin sine_onecycle_amp = 9'h1ff + sine_table_out[8:0]; address = phase[5:0]; end 2'b01: begin sine_onecycle_amp = 9'h1ff + sine_table_out[8:0]; address = ~phase[5:0]; end 2'b10: begin sine_onecycle_amp = 9'h1ff - sine_table_out[8:0]; address = phase[5:0]; end 2'b11: begin sine_onecycle_amp = 9'h1ff - sine_table_out[8:0]; address = ~ phase[5:0]; end endcase end The complete code of sin_anyfreq can be found at the link below. By default it generates a digital sine wave of 261.63Hz. Connecting a 10-bit DAC and feed the converted analog signal to the speaker module you should hear a C4 tone. https://github.com/eimtechnology/STEPFGA/blob/main/Tutorial%20Level1/Chapter5/5.6_SimplePiano/Seperate_Style /sin_anyfreq.v
Chapter 5 153 Top Module Design By now we have implemented the sin_anyfreq module to generate arbitrary frequency sine wave by setting the frequency control word M. In this project we use the 13 keys to represent a full Octave from C4 to C5 (including 5 half tones), which suggests that using a 13-input multiplexer does the job. Figure 5.6.13 shows the top level simpleTonePiano module for the digital design of this project. Figure 5.6.13: Structure of the digital module for simple tone electronic keyboard piano Project Summary The entire project is summarized in Figure 5.6.14.
A Tutorial for FPGA beginners 154 Figure 5.6.14: Summary of the simple electronic piano project
Chapter 5 155 5.7 A More Complex Electronic Piano Project Overview In previous example we got familiar with the process using DDS technique to construct arbitrary frequency sinusoidal waves, and this allows the audio system to generate simple musical tones. But now you may have a question: since each musical tone has a certain frequency, why can we still easily differentiate a harp and trumpet when both instruments playing the same tone? In music terms, timbre is used to describe the sound quality made by different musical instruments. Obviously, the timbres for a harp and a trumpet are different. From engineering and physics perspective, this can be explained by the harmonic series generated due to the physical property of the instrument. In this project, we will again use some signal processing techniques and attempt to simulate string harmonics on STEPFPGA board, you also need the piano kit and the speaker module to implement this project. String Harmonics The sounding mechanism of different musical instrument varies. For example, stringed instruments generate sounds by vibrating strings whereas wind instruments produce sounds by the vibration of air when a player blowing into a mouthpiece set near the end of the resonator. When playing a tone, our ears can easily differentiate the type of musical instruments played since each instrument gives a unique distribution of harmonic series. A harmonic is a wave with a frequency that is a positive integer multiple of the fundamental frequency. When a tone is played on any instrument, the sound you actually hear is a mixture of the base or fundamental frequency of the tone followed by a series of harmonic waves. Figure 5.7.1 shows a harmonic series of a standard string vibrations, where the tone is the base frequency f0 plus a series of harmonics at 2f0, 3f0, 4f0…
A Tutorial for FPGA beginners 156 Figure 5.7.1: Harmonic series of a standard string In theory, the harmonic series of a string can go up to a much higher frequency than the 5th harmonics in the picture, but the amplitude attenuates quadratically as the frequency increases, therefore the auditable portion usually within the 5 harmonics. To get a better feeling of the frequencies and sound, go to this amazing site. https://www.falstad.com/loadedstring/ As a practice in this project, we would like to simulate the sound produced by a standard string vibration by adding a second harmonic wave at 1/4 of the amplitude for each tone played. Delta-sigma Modulation To add a second harmonics to the simple tone, our system should have two output signal ports representing the base frequency fbase and 2fbase at the same time. If we stick with the method in Section 5.6 and use 10-bit DAC for each analog signal, then three signal sources will occupy 20 GPIOs. The piano module included in the kit has 18 keys thus the 36 GPIOs on STEPFPGA board is not enough. Amazingly, there is a technique called Delta-sigma Modulation that encodes/decodes an analog signal into a 1-bit digital signal. Delta-sigma modulation converts an analog voltage signal into a pulse density modulation signal (PDM), for which the amplitude of analog signal is represented by the density of pulses. Figure 5.7.2 shows the PDM representation of a sine wave.
Chapter 5 157 Figure 5.7.2: PDM representation of a sine wave The mathematical principle of Delta-sigma modulation is complicated, but the implementation of Delta-sigma on FPGA is surprisingly simple. In digital design, Delta-sigma modulation can be implemented with an accumulator with an arbitrary threshold placed at the output side to generate bitstream pulses. As shown in Figure 5.7.3, we simply use the MSB of the accumulator as the threshold. Figure 5.7.3: Digital implementation of Delta-sigma modulation using an accumulator The structure of the DeltaSigma module is shown in Figure 5.7.3. As the digital input signal DIN continuously popping data into the accumulator, the accumulating register will eventually overflow, and we take the overflowed bit as the PDM bitstream. Larger magnitude of DIN gives more frequent output of the overflowed bit which corresponds to higher density of the PDM pulses. Figure 5.7.3: Structure of Delta-sigma modulation module
A Tutorial for FPGA beginners 158 Code 5.4 is the Verilog implementation of a Delta-sigma modulator that converts any 10-bit digital signal into PDM output. Code 5.4: Verilog implementation of a 10-bit input Delta-sigma modulation module DeltaSigma ( input clk, input [9:0] data_in, output PDM_out ); // Sigma to delta conversion; reserve 1 extra bit than the input data reg [10:0] accumulator; always @(posedge clk) begin accumulator <= accumulator[9:0] + data_in; end assign PDM_out = accumulator[10]; endmodule To convert the PDM bitstream data into analog signal, a low pass RC filter can be placed to the PDW_out pin as shown in Figure 5.7.4. Figure 5.7.4: Converting a PDM signal into analog waveform by adding a low pass filter The selection of R and C depending on the cut-off frequency, also known as -3dB frequency, denoted as f3dB of the low pass filter. This f3dB frequency is calculated by: = In this audio project, we can suppress all frequencies above 20kHz which are not audible, therefore the above equation can be written as: = × = If choosing C=10nF, then the resistor value is 800 Ω. Using a 1kΩ resistor (more commonly used) is also acceptable in this application. Having the DeltaSigma module built to convert a digital signal into analog output, the next step is to work on the digital input data.
Chapter 5 159 Adjusting Amplitude using Division In previous section we used DDS technique to generate sine waves of arbitrary frequencies, now we want to control the magnitude of the sine wave, meaning a divider is required to attenuate the magnitude of the sine data generated by sin_anyfreq module. However, the operation for division is much more challenging than multiplications in FPGAs. To multiply, you simply use many Full Adders and reserve enough registers to hold the overflow bits. Therefore the line of code below can be synthesized and implemented by almost all FPGAs. Y = A * B; Division, which is an iterative algorithm where the results from the quotient must be shifted to the remainder, is much more painful for FPGAs. If the divisor is 2N, such as 2, 4, 32, 64, 256…the operation is simple since you can just left-shift the dividend binary number by 1 or N bits. However, for other than 2N divisors, many FPGAs cannot handle the work, and they cannot synthesize and implement the line of code below: Y = A / 3; Nevertheless, there is always tricks to walk around with this challenge. As we just mentioned that FPGAs can handle multiplications and division by 2N numbers. Combining these two properties we got an algorithm to estimate the divisional results. For example, if we want to perform Y = A/3, which means: = / ≈ × where 256 is 28 . Thus we can multiply A by 85 first, which is easy, and then left-shift the result by 8 bits. Using higher bits improve the estimation accuracy, for example, = / ≈ × which means you multiply A by 341 (or in binary of 101010101) and then left-shift by 10 bits since 1024 is 210. Using this algorithm, we design the module ampAdjust that may divide the 10-bit digital signal by up to 256 segments, as shown in Figure 5.7.5. Figure 5.7.5: Structure of the amplitude adjust module that varies the magnitude of a digital signal Code 5.5 is the algorithm to divide a 10-bit data by 256. Changing the parameter numerator to any integer from 1 to 256 will the reduce the magnitude of the output dac_Data. An increment of numerator means roughly 13mV increase in the output analog signal under the reference supply
A Tutorial for FPGA beginners 160 voltage at 3.3V, and this is good enough for this project. To be more precise, you can use higher bits divider, e.g. 10-bits which gives a theoretical resolution of 3mV. Code 5.5: Verilog implementation of the amplitude tuning module for a 10-bit digital signal module ampAdjust #(parameter numerator = 1) ( input clk, input [9:0] digitalSignal, output[9:0] dac_Data ); reg [17:0] amp_data; always @(posedge clk) amp_data = digitalSignal * numerator; assign dac_Data = amp_data[17:8]; // left shift by 8 bits to divide by 256 endmodule Harmonics Generation Until this stage, we know the DDS technique to design a 10-bit digital sinusoidal data with arbitrary frequency using the module sin_anyfreq, and we also learned the ampAdjust module that tunes the magnitude of the digital data. Combining the two modules is able to generate a sine wave of arbitrary frequency with arbitrary amplitude. For a standard string vibration, the harmonic series of a tone have integer multiples of its fundamental frequency and amplitudes are 1/4, 1/9, 1/16, 1/25... of the peak amplitude. Figure 5.7.6 shows the block diagram to generate a synthesized digital signal of a tone by adding its second and third harmonics. The output data has 12-bit to hold for the overflow bits. Figure 5.7.6: Generating a synthesized tone by adding the 2nd and 3rd harmonic series Figure 5.7.7 shows the structure of module HarmonicGen which by given a jump size M, will generate a 11-bit data containing the base frequency and the 2nd harmonic signal. The ampAdjust modules tune the 10-bit sine data into 100% and 25% of the magnitudes. By placing an Adder at the end of the three 10-bit data to combine all harmonics signals into a 11-bit digital output (consider the overflow bit).
Chapter 5 161 Figure 5.7.7: Structure of digital module design to generate 2nd harmonic synthesized tone Using 11-bit for DOUT may attenuate the output amplitude since the MSB will be 0 when overflow does not occur. This way you need to increase the gain of the audio amplifier on the analog portion of the hardware. You may still use a 10-bit data for DOUT but keep in mind that some frequencies may get clipped. Top Digital System Design Once we got each individual module worked, then it is the time to integrate all submodules into a single top module. In this project we want to use the 18 key piano module included in the kit (Figure 5.7.8), so the module should have a 18-bit input signal. Figure 5.7.8: 18-key piano kit with 18 pull-up pushbuttons The digital system should handle all mathematical operations and eventually generate a 1-bit PDM output, of which by connecting a low pass filter, will be ready to send the speaker module. Figure 5.7.9 shows this digital system pinao18Key, which does the job as described.
A Tutorial for FPGA beginners 162 Figure 5.7.9: Structure of the module to generate harmonic synthesized tone for 18 keys This time we used a big Adder instead of a Multiplexer to handle multiple keys being pressed simultaneously. Theoretically, summing a 11-bit data by 18 times may generate up to 17-bit data which corresponds to the condition when all keys are pressed at once. In practice, changes to press many keys at together are not often, so we only reserved 12 bits for the sum18. To convert this 12-bit data to analog signal, we also need to change input bits for the DeltaSigma module. See Code 5.6. Code 5.6: Verilog implementation of Delta-sigma modulation for 12-bit input signal module DeltaSigma ( input clk, input [10:0] data_in, output PDM_out ); // Sigma to delta conversion; reserve 1 extra bit than the input data reg [11:0] accumulator; always @(posedge clk) begin accumulator <= accumulator[10:0] + data_in; end assign PDM_out = accumulator[11]; endmodule The completed code for this project can be found at the link below. https://github.com/eimtechnology/STEPFGA/blob/main/Tutorial%20Level1/Chapter5/5.7_HarmonicsPiano/All_In_One _Style/piano18Keys.v
Chapter 5 163 The hardware setup for this project is shown in Figure 5.7.10, where you can simply connect the 18- key piano kit to the STEPFPGA board on a breadboard, and add an RC low pass filter to get the analog waveform of the synthesized audio signal. Connecting this audio signal to a speaker you should key the sound when a key is pressed. Figure 5.7.10: Hardware implementation of the 18-key piano project Project Summary The entire project is summarized in Figure 5.7.11.
A Tutorial for FPGA beginners 164 Figure 5.7.11: Summary of the harmonic synthesized tone electronic piano project
Chapter 5 165 5.8 Sending data through UART Project Overview A well-designed electronics system is like a perfectly arranged and cooperated manufacturing line where the work on each position is handled by the expertise. We know different hardware may be designed to handle only certain jobs, a communication process must exist between different hardware to ensure data can be accurately transmitted and received. If you have prior experiences with Arduino or Raspberry Pi, you should have used the serial monitor to display the digital sensor output values on computer, which is very handy for debugging purpose. The technology behind serial monitor is called Universal Asynchronous Receiver Transmitter, known as UART, is one of the most commonly used device-to-device communication protocol. We will establish an UART communication channel on STEPFPGA board. Parallel vs Serial Communications In data transmission, parallel communication sends multiple bits of data simultaneously whereas serial communication uses one or two transmission lines that send and receive one bit data at a time. Figure 5.8.1 shows the process to send a 1 Byte data using the two methods. Figure 5.8.1: Serial transmission vs. parallel transmission In general, serial communication is slower than parallel communication since it sends one bit data at a time, but serial communication is advantageous for applications that have very limited number of IOs. Also, for communications that require a long-distance cable (imaging using a 20ft USB cable or a 50 ft Ethernet cable), serial communication has a huge cost advantage comparing to parallel method that takes extra many long copper wires. Another advantage for serial communication is to establish a Full-duplex communication. Duplex is a term in telecommunication that describes a point-to-point system composed of two or more connected
A Tutorial for FPGA beginners 166 parties or devices that can communicate with one another in both directions. Figure 5.8.2 shows the mechanism of Simplex (one way only), Half-duplex (either way at a time) and Full-duplex (both ways simultaneously) communications. Figure 5.8.2: Simplex, Half-duplex and Full-duplex communications In parallel communication, all wires are either set to transmit or receive at a time, therefore can only support Simplex or Half-duplex. For serial communication we can always afford to have one or two extra wires allowing data transmit backwards simultaneously, thus the two hardware can communicate each other in real time. Unless for very high-speed communications in GHz level, serial communications play dominant roles in many applications due to the advantages mentioned above. Table 5.6 lists the main features of 3 common types of serial communication methods: UART, I2 C and SPI. Table 5.6: Comparison of UART, I2C and SPI UART I2 C SPI Speed Slow Faster Fastest Timing Asynchronous Synchronous Synchronous # of devices Up to 2 Up to 127 Many Duplexity Full Duplex Half Duplex Full Duplex # of wires 1 or 2 2 4 # of masters and salves Single to Single Multiple masters and slaves 1 master, multiple slaves You may see I2 C and SPI related FPGA projects in our next book of this series for more advanced applications. UART Communication Mechanism UART is one of the most common serial communication protocols that allows two devices communicate each other simultaneously. UART is known as asynchronous communication which means no physical clock wire is needed. On hardware level, two devices A and B want to ‘talk’ in UART protocol, each device needs two GPIOs for TX and RX, and connect as the way shown in Figure 5.8.3 depending on the duplexity you want to achieve.
Chapter 5 167 Figure 5.8.3: Setting up physical UART connections for two hardware Next step is to work on the protocols of communication. In UART communication, data is sending in Bytes, meaning each time there are 8-bits of data sequentially travel from the TX pin of device A to RX pin of device B. To ensure the data is received correctly by the receiver side, a starting bit of logic 0 and stop bit of logic 1 have been added at the two ends of each data Byte. Sometimes you can also add a parity check after the MSB which is optional. Figure 5.8.4 shows the protocol for 1 Byte data being sent. Figure 5.8.4: The data format of sending 1 Byte from the TX wire The speed of data transmission is measured in unit of Bauds, sometimes called Baud Rates, defined as the rate at which the number of symbol changes within 1 second when data passes through the transmission line. In UART communication, we may think of Baud as the number of bits transmitted within 1s. Table 5.7 lists some standard Bauds and their corresponding bit duration. The 3rd column for BPS_PARA is the parameter reference for Verilog design, which we will mention shortly. Table 5.7: The time duration to send each bit under different Bauds Standard Bauds Bit duration (ms) BPS_PARA 1200 8.33 10000 2400 4.16 5000 4800 2.08 2500 9600 1.04 1250 19200 0.52 625 38400 0.26 313 57600 0.176 208 115200 0.0868 104
A Tutorial for FPGA beginners 168 It is a common mistake to confuse Baud with Bit Rate which has unit of bit per seconds (bps). In UART, each symbol is represented by 1-bit data, therefore Baud in UART is same with Bit Rate. However, some other coding mechanisms in telecommunication use multiple bits to represent one symbol. For example, in Manchester coding each symbol carries 2-bit information, therefore a 10 Baud means 20 bps in Manchester coding. As an example, we will show a complete Simplex process for which a data byte 10111100 is sent from hardware A to hardware B. The entire process is by three steps as indicated in Figure 5.8.5. Step1: Transmitter loads 8-bit data on the tx_data input, which is an 8-bit parallel input Step2: Add starting and end bits (parity bit is optional) and sent bitstream through tx line; this data is sent from hardware A to hardware B in a sequential way Step3: Receiver converts the bitstream to 8-bit data on rx_data by removing the start bit and end bit from the tx line Figure 5.8.5: A complete Simplex process for data transmitting from hardware A to B Implement an UART Transmitter If you only need to send out data, an UART transmitter is enough. A complete UART module composes two parts. First, we need a BaudGen module that generates for different standard Bauds. The basic definition of the BaudGen module is drawn in Figure 5.8.6. To setup for different Baud Rates, change the parameter BPS_PARA according to Table 5.7 for other standard Bauds. Figure 5.8.6: Module definition of BaudGen
Chapter 5 169 module Baud # (parameter BPS_PARA = 1250)( input clk, rst_n, input bps_en, // connects to 'bps_en' on UART_Tx module output reg bps_clk // connects to 'bps_clk' on UART_Tx module ); We also need a module which receives data in Bytes and then transmit each bit of the data in a sequential way. Figure 5.8.7 shows the structure of UART_Tx module which is designed to continuously intakes 8-bit dataByte and send each bit sequentially though the output tx wire. Figure 5.8.7: Module definition of UART_Tx module Uart_Tx ( input clk, rst_n, input bps_clk, // Connects to bps_en on BaudGen output reg bps_en, // Connects to bps_clk on BaudGen input tx_en, // Enable transmission when tx_en is high input [7:0] tx_data, // The 8-bit data to be sent to receiver output reg tx // Send out the data pack through this wire ); Figure 5.8.8 shows a complete design structure for UART_Send module. This module takes 8-bits input data dataByte and send this data sequentially at certain Baud Rates (9600 Bauds by default) through the tx line. In next parts, we will connect this module to a rotary encoder and observe the output data of the encoder through a COM port. Figure 5.8.8: Structure of digital module to transmit data through UART
A Tutorial for FPGA beginners 170 You can find the complete Verilog code for UART_Send module at this link: https://github.com/eimtechnology/STEPFGA/blob/main/Tutorial%20Level1/Chapter5/5.8_UARTCommunication/Seper ate_Style/UART_Send.v Rotary Encoder Before connecting a rotary encoder, let us first understand how it works. A rotary encoder is a type of position sensor which is used for measuring the rotational speed. It generates an electrical signal, either analog or digital, according to the rotational movement. Depending on the encoding mechanism, rotary encoders are categorized into absolute type and incremental type. Figure 5.8.9 is a 3-bit absolute encoder for which a full revolution of shaft is divided into eight segments. Any rotation angle will be mapped to a certain binary number (using Gray code such that each adjacent segment only has 1 bit change). Figure 5.8.9: Demonstration of a 3-bit absolute rotary encoder Incremental type encoders do not have a fixed pattern matching to each shaft position, instead, it only generates output signal for each increment step. One most seen application of an incremental rotary encoder is the computer mouse wheel. The layout of an incremental encoder is illustrated in Figure 5.8.10. The placement of A and B always ensures a half phase shift between the two output signals, and by looking the digital output patterns generated during shaft movement we can determine the orientation of the rotation.
Chapter 5 171 Figure 5.8.10: Demonstration of an incremental type rotary encoder The rotary encoder module included in the kit (as shown in Figure 5.8.11) is of incremental type whereas pin A and pin B are connected to the encoder outputs. Pin S1, configured as pull-up network, is also connected to the encoder so when you press the encoder a low voltage is generated. VCC – Use 3.3V for STEPFPGA A, B – CW and CCW rotations of encoder S1 – Press of the encoder K1, K2 – two pushbuttons (pull up) Figure 5.8.11: Incremental type rotary encoder included in the kit In Verilog, we designed a digital module RotEncoder that reads and interprets the actions of the rotary encoder. As you can see in Figure 5.8.12, the 2 inputs key_A, key_B connect to the A and B of the encoder module. When the shaft rotates, depending on the orientation of rotation, either CC_pulse or CCW_pulse output will generate a single pulse for each increment. Figure 5.8.12: Module definition of incremental rotary encoder control module Due to the length of code, the full Verilog code for this rotary encoder module can be found in this link below. This code can be used as a general module to interface most incremental type encoders such as EC11. https://github.com/eimtechnology/STEPFGA/blob/main/Tutorial%20Level1/Chapter5/5.8_UARTCommunication/Seper ate_Style/RotEncoder.v
A Tutorial for FPGA beginners 172 To interface with an incremental rotary encoder, connect the pin A, B to the key_A and key_B inputs of the module. The output CC_pulse or CCW_pulse will generate fast pulses corresponding to each increment of shaft rotation. The pulse is synchronized to system clock and the pulse width is in nanoseconds range. Figure 5.8.13: Interface the rotary encoder module to the hardware Send Encoder data to Computer In telecommunication, RS-232 is a standard for serial communication transmission of data which has been commonly used in computer serial ports. On a desktop computer or an old fashion laptop, you may find a large connector port looks like Figure 5.8.14. This RS-232 standard Serial communication port has 9 pins, where pin 2 (RX) and pin 3 (TX) can be directly connected to the UART port of another hardware for serial communication. Pin # Signal Purpose 1 DCD Data carrier detect 2 RX Receive data 3 TX Transmit data 4 DTR Data terminal ready 5 GND Signal ground 6 DSR Data set ready 7 RTS Request to send 8 CTS Clear to send 9 RI Ring indicator Figure 5.8.14: RS232 Serial COM port connector pin definitions Most of our computers used today no longer offer this RS232 connector, therefore if you want to build up a serial communication between a hardware and a computer, that hardware must have embedded a USB to serial converter. For example, your Device Manager will show up a USB Serial Device COM port when plugin STEPFPGA MXO2-Core board (which has internal USB to serial convertor).
Chapter 5 173 Once we implemented a UART serial communication module on MXO2Core board, the tx and rx pins of the module can be assigned to RX (A3) and TX (A2) pins of the FPGA in the FPGA mapping step, see Figure 5.8.15. The older version for MXO2-C board does not have this function available so you need external USB to serial converter chip to setup UART communication to a computer. Figure 5.8.15: The internal UART communication port on STEPFPGA MXO2Core board In previous steps we have designed the UART_Send module which intakes data in Bytes and send out each bit sequentially through the output tx wire; we also implemented the RotEncoder module that connects to the pin A, pin B of an incremental rotary encoder and generate a single pulse for each increment. Combining the two modules together we got the RotEncoderTx module for this project. Figure 5.8.16: Basic definition of RotEncoderTx module
A Tutorial for FPGA beginners 174 We know the UART_Send module receive data in Bytes, therefore an additional ByteGen module is needed to convert single pulses into 8-bits of data. Specifically, for each pulse received from pulse_L, the 8-bit output dataByte decrement by 1 and for pulse_R will increment by 1. An OR gate is connected to the two pulse signals to ensure data transmission is enabled as long as the shaft rotates. The complete digital design structure is shown in Figure 5.8.17. Figure 5.8.17: Structure of digital module for RotEncoderTx To observe any changes, we need a serial debugger tool that displays the received data on computer. Here we use a free software called Serialplot which can be downloaded from this link below: https://hackaday.io/project/5334-serialplot-realtime-plotting-software Before running the software, we first ensure the RotEncoderTx module has been implemented on the STEPFPGA MXO2Core board and the inputs & outputs were assigned to the correct pins. Figure 5.8.18 shows the hardware setup of the project, and when you plugged the board to computer, you should observe a COM port in Device Manager. Figure 5.8.18: Hardware setup of the project
Chapter 5 175 Now we can open the Serialplot. Select and open the COM port of the FPGA, and change the Port setting to: Baud Rate 9600, No Parity, 8-bits, 1 Stop Bit as shown in Figure 5.8.19. Figure 5.8.18: Port setting for displaying the data received from the rotary encoder Once the Port is open is set correctly, the waveform plot will display while rotating the shaft, and you can always change plot setting such as butter size and plot width based on your plotting requirements. The plotted data range should be an unsigned 8-bit data (from 0 to 255 on Y-axis). Figure 5.8.19: Plot settings on Serialplot
A Tutorial for FPGA beginners 176 Project Summary The entire project is summarized in Figure 5.8.20. Figure 5.8.20: Summary of the harmonic synthesized tone electronic piano project
Project Based Learning STEP FPGA