Tutorial for FPGA Beginners

A Tutorial for FPGA beginners 46 ❺ When the mapping is successful, the IDE will generate the final hardware configuration file implementation.jed. Drag and drop the file directly into the Little Foot FPGA to complete all hardware configurations.

Chapter 2 47 Diamond IDE FPGA manufacturers will also launch their own IDE tools for their chips. The STEPFPGA uses Lattice MXO2-4000 chip and can be developed with Diamond IDE. Here we only show some key steps to use Diamond, more detailed procedures can be found in Lattice’s official technical documents. Find Diamond software in Lattice Semiconductor website download page, see Figure 2.3.4, then download and install. Figure 2.3.4: Login to the Lattice website to find the download file After opening Diamond IDE, you will start off by creating a new project file, see Figure 2.3.5. Your project folder holds all work pieces including Verilog design files, simulation results and implementation files, so set the folder directory to a place that is easy to locate.

A Tutorial for FPGA beginners 48 Figure 2.3.5: Creating an FPGA project in Diamond IDE Then we need to select “MXO2-4000HC” for the chip, see Figure 2.3.6. Figure 2.3.6: Selecting the corresponding board model The development interface of Diamond looks like Figure 2.3.7, where you have different working areas for HDL design, EDA tools, output message area and file hierarchy. Figure 2.3.7: Introduction to the development interface Once the Verilog design is completed, use the development EDA tools to continue the synthesize, pin mapping, place and route trace and eventually generate the implementation file. To assign inputs and outputs to FPGA IO pins, click ‘Spreadsheet View’ and assign pins accordingly as shown in Figure 2.3.8.

Chapter 2 49 Figure 2.3.8: FPGA chip pin assignment The implementation file generated by Diamond IDE has a file extension ‘.jed’, which can be programmed into the FPGA chip. When you plug this STEPFPGA board to your computer, it is automatically configured as a USB flash drive. To program the FPGA, you can simply drag the .jed file into this USB drive to complete the final programming. 2.4 Building Digital Modules with 74 series chips In Chapter 5 we will carry out some comprehensive projects with actual hardware building, so this section is a good time to get familiar with some simple circuiting skills on breadboards, and we use some 74 series logic chips as examples. Reading the Datasheet For any Integrated Circuit, a datasheet gives detailed information of its main functions, electrical parameters, pin definitions, IC footprints, physical dimensions and typical applications…which literally include all information needed to fully understand the chip. The ability to read and understand key information in a datasheet is also an important skill for electronics engineers. Taking 74HC00 as an example. First go to Texas Instruments website and search for 74HC00 in the search box, and should get something like Figure 2.4.1. You may also use Google search but make sure you choose the matching result provided by the same manufacturer.

A Tutorial for FPGA beginners 50 Figure 2.4.1: Searching the 74HC00 data sheet on the TI website The summary information is usually given in the home page, see Figure 2.4.2. You should refer to the latest revision of the manufacturer's datasheet which in this example can be found at the right top conner of the page. Figure 2.4.2: Overview of the 74HC00 chip technical manual Checking the summary page usually gives you a quick sense that if this chip satisfies your design requirements. More detailed information such as pin definitions and electrical parameters can be found in later sections of the datasheet.

Chapter 2 51 Commonly used 74 series chips For nearly half century development, the family of 74 series logic chips became huge and deviated thousands of types to serve for various logic functions. If you visit Wikipedia and search for 74 series, do not be shocked by the fact that almost all digital modules and circuits learned in textbooks can be fully implemented by 74 series chips. We have selected some commonly used ones as listed in Table 2.3 covering from Gates, combinational logic modules and sequential modules, and will use FPGA to achieve their designated functions in Chapter 4. Table 2.3: Some selected 74 logic ICs to be implemented by FPGA Part Number Main Function Exercises 74HC08 2-input AND gate Section 4.1 74HC283 4-bit Full Adder Section 4.2 74HC138 3-8 Decoder Section 4.3 74HC74 Positive Edge D flip-flop Section 4.4 74HC165 8-bit Shift Register Section 4.5 74HC393 4-bit Binary Counter Section 4.6 Circuit construction Before advancing to the FPGA implementations of the 74 logic functions, it is worthy to know the procedures for which a physical 74 logic chip is built on a breadboard. We use the NAND Gate 74LS00 as an example to demonstrate the experimental procedures. According to datasheet, the maximum supply voltage for 74LS00 is 7V, so powering it at 5V is an acceptable range. Figure 2.4.3 is the pin diagram of 74LS00, where pin 14 is the power pin for VCC which should be connected to 5V; pin 7 is connected to GND. The rest pins represent the input and outputs for 4 NAND Gates, which explains that the chip is called Quadruple 2-input NAND Gates. Figure 2.4.3: Schematic diagram of 74LS00 chip pins Figure 2.4.4 shows the breadboard layout. Here we use our breadboard power supply MEGO and set it to 5V. We also need some resistors, switches and LEDs for tangible engagements and observation of the experimental results.

A Tutorial for FPGA beginners 52 Figure 2.4.4: Connecting chips to the breadboard The complete breadboard testing circuit for 74HC00 is shown in Figure 2.4.5, where the left schematic consists of the chip and peripheral design. Each input side has a switch, a current limiting resistor and an LED. The output also has a resistor and LED to show for High or Low output. Eventually everything was connected on the breadboard as shown on the right side. Figure 2.4.5: Reference schematic of breadboard connection Once the circuit is built, we can turn on the power and observe the LEDs by toggling the switches and observe the corresponding lighting patterns of the LEDs to verify the logical behavior of your test circuit. The result should match to the Truth Table of an AND Gate.

Chapter 3 53 Chapter 3: FPGA Implementation of Digital Modules 3.1 Implement a 3-input XOR circuit XOR gates are often used in operations such as addition, subtraction, multiplication and division and they play important roles in computer logic & arithmetic operations. A 3-input XOR gate is essentially built on two 2-input XOR gates as shown in Figure 3.1.1, and it only generates a logic 1 when the input side contains odd number of logic 1s. Figure 3.1.1: Logic diagram of 3-input XOR gate circuit The Truth Table of the 3-input XOR logic gate circuit is shown in Table 3.1: Table 3.1: Truth Table for 3-input XOR gate Input Output A B C Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Verilog Design Regardless of designing with VHDL or Verilog, there are 3 philosophies to describe the structure of a digital circuit: Gate-level description (sometimes also called structural description), Data flow description, and Behavior-level description. Being our first FPGA example, we use the most intuitive method: Gate-level description to implement this XOR3 gate. The first step is to complete the basic definition of the Module, that is, the name, inputs and outputs of the module. Before going into the code, we can essentially draw this Module on paper, as seen in Figure 3.1.2.

A Tutorial for FPGA beginners 54 Signal Name Bit size Type A 1 bit Input B 1 bit Input C 1 bit Input Y 1 bit Output Figure 3.1.2: XOR3 module We name the module as XOR3_1 to represents a 3-input, 1-output XOR gate. But you can name it whichever way preferred. In Verilog, the way to describe what we just drew is given as follows: module XOR3_1 ( input wire A, input wire B, input wire C, output wire Y ) ; You noticed that all user defined variables such as XOR3_1, A, B… are color-coded. The yellow texts such as module, input wire, output wire are instruction words in Verilog which carry certain functions. We will go over more details as moving forward. The next step is to describe the logic function of the module. In most Verilog compilers, those commonly used Gates such as NOT, AND, NAND, OR, XOR, etc., have been packaged as a prebuilt model (known as primitives) so you can use them directly. For example, you can describe the logic behavior of a 3-input XOR Gate as: xor (Y, A, B, C) ; Therefore, the complete code to implement a 3-input XOR Gate using Gate-level description method is shown in Code 3.1. Code 3.1: Construction of a 3-input XOR Gate circuit using the Gate-level description method module XOR3_1 ( input wire A, input wire B, input wire C, output wire Y ) ; xor (Y, A, B, C) ; endmodule FPGA Experiment In this experiment, we use WebIDE to implement a 3-input XOR gate with the following procedures. ❶ Go to www.eimtechnology.com, click WebIDE in the tools section. Create a project called XOR3_1, add a source code file with the same name (recommended). To create the Verilog design file, type in the codes in Code 3.1.

Chapter 3 55 ❷ Click Logic synthesis. If the code is correct, it shows that the synthesis was successful. If there are errors in the code, the debug.log file will mark the corresponding lines of the errors. ❸ Pin Assignment. Since your code defined three inputs and one output for XOR3_1, we need to map these pins onto the FPGA board. For observation purposes, we can assign the three inputs to the three toggle switches, and the one output to one of the LEDs on board. ❹ Once the pins are assigned, click FPGA mapping to convert the entire project to the executable implementation file that ‘instructs’ the FPGA to configure the internal wiring to achieve the logic functions. This step is done automatically by the EDA tool.

A Tutorial for FPGA beginners 56 ❺The implementation file (with extension of JED) is ready to be programed or burned into the FPGA board. To do so, connect FPGA to the USB port and download the file into the USB flash drive of your FPGA to complete the final burning process. This step usually takes few seconds depending on the size of your project. Once the program is burned into the board, you may toggle the on-board switches as shown in Figure 3.1.3 and observe the LED effects.

Chapter 3 57 Figure 3.1.3: Debugging a 3-input XOR gate on STEPFPGA The results might be somehow counterintuitive since the LED turns off at logic 1 and turns on when it gets a logic 0. This is because all LEDs of the STEPFPGA used inverting logic. This way may increase output current capability for the internal push-pull structure therefore is commonly used in industrial design. Exercise Gate-level description is suitable to build simple modules constructed by fundamental logic gates. For an exercise, a custom gate module called xgate is described below, please complete the following tasks. module xgate ( input wire A, input wire B, input wire C, output wire Y ); wire s1, s2; and (s1, A, B); not (s2, C); or (Y, s1, s2); endmodule Task 1: Draw the detailed internal structure of this module: Task 2: Complete the Truth Table for this module A B C Y

A Tutorial for FPGA beginners 58 Task 3: Implement this module on STEPFPGA board and observe the logic behaviors for different input signals. 3.2 Implement a 1-bit Full Adder In Section 1.3, we learned the basic working principles of a binary Full Adder. To repeat, a 1-bit Full Adder contains 3 inputs and 2 outputs and it has the Truth Table listed in Table 3.2. Table 3.2: Truth Table and Boolean expressions for a 1-bit Full Adder Input Output CIN A B Sum CO 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 = ⨁⨁ = (⨁) + Verilog Design With Gate-level description, we need to draw the internal structure of a Full Adder explicitly showing all primitive Gates. In Figure 3.2.1, a Full Adder consists of five Gates and three intermediate signals s1, s2, and s3. These intermediate signals exist only inside of the module but cannot be accessed or seen from basic module definition. Figure 3.2.1: Building a 1-bit Full Adder using a Gate-level description As a recap exercise you can try to implement this structure with Gate-level description learned in Section 3.1. Now we introduce the Data-flow description method, a more efficient way to describe modules that has many mathematical operations or data manipulations. Like programming languages, Verilog contains many operators to support different mathematical operations, we listed some common binary operators in Table 3.3.

Chapter 3 59 Table 3.3: Common binary logic operation symbols in Verilog Symbol Function & AND | OR ^ XOR ~ NOT ^~ XNOR Code 3.2 is a 1-bit Full Adder circuit built with Data flow description method. As we can see, using these operator instead of explicitly drawing all the internal Gates will realize the mathematical operations in a faster and easier way in terms of coding style. Code 3.2: Constructing a 1-bit Full Adder module full_adder ( input wire a, input wire b, input wire cin, output wire sum, output wire co ); assign sum = a^b^cin; assign co = ((a^b)&cin)|(a&b); endmodule However, we should be aware that Data-flow description is not necessarily more economical or efficient than Gate-level description, since the actual synthesis is handled by the EDA tool which sometimes may use more resources to achieve simple functions. But you do not need to worry about the economics of logic units until reach to a stage that gives a more serious concern about resource efficiency and timing. FPGA Experiment Figure 3.2.2 shows the suggested pin assignments. In the experiment, we can verify the design by toggling the switches and observe the LED status. Figure 3.2.2: Pin assignments for implementing a 1-bit Full Adder

A Tutorial for FPGA beginners 60 Exercise Assuming we have obtained the Boolean expressions of the module: = = �� + �� + = �� + � Here we can name the module as test, which contains 4 inputs and 3 outputs. The following figure gives the definition of the module's ports: Task 1: Complete the following Verilog code for the Boolean expressions: module test ( input A, B, C, D, output Y3, Y2, Y1 ); assign Y3 = ; assign Y2 = ; assign Y1 = ; endmodule Task 2: Complete the Truth Table for the test module section A B C D Y3 Y2 Y1 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 0

Chapter 3 61 Task 3: Implement your program on STEPFPGA board and check against your Truth Table to see if your program is correct. 3.3 Implement a 2-4 Decoder A 2-4 Decoder contains 2 inputs and 4 outputs. A 2-4 Decoder is the simplest structure in Decoder family. The Truth Table and Boolean expressions are shown in Table 3.4. Table 3.4: Truth Table for a 2-4 Decoders Input Output A1 A0 Y3 Y2 Y1 Y0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 0 = �� = � = � = Verilog Design Either Gate-level or the Data-flow description is acceptable to describe this 2-4 Decoder. Now it’s time to introduce a mostly used method: Behavior-level description. To approach this method, let us first attempt to explain the Truth Table 3.4 in natural language： • When A1 = 0, A0 = 0, then Y0 = 1, and the rest of the output signals are 0. • When A1 = 0, A0 = 1, then Y1 = 1, and the rest of the output signals are 0. • When A1 = 1, A0 = 1, then Y2 = 1, and the rest of the output signals are 0. • When A1 = 1, A0 = 1, then Y3 = 0, and the rest of the output signals are 0. As usual, we start from the basic definition of the module. You noticed that the outputs are specified in reg instead of wire in Behavioral-level description. module decoder24 ( input wire A1, A0, output reg Y3, Y2, Y1, Y0 ); Moreover, if the input or output port has multiple signals arranged in binary sequence, we can also rewrite in this bit-wise form as shown below: module decoder24 ( input [1: 0] A, output reg [3: 0] Y );

A Tutorial for FPGA beginners 62 Whereas input [1: 0] A means there are two input signals and A[1] is the most significant bit, A[0] is the least significant bit. To continue for the logic behavior of the module, we use a block statement called always @ (…) : always @ ( ) begin end This block statement means: if the condition inside @(…) is activated, the content in the block statement will be enabled. In Behavioral-level description method, we use block statements to describe the logic behavior of the module. We will also see conditional statements like if…else in later contents. Also, all data assignment occurred in block statements must have data type of reg. Code 3.3 is the 2-4 Decoder implemented with Behavior-level description. Code 3.3: Construction of a complete 2-4 Decoder module decoder24 ( input [1: 0] A, output reg [3: 0] Y ); always @ (A) begin case (A) 2'b00: Y = 4'b0001; 2'b01: Y = 4'b0010; 2'b10: Y = 4'b0100; 2'b11: Y = 4'b1000; endcase end endmodule In addition to the always @ ( ) block statement, the case( ) conditional block statement is also used. In this code, when the signal A equals to 01, the corresponding output results for Y is 0010. In Verilog, data type and data size are specified by adding prefix before a data. In the code, we noticed that the input and output data are specified as 2'b00 and 4'b1000, this means the input A is a binary data and it occupies 2 bits; output Y is a binary data of 4 bits. More concisely, Figure 3.3.1 lists different results by implementing the example of A = 10 but with different prefixes added.

Chapter 3 63 Figure 3.3.1: Specify data type and data size in Verilog FPGA Experiment To implement this 2-4 Decoder on STEPFPGA board, we create a project on WebIDE and put the contents of Code 3.3 to design the hardware. The pin mapping on the board is shown in Figure 3.3.3. Figure 3.3.3: Pin assignment reference for 2-4 Decoder experiment Experiment with the FPGA configuration in Figure 3.3.4 below. While playing the toggle switches, you may find it is more intuitive to assign A[0] to SW2 and A[1] to SW1 since the least significant bit usually sits at the rightmost place by conventional writing. Figure 3.3.4: Implement a 2-4 Decoder on STEPFPGA board

A Tutorial for FPGA beginners 64 Exercise We learned Binary Encoders in Section 1.3, however, Priority Encoders are more often used in practice. A 2-4 Priority Encoder has the following Truth Table: Input Ouput I3 I2 I1 I0 Y1 Y0 0 0 0 1 0 0 0 0 1 X 0 1 0 1 X X 1 0 1 X X X 1 1 From the Truth Table we see that a Priority Encoder only detects the most significant bit and overlooks the rest lower bits. Priority Encoder reduces the requirements on the input side and has more tolerance to the errors occurred due to input noise. We can model a Priority Encoder using the block diagram below. Notice that the inputs and outputs are represented with data bus. Task 1: Complete the missing part of the code of a 2-4 Encoder module pr_Encoder24 ( input [3: 0] I, output ______ [3: 0] Y ); always@ ( ____ ) begin casez ( ____ ) 4'b0001: Y = 2'b 00; 4'b001z: Y = 2'b __; 4'b01zz: Y = 2'b __; 4'b1zzz: Y = 2'b __; default: Y = 2'b __; endcase end endmodule Task 2: Synthesize the above code and implement the program on STEPFPGA board according to the pin assignment as suggested.

Chapter 3 65 Task 3: Design your own Verilog code for an 8-3 Binary Encoder with the below Truth Table. I[7] I[6] I[5] I[4] I[3] I[2] I[1] I[0] Y[2] Y[1] Y[0] 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 A 8-3 Binary Encoder requires 8 inputs so on STEPFPGA board you can use the additional 4 pushbuttons to verify the result. 3.4 Implement a 3-8 Decoder 3-8 Decoders are more frequently used in practical applications since the 8 output bits form a Byte. In this experiment we will build a 3-8 Decoder by instantiating two 2-4 Decoders. Though you may still use Behavioral-level description and lists the 8 conditions in a case statement, instantiation of modules is a commonly used technique to build large and complex digital systems. First, we may recall the Truth Table of the 3-8 Decoder (See Table 3.5). Table 3.5: Truth Table for 3-8 Decoders Input Output A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0

A Tutorial for FPGA beginners 66 By splitting the Truth Table above, we realized that a 3-8 Decoder can be implemented by two decoder24 modules. In Table 3.6, an additional enable signal (E) is added. When E = 0, the first 2-4 Encoder which controls the 4 lower bits is functional; when E = 1, the second 2-4 Encoder controlling the 4 higher bits is functional. Table 3.6: Building a 3-8 Decoder with two 2-4 Decoder with Enable Function E A1 A0 Y3 Y2 Y1 Y0 y3 y2 y1 y0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 Based on the property existed in the above Truth Table, we can construct a 3-8 Decoder using two 2- 4 Decoders each controlled by an enable input signal, as shown in Figure 3.4.1. This hardware connection structure will be also referred in later code design. Figure 3.4.1: Building a 3-8 Decoder with Two 2-4 Decoders with Enables Verilog Design As before, we start from defining the basic definition of the module, therefore name the module decoder38 and define 3 input signals and 8 output signals. Note that the output signal type must be defined as wire if it is connected to a instantiated module. module decoder38 ( input wire [2: 0] X, output wire [7: 0] D ) ;

Chapter 3 67 The next step is to instantiate two 2-4 Decoders. On top of the Decoder 24 module build in code 3.3, we add an enable input signal E. The Verilog code of modified 2-4 Decoder is given in code 3.4. Code 3.4: Behavioral description of a 2-4 Decoder with enable input signal module decoder24_en ( input wire [1:0] A, input wire EN, output reg [3:0] Y ); always @ (EN, A) begin if (EN == 1'b1) case (A) 2'b00: Y = 4'b0001; 2'b01: Y = 4'b0010; 2'b10: Y = 4'b0100; 2'b11: Y = 4'b1000; endcase else Y = 4'b0000; end endmodule Code 3.5 shows the syntax for submodules instantiation. Each submodule must be given an identical name (e.g. upper and lower) and the complete code for the instantiated submodule must either written in the same Verilog file or stay in the same project directory. You will see in the Experiment part. Code 3.5: Instantiate two 2-4 Decoders to construct a 3-8 Decoder module decoder38 ( input wire [2: 0] X, output wire [7: 0] D ) ; decoder24_en upper ( .A (X[1: 0]) , .EN (X[2]) , .Y (D[7: 4]) ) ; decoder24_en lower ( .A (X[1: 0]) , .EN (!X[2]) , .Y (D[3: 0]) ) ; endmodule If you prefer less lines, Code 3.5 can be also written in the way below by removing the searching operator such as .A( ) and .EN(). With a neater style and less codes, however, you need to ensure the signals match the exact same sequence defined in your submodule. module decoder38 ( input wire [2: 0] X,

A Tutorial for FPGA beginners 68 output wire [7: 0] D ) ; decoder24_en upper (X[1:0], X[2],D[7: 4]); decoder24_en lower (X[1:0],!X[2],D[3: 0]); endmodule FPGA Experiment The first method is to write all submodules in the same Verilog design file as shown in Fig 3.4.2. Figure 3.4.2: Include all submodule code in one design file The second method is to create two files in the same project folder. Decoder 38 as the direct port definition of the module needs to be set as the top-level file; the other file is a sub-file of Decoder24_en, which is also placed in the same project directory. The top-level file can be synthesized during logic synthesis. Figure 4.2.4: Put Submodule in the Same Project Directory

Chapter 3 69 Obviously method 1 is convenient for relatively simple modules. For modules containing many subentities, building a hierarchical structure with the second method can help us quickly understand the functional composition of the entire system. Exercise If a 3-8 Decoder can be composed of two 2-4 Decoders, it means that a 4-16 Decoder can be composed of two 3-8 Decoders. Here we give the modular structure of the 4-16 Decoder: We first write the codes of the basic definitions of decoder416, then complete the following tasks: module decoder416 ( input wire [3: 0] X, output wire [15: 0] D ); Task 1: Ensure the 3-8 Decoder has a enable input signal, thus we need to have a complete code for decoder38_en. Fill in the blanks of the code below.

A Tutorial for FPGA beginners 70 module decoder38_en ( input [ : ] A, input EN, output reg [ : ] Y ); always @ (EN, A) begin if (EN == ) case (A) 3'b000: Y = 8'b0000_0001; 3'b001: Y = 8'b0000_0010; 3'b : Y = 8' ; 3'b : Y = 8' ; 3'b : Y = 8' ; 3'b : Y = 8' ; 3'b : Y = 8' ; 3'b : Y = 8' ; endcase else Y = 8'b0000_0000; end endmodule Task 2: Build the decoder416 by instantiate two decoder38_en. Make sure you go through the entire process and generate the final implementation file to program your FPGA board. module decoder416 ( input wire [ : ] X, output wire [ : ] D ); decoder38_en u1 ( .A (X[ : ]), .EN (X[ ]), .Y (D[ : ]) ); decoder38_en u2 ( .A (X[ : ]) , .EN (!X[ ]), .Y (D[ : ]) ); endmodule 3.5 Drive a 7-segment display A 7-segment display consists of 7 or 8 LED segments called a, b, c, d, e, f, g (and a dp segment for decimal point) and each segment LED is independently controlled. There are two types of 7-segment display namely Common Anode (CA) and Common Cathode (CC). Their structures are shown in Figure 3.5.1:

Chapter 3 71 Figure 3.5.1: The circuit schematic of two common types of 7-segment display To drive a CA segment display, a Logic 1 needs to be added to the common port whereas a CC segment display requires a Logic 0 for the common port. By controlling the lighting patterns of the LED segments (a, b, … f, g), we can interpret numbers and symbols. Figure 3.5.2 illustrates the working mechanism to display number 2 on a CC segment display. Figure 3.5.2: Lighting patterns of LED segments to display the number 2 A 7-segement display can display digits 0, 1…9, A, ..., F in total of 16 different symbols. The lighting patterns corresponding to each digit is shown in Table 3.7. This table is also called Look-up table. Table 3.7: Lookup table for 7-terminal common cathode digital tube CC Segement Lighting Pattern Display g f e d c b a 0 1 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 1 1 0 1 1 2 1 0 0 1 1 1 1 3 1 1 0 0 1 1 0 4 1 1 0 1 1 0 1 5 1 1 1 1 1 0 1 6

A Tutorial for FPGA beginners 72 0 0 0 0 1 1 1 7 1 1 1 1 1 1 1 8 1 1 0 1 1 1 1 9 1 1 1 0 1 1 1 A 1 1 1 1 1 0 0 B 0 1 1 1 0 0 1 C 1 0 1 1 1 1 0 D 1 1 1 1 0 0 1 E 1 1 1 0 0 0 1 F Verilog Design If we would like to manually control the displayed content, then the segment display module needs at least 4 input signals to be able to show all 16 symbols. Obviously using Behavioral level description is the best approach to implement a 7-segment driver. In Code 3.6, we described the logic behavior to implement a CC segment driver. Code 3.6: Common Cathode 7-segment Driver module segment7 ( input wire [3:0] seg_data, output reg [8:0] segment_led // MSB~LSB = SEG, DP, g, f e, d, c, b, a ) ; always @ (seg_data) begin case (seg_data) 4'b0000: segment_led = 9'h3f; // 0 4'b0001: segment_led = 9'h06; // 1 4'b0010: segment_led = 9'h5b; // 2 4'b0011: segment_led = 9'h4f; // 3 4'b0100: segment_led = 9'h66; // 4 4'b0101: segment_led = 9'h6d; // 5 4'b0110: segment_led = 9'h7d; // 6 4'b0111: segment_led = 9'h07; // 7 4'b1000: segment_led = 9'h7f; // 8 4'b1001: segment_led = 9'h6f; // 9 4'b1010: segment_led = 9'h77; // A 4'b1011: segment_led = 9'h7C; // b 4'b1100: segment_led = 9'h39; // C 4'b1101: segment_led = 9'h5e; // d 4'b1110: segment_led = 9'h79; // E 4'b1111: segment_led = 9'h71; // F endcase end endmodule FPGA Experiment According to the STEPFPGA board implementation as shown in Figure 3.5.3, we assigned segment_led[0] to segment_led[6] to segment LEDs from ‘a’ to ‘g’ respectively. The decimal

Chapter 3 73 point on the tube is assigned to segment_led[7] and the DIG which stands for the common port is attached to segment_led[8]. Figure 3.5.3: Assigning FPGA Pins to a Common Cathode Segment Display As an exercise, you can also try to use the other 4 keys of the FPGA as inputs to control another segment display on the board. Exercise The STEPFPGA board has two 7-segment displays that can display two characters concurrently. As an exercise we use 4 toggle switches to control to left tube and 4 pushbuttons to control the right segment. Once implemented the code, see if you can display F4.

A Tutorial for FPGA beginners 74 Now we can instantiate two segment7 modules to form a segment7_2, please complete the code below: module segment7_2 ( input wire [7:0] seg_data_2, output wire [17:0] segment_led_2 ); segment7 u1 ( .seg_data (seg_data_2[ 7 : 4 ]), .segment_led(segment_led_2[ 17 : 9 ]) ); segment7 u2 ( .seg_data (seg_data_2[ : ]), .segment_led(segment_led_2[ : ]) ); endmodule Make sure you match all inputs and outputs correctly to the FPGA IO pins. 3.6 Implement a Decimal Counter Counters are important modules in sequential logic. You will see counters all over the places in projects that related to time. In fact, a digital circuit is ‘unintelligent’ and has no sense of time as humans. The only way we can tell the system about time is using counters. Like microcontroller boards, the STEPFPGA board also operates at a fixed frequency (12MHz) generated by the on-board crystal. Anything regarding to time or frequency is taking reference to this 12MHz system clock. Figure 3.6.1 is an illustration to calculate the time by counting N times of the system clock cycles. Figure 3.6.1: Determining time based on number of counts Tcnt = Tclk × N A 12MHz clock has a period of 83.3ns and it is also the smallest timing resolution for counters implemented on this board. Using an internal hard-IP of Phase-locked Loop (PLL) with Lattice Diamond IDE, you can boost the clock frequency up to 400MHz. In this tutorial 12MHz is more than enough and we do not cover this part in the book. Though it sounds tedious to a human, a counter acquires the actual time such as 1s, 2s is simply by tireless counting (see Table 3.8). Note that the size of a counter must be sufficient to hold for enough bit-width for counts. As an example, a clock synchronized counter must have at least 24 bits-width to hold for 1s in real time.

Chapter 3 75 Table 3.8: Required counts and bit width of the counter for different time lengths Actual Time Counts (decimal) Counts (binary) Minimum width 1s 12, 000, 000 101101110001101100000000 24 2s 24, 000, 000 1011011100011011000000000 25 3s 36, 000, 000 10001001010101000100000000 26 4s 48, 000, 000 10110111000110110000000000 26 As a practice, we use counters to generate some time delays so that the 4 LEDs on STEPFPGA board sequentially light up with a time interval of 1s. Verilog Design Suppose we want to use a single counter to handle to work, it suggests that this counter should have at least 26 bits for hold for at least 4s (4 LEDs each with 1s). When the counter reaches to 12, 24, 36 and 48 million counts, we ask the 4 LEDs turn ON respectively. This process is illustrated in Figure 3.6.2. Figure 3.6.2: Using a counter to control the 4 LEDs in sequence Now let us write the Verilog code. First we name the module as LED_sequence and it has 4 output signals to control 4 LEDs. But what are the input signals? In previous experiments, the inputs were controlled manually with switches or pushbuttons. In this experiment, since all activities are synchronized to clk, we can use the on-board system clock being the input signal for the module. Also, we can add a manually controlled reset signal in case we want to clear the counter. Thus the definition of module is: module LED_sequence ( input clk, input rst_n, output [3:0] led ) ; Now we generate a counter.

A Tutorial for FPGA beginners 76 As you learned in Section 1.4, a counter is simple a bunch of Registers or Flip-flops. Since our counter requires 26 bits, in Verilog we will first reserve enough resources for it, as written in this one line of code: reg [25: 0] cnt; // Create a 26 bit width space for Counter If the rst_n button was manually pushed, the counter is cleared to 0. Otherwise the counter continuously increments by 1 with each clock tick. The counter will also automatically resets when it is full. In Verilog we have: always @ (posedge clk or negedge rst_n) begin if (!rst_n) cnt <= 0; else cnt <= cnt + 1'b1; end While the counter running continuously, the system should have raised flags when counter reaches to the corresponding checkpoints. In Verilog, the flags or constants can be defined as parameter, so in this code we defined four parameters: parameter t_1s = 12_000_000; //The number of counts required to count to 1 s parameter t_2s = 24_000_000; // ...2s parameter t_3s = 36_000_000; // ...3s parameter t_4s = 48_000_000; // ...4s Note that here we used non-blocking assignment <= in the code. You may still recall that in Code 3.5 we used blocking assignment =. These two types of assignments may cause confusions in Verilog, and there are lots of in-depth explanations in relevant books or articles. To put it simple, you use nonblocking assignments <= for sequential logic and blocking assignment = for combinational logic. And a good indicator for sequential logic is the presence of posedge (or negedge) in the conditions of always@() block statement. You can use either posedge clk or negedge clk to synchronize the counter, but note that their difference is a half clock cycle phase shift for the two triggering edges, you can clearly view this in Figure 3.6.3.

Chapter 3 77 Figure 3.6.3: Half system clock phase difference between rising edge and falling edge The last step to complete the code is to turn on the LEDs when counter reaches its respective time stamp. Here we introduce a new technique called conditional assignment, which is written in the following format: assign Y = (condition) ? value1 : value0; In the above sentence, when condition is true, then Y will be assigned to value1; if condition is false, Y will be assigned to value0. Using four conditional assignments to control the turn on sequence of the four LEDs. assign led{0} = (cnt < t_1s) ? 1 : 0; assign led{1} = (cnt < t_2s) ? 1 : 0; assign led{2} = (cnt < t_3s) ? 1 : 0; assign led{3} = (cnt < t_4s) ? 1 : 0; Again, you noticed above assignments are blocking assignment because they are not in sequential logic block inside of always @ (posedge clk) block statement. Code 3.6 is the complete code for this experiment. Code 3.6: Using four counters to control the on-off time of four LED lights respectively module LED_sequence ( input clk, input rst_n, output [3:0] led ) ; reg [25: 0] cnt; parameter t_1s = 12_000_000, t_2s = 24_000_000, t_3s = 36_000_000, t_4s = 48_000_000; always @ (posedge clk or negedge rst_n) begin if (!rst_n) cnt <= 0; else cnt <= cnt + 1'b1; end assign led[0] = (cnt < t_1s) ? 1 : 0; assign led[1] = (cnt < t_2s) ? 1 : 0; assign led[2] = (cnt < t_3s) ? 1 : 0; assign led[3] = (cnt < t_4s) ? 1 : 0; endmodule

A Tutorial for FPGA beginners 78 FPGA Experiment For pin assignment, we assign the input signal clk to the onboard system clock signal C1 pin of the FPGA, see Figure 3.6.4. Figure 3.6.4: Assigning the on-board system clock to the clk signal for counter This experiment once again shows the advantage of using behavioral-level description to implement sequential logic. By comparison, Figure 3.6.5 shows the structure of a 4-bit Ripple Counter in CircuitJS. Even we built a module for JK Flip-flop (D Flip-flop can do the same), generating a 26-bit Ripple Counter will have to instantiate the module by 26 times, and you also need a big comparator for conditional assignment. With behaviral-level description all these operations are implemented with few lines of code, and all complicated synthesis are taken care by the EDA tools. Figure 3.6.5: Observe the logic of the 4-bit ripple counter in CircuitJS

Chapter 3 79 Exercise In this exercise we build two D Flip-flops and add some time delay for one of them to visualize the process of writing a data into a D Flip-flop. We call this module delay_dff and it has the definition as shown in drawing: A regular D Flip-flop can be easily implemented using Behavior-level description: module dff(input clk, D, output reg Q); always @ (posedge clk) begin Q <= D; end endmodule Task 1: Implement a manually controlled D Flip-flop on STEPFPGA board. You can use a push button as the triggering clock and switch for data. The reason to use manual trigger is to give enough time for observation; the system clock is way too way for eyes to see the process. Task 2: Implement the module delay_dff. Note that this module has two D Flip-flops and one of them has a 2s delay. You can complete the code below: module delayed_dff (input clk, key, sw, output led1, led2); reg [ : ] cnt; reg delay_key; dff u1 (key, sw, led1); dff u2 (delay_key, sw, led2); always @ (posedge clk) if (!key) begin cnt <= 0; delay_key <= 0; end else if (cnt == ) begin

A Tutorial for FPGA beginners 80 cnt <= 0; delay_key <= 1; end else begin cnt <= cnt + 1; delay_key <= delay_key; end endmodule module dff(input clk, D, output reg Q); always @ (posedge clk) begin Q <= D; end endmodule Task 3: You may still remember that we mentioned the self-starting function of a counter in Section 1.4. A simple structure to add self-starting function for a 4-bit Ring Counter is to add a 3-input NOR Gate for the feedback, as drawn below: For exercise, complete the code below: module ripple4_fb ( input clk, output [3:0] led ); wire x; nor (x, , , ]); dff u1 (clk, , led[0]); dff u2 (clk, led[0], led[1]); dff u3 (clk, led[1], led[2]); dff u4 (clk, led[2], led[3]); endmodule module dff(input clk, D, output reg Q); always @ (posedge clk) begin Q <= D; end endmodule

Chapter 3 81 Referring to the pin assignments in the figure below, implement the self-starting 4-bit Ring Counter on FPGA, and observe the lighting sequence of LEDs. Note according to this pin assignment the counter only ticks when you press the pushbutton. 3.7 Implement a Frequency Divider Generating different frequencies is a must-known technique in FPGA projects, and it involves frequency multiplier using PLL (we do not cover in this tutorial) and frequency divider. We know the clock frequency on STEPFPGA is 12MHz, and using frequency divider technique allows to generate frequencies equal or lower than this number. Figure 3.7.1 shows the process of frequency divider with even divisors. Figure 3.7.1: Divide the system clock frequency with even number Suppose we have a counter cnt that counts the positive edge of the system clock clk. Here is our obseravation: • clk_div2 flips the output signal polarity when cnt is 1 • clk_div4 flips the output signal polarity when cnt is 2 • clk_div6 flips the output signal polarity when cnt is 3 thus for clk_div_N, we simply need to flip the polarity at cnt when it counts to N/2.

A Tutorial for FPGA beginners 82 If you apply the same technique for odd divisors, it may end up with getting a non 50% duty cycle due to a remainder of 1. More detailed illustration is shown in Figure 3.7.2. Therefore, using the same technique for odd divisors always exists a phase shift of half clock period. Figure 3.7.2: Divide the system clock frequency with odd number In practice, this half cycle can be neglected for larger divisors. Table 3.9 lists the duty cycles for different odd divisors from 3 to 99. In Chapter 5 for piano related projects we will introduce an advanced technique of using phase accumulator for fine tuning frequencies, but for most scenarios using clock divider will suffice. Table 3.9: The effect of different odd multiples on duty cycle Odd divisors Duty cycle By 3 1/3 ≈ 33.3% By 5 2/5 = 40% By 7 3/7 ≈ 42.9% By 9 4/9 ≈ 44.4% By 99 49/99 ≈ 49.5% Verilog Design In Verilog design, we first attempt to generate a 1Hz output signal. This means we need to divide the system clock frequency by 12 million times. The job is handled by a diligent counter which should have at least 24-bit width to hold 12,000,000 counts. This parameter N = 12_000_000 is similar as defining a constant in programming language. If you did not specify the bit-width of N, by default it will be 32 bits. module divider1 ( input clk, input rst_n, output clkout ) ; parameter N = 12_000_000; reg [23:0] cnt;

Chapter 3 83 Next, we will describe the logic behavior of the counter. In natural language, this counter is just doing the following things: • The counter starts from 0 when rst_n is triggered • The counter also starts from 0 when it reaches to 12,000,000 counts • The counter keeps incrementing if it does not reach to 1200000 counts Using behavioral level description, we can convert the above language into the Verilog code: always @ (posedge clk or negedge rst_n) begin if (!rst_n) cnt <= 1'b0; else if (cnt == (N-1) ) cnt <= 1'b0; else cnt <= cnt + 1'b1; end Eventually, we add conditional assignment to generate the output signal: when cnt reaches to N/2, the output clkout is set to 1; otherwise output clkout is set to 0. assign clkout = (cnt < N/2) ? 1'b1:1'b0; By examining the code, the only changes needed if we want to use other divisors is simply the divisor N and the size of counter WIDTH to hold the divisor. This way, we can extract the parameters to make the code more adaptive and generic. Code 3.7 is a complete code for frequency divider with arbitrary integer divisors. The parameters: #(parameter N, parameter WIDTH) are separated. Whenever we need to instantiate this module, we only need to modify the parameters inside #( ) block. You will see this in the coming experiment. Code 3.7: Frequency division by any integer module divider_integer # ( parameter WIDTH = 24, parameter N = 12000000 ) ( input clk, output reg clkout ); reg [WIDTH-1:0] cnt; always @ (posedge clk) begin if(cnt>=(N-1)) cnt <= 1'b0; else cnt <= cnt + 1'b1; clkout <= (cnt<N/2)?1'b1:1'b0; end endmodule

A Tutorial for FPGA beginners 84 FPGA Experiment In the experiment part, we generate two output frequencies 0.5Hz and 2Hz by instantiating two submodules. To do so, we create a top module called divider_top, and instantiate frequency dividor module (code 3.7) twice, where the parameters of divisors are set to 6,000,000 and 24,000,000 respectively. Make sure the submodules are placed in the same project directory of the top module. module divider_top ( input wire clk, input wire rst_n, output wire led_2hz, output wire led_05hz ) ; divider_integer # (.WIDTH (24), .N (6_000_000) ) clk_2hz ( .clk (clk), .clkout (led_2hz) ) ; divider_integer # (.WIDTH (24), .N (24_000_000) ) clk_05hz ( .clk (clk), .clkout (led_05hz) ) ; endmodule Exercise In Section 1.4 we introduced the structure of a 4-bit shift register. If the register is synchronized to system clock, the transition of data is impossible to observe since the clock is way faster than our eyes to see. With frequency divider technique, can generate a slow clock to synchronize the register to the shifting process can be clearly observed. First, we draw the block diagram of this 4-bit shift register: As the reference, the module shift4 below is synchronized directly to the system clock. Note that here we also instantiated the D Flip-flop submodules dff in Section 3.6 exercise.

Chapter 3 85 module shift4 ( input clk, input dataIn, output [3:0] led ); dff u1 (clk, dataIn, led[0]); dff u2 (clk, led[0], led[1]); dff u3 (clk, led[1], led[2]); dff u4 (clk, led[2], led[3]); endmodule Task 1: Generate a 1Hz clock and use this slow clock to synchronize the shift register module shift4_slow. Complete the Verilog code of the shift4_slow module and observe the result on the FPGA. module shift4_slow ( input clk, rst_n, input dataIn, output [3:0] led ); wire clk1hz; divider_integer # (.WIDTH ( ),.N ( )) u0( .clk ( ), .clkout ( ) ); dff u1 (clk1hz, , ); dff u2 (clk1hz, , ); dff u3 (clk1hz, , ); dff u4 (clk1hz, , ); endmodule Task 2: Build an 8-bit shift register module shift8_slow which is synchronized to a 1Hz clock on STEPFPGA board.

A Tutorial for FPGA beginners 86 Task 3: Draw the block diagram of a 4-bit shift register that is serial input and serial output, and implement this new module on STEPFPGA board.

Chapter 4 87 Chapter 4: Build 74xx Chips with FPGA 4.1 Implement a 74HC08 Quad 2-input AND gate In previous section we have implemented fundamental combinational and sequential modules on the STEPFPGA board and experimented results with the on-board components. In this section we will implement some common 74 series ICs and use the external GPIOs to verify the result. 74HC08 Logic Functions The datasheet of 74HC08 can be found on Texas Instrument by searching the part number. The datasheet specifies that the chip has 4 pairs of AND gates which operate in the range of 2V to 6V, and the logic functions of all pins are summarized in Figure 4.1.1. = = = = Figure 4.1.1: Pin Diagram of 74HC08 Figure 4.1.2 shows a simple circuit schematic to test one of the AND gate of the actual chip: two green LEDs with current limiting resistors are connected at the input side. Let’s consider the condition when SW1 is closed and SW2 is open, then pin A1 is connected to 5V indicating a logic High; whereas B1 is a logic Low due to the pull-down resistor R2. Theoretically, we should expect a Low voltage from the output Y1 due to the logic operation of an AND gate.

A Tutorial for FPGA beginners 88 Figure 4.1.2: A Simple Test Circuit for 74HC08 Logic Functions Figure 4.1.3 shows a breadboard layout to build the above circuit in practice, so you can physically test and validate the actual circuit and chip functionality. Figure 4.1.3: Breadboard Layout for 74HC08 Test Circuit Assuming now we would like to design a chip in which the logic behavior is exactly same with 74HC08, thus we will implement the code on STEPFPGA first, then use the extendable 36 GPIOs to connect other peripherals such as resistors, switches, and LEDs to test and verify the chip we built. Implement 74HC08 with FPGA Implementing a 74HC08 will utilize the programmable GPIOs of the STEP FPGA. According to datasheet, this IC has 16 pins in which: • 2 power pins for VCC and GND • 8 input pins for the four AND gates • 4 output pins for the four AND gates The Verilog code for 74HC08 module is given in code 4.1. Though you can define the inputs and outputs using signal names such as A1, B1, Y1, a more secure way to reduce chances of mistaking pin numbers is to define all pins according to the sequence on datasheet. Code 4.1: Verilog code to implement 74HC08 module sn74hc08 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8, pin9,pin10,pin11,pin12,pin13,pin14); input pin1,pin2,pin4,pin5,pin9,pin10,pin12,pin13; output pin3,pin6,pin8,pin11; output pin7,pin14; // connects to Vcc and GND wire A1,B1,Y1,A2,B2,Y2,A3,B3,Y3,A4,B4,Y4; assign A1 = pin1; assign B1 = pin2; assign A2 = pin4; assign B2 = pin5; assign A3 = pin9; assign B3 = pin10; assign A4 = pin12; assign B4 = pin13; assign pin3 = Y1; assign pin6 = Y2; assign pin8 = Y3;

Chapter 4 89 assign pin11 = Y4; assign pin7 = 1'b0; assign pin14 = 1'b1; assign Y1 = A1 & B1; assign Y2 = A2 & B2; assign Y3 = A3 & B3; assign Y4 = A4 & B4; endmodule Most IDE will generate a Design Summary documentation once you have finished the “Run” step after assigning all module inputs/outputs to FPGA pins. For example, in STEP FPGA WebIDE once the FPGA mapping is completed, we can check the Design Summary in run.log, see Figure 4.1.4. Figure 4.1.4: Design Summary in Run.log for Code 4.1 The summary page lists the usage of FPGA resources to implement the module, particularly the number of registers number of LUTs and number of PIO (Programmable I/O). In this example the resource occupation seems insignificant comparing to the plenty resources available in this MXO2- 4000 version of FPGA, however, complicated digital system may require many resources. Also, improper design of the system architecture could waste lots of logic units. This book does not go into details of architectures, but it’s a good habit to be aware of the utilization efficiency of your design. 4.2 Implement a 74HCF283 4-bit Binary Full Adder 74F283 is a 4-bit binary Full Adder with fast carry, which is also referred as carry-lookahead adder. Comparing to the simpler Ripple-carry adder, which is constructed by simply cascading four full adders learned in Section 3.2, a carry-lookahead adder improves speed by reducing the amount of time required to determine carry bits.

A Tutorial for FPGA beginners 90 74F283 Logic Functions The datasheet of 74F283 can be found in Texas Instruments products, in Figure 4.2.1 we listed the pin definitions of the chip: (a) Pin mapping diagram (b) Logic Function Figure 4.2.1: Pin Diagram of 74F283 This chip operates at ideally 5V. For the purpose of hands-on practice, you may attempt building a testing circuit on breadboard, but here we neglect this step. Implement 74F283 with FPGA A 74F283 has the following input and output pins: • 2 power pins for VCC and GND • 8 input pins for the two 4-bit addends • 1 input pin for initial carry input sent from the previous stage • 4 output pins for the 4-bit sum • 1 output pin for final carry output The Verilog code for 74F283 module is given in code 4.2. Comparing to the logic diagram of 74F283 in datasheet, you will be surprised by the fact using such complicated structure can be synthesized with a line simple dataflow assignment in Verilog, though lots of complicated computations and internal wiring were handled by the EDA tool. Code 4.2: Verilog code to implement 74F283 module sn74hcf283 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8, pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16); input pin5,pin3,pin14,pin12,pin6,pin2,pin15,pin11; // two 4-bit Addends input pin7; // Initial Carry input output pin9; // Final Carry output output pin8,pin16; // Connect to VCC and GND output pin4,pin1,pin13,pin10; // 4-bit output Sum wire [3:0] a,b,sum; wire ci,co; assign pin8 = 1'b0; assign pin16 = 1'b1; assign a[0] = pin5; assign a[1] = pin3;

Chapter 4 91 assign a[2] = pin14; assign a[3] = pin12; assign b[0] = pin6; assign b[1] = pin2; assign b[2] = pin15; assign b[3] = pin11; assign ci = pin7; assign pin9 = co; assign pin4 = sum[0]; assign pin1 = sum[1]; assign pin13 = sum[2]; assign pin10 = sum[3]; assign {co,sum} = a + b + ci; endmodule 4.3 Implement a 74HC138 3-8 Decoder 74HC138 Logic Functions Figure 4.3.1 is the pin diagram of 74HC138, you noticed that an inverted sign is added to the output signals from Y0 to Y7. The pin configuration of 74HC138 given in Texas Instruments datasheet does not explicitly mention the output polarity, but referring to the functional block diagram we see eight inverters were added to the output signals. Figure 4.3.1: Pin Diagram of 74HC138 The output in this structure uses inverted logic which is same to the eight LEDs on the STEP FPGA board. A simple test circuit on breadboard is shown in Figure 4.3.2 where you can see the logic inversion by observing the ON/OFF conditions at the output LEDs.

A Tutorial for FPGA beginners 92 Figure 4.3.2: Build a Simple Test Circuit for 74HC138/74LS138 Implement 74HC138 with FPGA A 74HC138 has the following input and output pins: • 2 power pins for VCC and GND • 3 input pins for the data selector address inputs (for MUX8 function) • 3 input strobe signals • 1 output pin for final carry output Similar to the 3-8 Decoder implemented Section 3.4, using behavioral description is efficient to specify the logic behavior of 74HC138, as seen in Code 4.3. Code 4.3: Verilog code to implement 74HC138 module sn74hc138 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8, pin9,pin10,pin11,pin12,pin13,pin14,pin15,pin16); input pin1,pin2,pin3; // 3 inputs corresponding to the address location input pin4,pin5,pin6; // 3 inputs for strobe enable output pin7,pin9,pin10,pin11,pin12,pin13,pin14,pin15; output pin8,pin16; // connects to VCC and GND wire [2:0] a ; reg [7:0] q ; wire sel;

Chapter 4 93 assign pin8 = 1'b0; assign pin16 = 1'b1; assign a = {pin3, pin2, pin1}; assign sel = (~pin4) & (~pin5) & pin6; assign pin7 = q[7]; assign pin9 = q[6]; assign pin10 = q[5]; assign pin11 = q[4]; assign pin12 = q[3]; assign pin13 = q[2]; assign pin14 = q[1]; assign pin15 = q[0]; always@(a,sel) begin if(!sel) q = 8'b1111_1111; else begin case(a) 3'b000: q = 8'b1111_1110; 3'b001: q = 8'b1111_1101; 3'b000: q = 8'b1111_1011; 3'b000: q = 8'b1111_0111; 3'b000: q = 8'b1110_1111; 3'b000: q = 8'b1101_1111; 3'b000: q = 8'b1011_1111; 3'b000: q = 8'b0111_1111; default:q = 8'b1111_1111; endcase end end endmodule 4.4 Implement a 74HC74 Dual Positive Edge Triggered D-Flipflop 74HC74 Logic Functions 74HC74 contains two D-Flipflops triggered by the positive or rising edge of the clock signal. It also has the functionality to preset a data for initial stored value and a clear signal to reset what’s being previously stored. The pin diagram is given in Figure 4.4.1. Pin Description CLR’ Clear input, active low D Data input CLK Positive edge trigger clock PRE’ Preset input, active low Q Output Q’ Inverted output Figure 4.4.1: Pin Diagram of 74HC138 Figure 4.4.2 shows a simple testing circuit for this chip. The pushbutton P1 is a manually triggered clock signal and toggle switch SW1 represents the input data.

A Tutorial for FPGA beginners 94 Figure 4.4.2: Build a Simple Test Circuit for 74HC74 Implement 74HC74 with FPGA A 74HC74 has the following input and output pins: • 2 power pins for VCC and GND • 2 input pins for clock signal CLK • 2 input pins for SET • 2 input pins for RESET • 2 input pins for DATA • 2 output pins for Q • 2 output pins that are complementary to Q The Verilog code for 74HC74 using behavior description is in Code 4.4. The clock signals are positive edge triggered so we use posedge; the triggering for clear (or reset) is not explicitly specified in datasheet so by default we treat it as negedge. Code 4.4: Verilog code to implement 74HC138 module sn74hc74 (pin1,pin2,pin3,pin4,pin5,pin6,pin7,pin8, pin9,pin10,pin11,pin12,pin13,pin14); input pin3,pin11; // 2 inputs for CLOCK input pin1,pin13; // 2 inputs for RESET input pin4,pin10; // 2 inputs for SET input pin2,pin12; // 2 inputs for DATA output pin7,pin14; // Connects to VCC and GND output pin5,pin6,pin8,pin9;

Chapter 4 95 wire clk1,clk2,reset1_n,reset2_n,set1_n,set2_n,d1,d2; reg [1:0] q1,q2; assign pin7 = 1'b0; assign pin14 = 1'b1; assign clk1 = pin3; assign clk2 = pin11; assign reset1_n = pin1; assign reset2_n = pin13; assign set1_n = pin4; assign set2_n = pin10; assign d1 = pin2; assign d2 = pin12; assign pin5 = q1[1]; //1Q assign pin6 = q1[0]; //1Q' assign pin9 = q2[1]; //2Q assign pin8 = q2[0]; //2Q' //Building the first channel of D flipflop; always @ (negedge reset1_n or negedge set1_n or posedge clk1) begin if(reset1_n==0) q1<=2'b01; else if(set1_n==0) q1<=2'b10; else q1<={d1,~d1}; end //Building the second channel of D flipflop always @ (negedge reset2_n or negedge set2_n or posedge clk2) begin if(reset2_n==0) q2<=2'b01; else if(set2_n==0) q2<=2'b10; else q2<={d2,~d2}; end endmodule This is the first sequential logic chip implemented in this section, the design summary of this code shows that 12 out of 4630 registers and 15 LUTs have been used to implement 74HC74. The 12 registers coming from the two D Flip-Flop channels each requires 6 registers for holding three 2-bit data. Figure 4.4.4: Design Summary in Run.log for Code 4.4