Microcontroller & Embedded Programming
(MEP)
SUBJECT CODE: ITC501
RESOURCE MATERIAL
Subject-In-Charge: Prof. Selvin Furtado
Third Year Information Technology
(Academic Year 2019-2020)
TE-IT: MEP Contents
1 Contents
Contents .......................................................................................................... 2
Syllabus............................................................................................................ 9
0 Module 0 – Prerequisite ........................................................................... 12
0.1 Revision of Microcomputer System Terminologies................................................................. 12
0.2 High level, Machine level and Assembly level Programming Language .................................. 12
0.2.1 Machine Language ........................................................................................................... 12
0.2.2 Assembly Language.......................................................................................................... 12
0.2.3 High level Language ......................................................................................................... 13
0.3 Difference between Microprocessor and Microcontroller...................................................... 14
1 Module 1 - Introduction to Embedded Systems........................................ 17
1.1 Overview of Embedded System Architecture.......................................................................... 17
1.2 Application areas of Embedded Systems................................................................................. 19
1.3 Categories of Embedded Systems ........................................................................................... 21
1.3.1 Stand-alone embedded systems...................................................................................... 21
1.3.2 Real-time systems............................................................................................................ 22
1.3.3 Networked information appliances ................................................................................. 22
1.3.4 Mobile devices ................................................................................................................. 23
1.4 Specialties of Embedded Systems ........................................................................................... 24
1.4.1 Reliability ......................................................................................................................... 24
1.4.2 Performance .................................................................................................................... 24
1.4.3 Power Consumption ........................................................................................................ 24
1.4.4 Cost .................................................................................................................................. 24
1.4.5 Size ................................................................................................................................... 25
1.4.6 Limited User Interface ..................................................................................................... 25
1.4.7 Software Upgradation Capability..................................................................................... 25
1.5 Recent trends in Embedded Systems. ..................................................................................... 26
1.5.1 Processor Power .............................................................................................................. 26
1.5.2 Memory ........................................................................................................................... 26
1.5.3 Operating Systems ........................................................................................................... 26
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1.5.4 Communication Interface and Network Capability ......................................................... 26
1.5.5 Programming Languages ................................................................................................. 27
1.5.6 Development Tools.......................................................................................................... 27
1.5.7 Programming Hardware .................................................................................................. 27
1.6 Brief Introduction to Embedded microcontroller cores CISC, RISC, ARM, DSP and SoC. ........ 27
1.6.1 CISC vs RISC ...................................................................................................................... 27
1.6.2 ARM ................................................................................................................................. 31
1.6.3 DSP ................................................................................................................................... 31
1.6.4 SoC ................................................................................................................................... 35
1.7 Design Challenge — Optimizing Design Metrics...................................................................... 36
1.7.1 Common Design Metrics.................................................................................................. 36
2 Module 2 - The Microcontroller Architecture and Programming of 8051 .. 38
2.1 Introduction to 8051 Microcontroller ..................................................................................... 38
2.2 Architecture ............................................................................................................................. 38
2.2.1 ALU................................................................................................................................... 38
2.2.2 Boolean Processor ........................................................................................................... 39
2.3 Program and Data Memories .................................................................................................. 39
2.3.1 Stack Pointer and Program Counter ................................................................................ 39
2.3.2 Special Function Registers (SFR) ...................................................................................... 41
2.4 Pin configuration...................................................................................................................... 46
2.5 Memory Organization.............................................................................................................. 50
2.6 Input /Output Ports ................................................................................................................. 52
2.6.1 Port 0................................................................................................................................ 52
2.6.2 Port 1................................................................................................................................ 53
2.7 Counter and Timers ................................................................................................................. 57
2.7.1 Timer Counter Interrupts................................................................................................. 58
2.7.2 Timing .............................................................................................................................. 58
2.7.3 Timer Modes of Operation .............................................................................................. 59
2.7.4 Timer Program ................................................................................................................. 61
2.7.5 Counting........................................................................................................................... 62
2.8 Serial Communication.............................................................................................................. 63
2.8.1 Serial Data Interrupt ........................................................................................................ 63
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TE-IT: MEP Contents
2.8.2 Data Transmission............................................................................................................ 63
2.8.3 Data Reception ................................................................................................................ 64
2.8.4 Serial Data Transmission Modes...................................................................................... 66
2.9 Interrupts ................................................................................................................................. 70
2.9.1 Timer Interrupt Flag......................................................................................................... 72
2.9.2 Serial Port Interrupt ......................................................................................................... 72
2.9.3 External Interrupts........................................................................................................... 72
2.9.4 Reset ................................................................................................................................ 73
2.9.5 Interrupt Control.............................................................................................................. 73
2.9.6 Interrupt Enable/Disable ................................................................................................. 74
2.9.7 Interrupt Priority.............................................................................................................. 74
2.9.8 Interrupt Destinations ..................................................................................................... 75
2.9.9 Software Generated Interrupts ....................................................................................... 75
2.10 Instruction Set with Examples ................................................................................................. 76
2.11 Addressing Modes ................................................................................................................. 106
2.11.1 Immediate Addressing Mode ........................................................................................ 106
2.11.2 Register Addressing Mode............................................................................................. 106
2.11.3 Direct Addressing Mode ................................................................................................ 109
2.11.4 Indirect Addressing Mode.............................................................................................. 111
2.12 Development Tools................................................................................................................ 112
2.13 Assembler Directives ............................................................................................................. 112
2.14 Rules for labels in Assembly language ................................................................................... 114
2.15 Programs for PORT................................................................................................................. 115
3 Module 3 - Interfacing with 8051 Microcontroller .................................. 118
3.1 Interfacing with ADC.............................................................................................................. 118
3.2 Interfacing with DAC.............................................................................................................. 126
3.3 Programs of 8051:.................................................................................................................. 129
3.4 Interfacing with Stepper Motor............................................................................................. 134
Program ......................................................................................................................................... 137
3.5 Interfacing the keypad to 8051.............................................................................................. 139
3.6 Interfacing LCD to 8051 ......................................................................................................... 147
3.7 Interfacing 8255 – Programable Peripheral Interface ........................................................... 152
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4 Module 4 - ARM 7 Architecture .............................................................. 159
4.1 Architectural inheritance ....................................................................................................... 159
4.1.1 Features used................................................................................................................. 159
4.1.2 Features rejected ........................................................................................................... 159
4.1.3 Simplicity........................................................................................................................ 160
4.2 Principal features of the ARM architecture. .......................................................................... 160
4.3 The RISC design philosophy ................................................................................................... 161
4.4 Architecture (ARM core data-flow model) ............................................................................ 161
4.4.1 #Barrel shifter:................................................................................................................ 162
4.5 The ARM programmer's model ............................................................................................. 163
4.5.1 The Current Program Status Register (CPSR)................................................................. 164
4.5.2 The memory system ...................................................................................................... 166
4.5.3 Load-store architecture ................................................................................................. 166
4.5.4 Supervisor mode............................................................................................................ 167
4.5.5 The ARM instruction set ................................................................................................ 167
4.5.6 The I/O system............................................................................................................... 167
4.5.7 ARM exceptions ............................................................................................................. 168
4.6 Registers................................................................................................................................. 168
4.7 Banked Registers.................................................................................................................... 169
4.8 Endian (E) bit:......................................................................................................................... 173
4.9 ARM development tools ........................................................................................................ 174
4.9.1 The ARM C compiler ...................................................................................................... 174
4.9.2 ARM development board............................................................................................... 176
4.9.3 Software Toolkit............................................................................................................. 176
4.9.4 JumpStart....................................................................................................................... 177
4.10 ARM Instruction Set............................................................................................................... 177
4.10.1 Data Processing.............................................................................................................. 177
4.10.2 Data transfer instructions .............................................................................................. 182
4.10.3 Control Flow Instructions............................................................................................... 189
4.11 Writing simple assembly language programs........................................................................ 193
4.12 ARM Addressing Modes......................................................................................................... 195
4.12.1 Data-processing operands ............................................................................................. 195
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4.12.2 The shifter operand ....................................................................................................... 195
4.12.3 Immediate...................................................................................................................... 196
4.12.4 Register .......................................................................................................................... 197
4.12.5 Logical Shift Left by Immediate...................................................................................... 197
4.12.6 Logical Shift Left by Register .......................................................................................... 199
4.12.7 Logical Shift Right by Immediate ................................................................................... 199
4.12.8 Logical Shift Right by Register........................................................................................ 199
4.12.9 Arithmetic Shift Right by Immediate ............................................................................. 201
4.12.10 Arithmetic Shift Right by Register.............................................................................. 201
4.12.11 Rotate Right by Immediate ........................................................................................ 201
4.12.12 Rotate Right by Register ............................................................................................ 203
4.12.13 Rotate Right with Extend ........................................................................................... 203
4.13 Memory Access...................................................................................................................... 203
4.13.1 Immediate Offset........................................................................................................... 203
4.13.2 Register Offset ............................................................................................................... 205
4.13.3 Scaled Register Offset.................................................................................................... 205
4.13.4 Immediate Pre-indexed ................................................................................................. 207
4.13.5 Register Pre-indexed...................................................................................................... 207
4.13.6 Scaled Register Pre-indexed .......................................................................................... 207
4.13.7 Immediate Post-indexed................................................................................................ 209
4.13.8 Register Post-indexed .................................................................................................... 209
4.13.9 Scaled Register Post-indexed......................................................................................... 211
4.14 The ARM Pipeline................................................................................................................... 211
4.14.1 3-stage pipeline ARM organization................................................................................ 211
4.14.2 Pipeline Executing Characteristics ................................................................................. 212
4.14.3 PC behaviour.................................................................................................................. 214
5 Module 5 - Open Source RTOS................................................................ 215
5.1 Basics of RTOS: Real time concepts ....................................................................................... 215
5.2 Hard Real time and Soft Real-time ........................................................................................ 215
5.2.1 Hard ............................................................................................................................... 215
5.2.2 Firm ................................................................................................................................ 215
5.2.3 Soft................................................................................................................................. 216
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TE-IT: MEP Contents
5.3 Differences between GPOS & RTOS....................................................................................... 216
5.4 Basic architecture of an RTOS................................................................................................ 217
5.5 Scheduling Systems................................................................................................................ 217
5.5.1 Non-pre-emptive Scheduling......................................................................................... 217
5.5.2 Pre-emptive Scheduling................................................................................................. 219
5.6 Performance Matrix in scheduling models............................................................................ 220
5.7 Priority Inversion.................................................................................................................... 220
5.7.1 Problem of priority inversion:........................................................................................ 220
5.7.2 Solving the problem of priority inversion: ..................................................................... 222
5.8 Inter-Process Communication ............................................................................................... 222
5.8.1 Shared Memory ............................................................................................................. 222
5.8.2 Message Passing ............................................................................................................ 223
5.8.3 Remote Procedure Call (RPC) and Sockets .................................................................... 225
5.9 Interrupt management in RTOS environment....................................................................... 226
5.9.1 Interrupt Service Routine (ISR) ...................................................................................... 227
5.10 Memory Management........................................................................................................... 228
5.11 File Systems............................................................................................................................ 229
5.12 I/O Systems ............................................................................................................................ 229
5.13 Advantage and Disadvantage of RTOS................................................................................... 229
5.13.1 Advantages: ................................................................................................................... 229
5.13.2 Disadvantages:............................................................................................................... 230
5.14 Portable Operating System Interface (POSIX) ....................................................................... 230
5.15 RTOS issues – selecting a Real Time Operating System......................................................... 230
5.15.1 Functional Requirements............................................................................................... 230
5.15.2 Non-functional Requirements ....................................................................................... 231
5.16 RTOS comparative study........................................................................................................ 232
5.16.1 QNX Neutrino................................................................................................................. 232
5.16.2 VxWorks ......................................................................................................................... 232
5.16.3 MicroC/OS-II .................................................................................................................. 232
5.16.4 RTLinux........................................................................................................................... 233
6 Module 6 - Introduction to Embedded target boards.............................. 234
6.1 Raspberry Pi & Arduino.......................................................................................................... 234
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TE-IT: MEP Contents
6.1.1 Differences between Raspberry Pi and Arduino............................................................ 235
6.1.2 How to decide between Raspberry Pi and Arduino....................................................... 236
6.2 Intel Galileo............................................................................................................................ 238
6.2.1 Features of the Intel® Galileo Board.............................................................................. 238
6.3 Difference between Intel Galileo, Raspberry Pi, Arduino Yun............................................... 239
6.4 Arduino Libraries.................................................................................................................... 241
6.4.1 Standard Libraries .......................................................................................................... 241
6.4.2 101 Only Libraries .......................................................................................................... 242
6.4.3 Due Only Libraries.......................................................................................................... 242
6.4.4 Due, Zero and MKR1000 Libraries ................................................................................. 242
6.4.5 Zero, MKRZERO and MKR1000 Libraries........................................................................ 242
6.4.6 WiFi 101 and MKR1000 Library ..................................................................................... 242
6.4.7 MKR WiFi 1010, MKR VIDOR 4000 and Arduino UNO WiFi Rev.2 ................................. 243
6.4.8 MKR Motor Carrier Only Library .................................................................................... 243
6.4.9 MKR FOX 1200 only Library ........................................................................................... 243
6.4.10 MKR WAN 1300 only Library.......................................................................................... 243
6.4.11 MKR GSM 1400 only Library .......................................................................................... 243
6.4.12 MKR NB 1500 only Library ............................................................................................. 243
6.4.13 Esplora Only Library ....................................................................................................... 243
6.4.14 Arduino Robot Library.................................................................................................... 243
6.4.15 Yún devices Library ........................................................................................................ 243
6.4.16 USB Libraries (Leonardo, Micro, Due, Zero and Esplora)............................................... 243
6.4.17 Contributed Libraries ..................................................................................................... 243
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TE-IT: MEP Syllabus
2 Syllabus
Course Code Course Name Theory Practical Tutorial Theory Oral & Practical Tutorial Total
ITC501 Microcontroller and 04 -- 04 -- -- 04
Embedded Programming
Examination Scheme
Course Course Name Theory Marks Oral & Oral Total
Code Practical
Internal assessment
Test1 Test2 Avg. of End Sem. Term
two Tests Exam Work
ITC501 Microcontroller and 20 20 20 80 -- -- -- 100
Embedded Programming
2.1 Course Objectives
Students will try to learn:
1. The concepts and architecture of embedded systems
2. Basic of microcontroller 8051.
3. The concepts of microcontroller interface.
4. The concepts of ARM architecture
5. The concepts of real-time operating system
6. Different design platforms used for an embedded systems application
2.2 Course Outcomes
Students will be able to:
1. Explain the embedded system concepts and architecture of embedded systems
2. Describe the architecture of 8051 microcontroller and write embedded
programs for 8051 microcontrollers.
3. Design the interfacing for 8051 microcontrollers.
4. Understand the concepts of ARM architecture.
5. Demonstrate the open source RTOS and solve the design issues for the same.
6. Select elements for an embedded systems tool.
2.3 Prerequisite:
COA, Microprocessors and Assembly Programming languages
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TE-IT: MEP Syllabus
2.4 Contents Hrs Marks CO
Mapping
Sr. Module Detailed Content
No.
0 Prerequisite Revision of microcomputer system terminologies, High 02 --
level, Machine level and Assembly level programming
language, difference between microprocessor and
microcontroller.
I Introduction to Overview of Embedded System Architecture, Application 05 12 CO1
Embedded areas, Categories of embedded systems, specialties of
systems embedded systems. Recent trends in embedded systems.
Brief introduction to embedded microcontroller cores
CISC, RISC, ARM, DSP and SoC.
II The Introduction to 8051 Microcontroller, Architecture, Pin 14 34 CO2
Microcontroller configuration, Memory organization, Input /Output Ports,
Architecture and Counter and Timers, Serial communication, Interrupts.
Programming of Instruction set. Addressing modes, Development tools,
8051: Assembler Directives, Programming based on Arithmetic &
Logical Operations, I/O parallel and serial ports, Timers &
Counters, and ISR.
III Interfacing with Interfacing ADC, DAC, Stepper motor, LCD, KBD matrix, 06 14 CO3
8051 8255 PPI.
Microcontroller
IV ARM 7 Architectural inheritance, Detailed study of Programmer’s 10 24 CO4
Architecture model, ARM Development tools, Instruction set: Data 17 CO5
processing, Data Transfer, Control flow. Addressing modes.
V Open source Writing simple assembly language programs. Pipelining,
RTOS Brief introduction to exceptions and interrupts handling.
Basics of RTOS: Real-time concepts, Hard Real time and 07
Soft Real-time, differences between general purpose OS &
RTOS, basic architecture of an RTOS, scheduling systems,
inter-process communication, performance Matrix in
scheduling models, interrupt management in RTOS
environment, memory management, file systems, I/O
systems, advantage and disadvantage of RTOS. POSIX
standards, RTOS issues – selecting a Real Time Operating
System, RTOS comparative study.
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TE-IT: MEP Introduction to Arduino, Raspberry Pi, ARM Cortex, Intel 08 Syllabus
VI Introduction to Galileo etc. Open- source prototyping platforms. Basic 19 CO6
Arduino programming; Extended Arduino libraries;
Embedded Arduino-based Internet communication; Raspberry pi;
target boards ARM Cortex Processors; Intel Galileo boards; Sensors and
Interfacing: Temperature, Pressure, Humidity.
2.5 Text Books:
1. M. A. Mazidi, J. G. Mazidi, R. D., McKinlay, “The 8051 microcontroller & Embedded systems
Using Assembly and C”, Pearson, 3rd edition.
2. Embedded / real – time systems: concepts, design & programming, Black Book, Dr. K. V. K. K.
Prasad, Dreamtech press, Reprint edition 2013
3. Shibu K. V., “Introduction to embedded systems”, McGraw Hill
2.6 References:
1. Laya B. Das, “Embedded systems an integrated approach”, Pearson, Third impression, 2013
2. Steve Furber, “ARM System on chip Architecture”, Pearson, edition second
3. Michael Margolis, “Arduino Cookbook”, O’reilly
4. Simon Monk,” Raspberry Pi Cookbok”, O’reilly
5. Raspberry Pi User Guide.
6. Massimo Banzi, “Getting Started with Arduino: The Open Source Electronics Prototyping
Platform (Make)”, O'Reilly Media.
2.7 Assessment:
2.7.1 Internal Assessment for 20 marks:
• Consisting of Two Compulsory Class Tests
• Approximately 40% to 50% of syllabus content must be covered in First test and remaining
40% to 50% of syllabus contents must be covered in second test.
End Semester Examination: Some guidelines for setting the question papers are as:
• Weightage of each module in end semester examination is expected to be/will be proportional
to number of respective lecture hours mentioned in the syllabus.
• Question paper will comprise of total six questions, each carrying 20 marks.
• Q.1 will be compulsory and should cover maximum contents of the syllabus.
• Remaining question will be mixed in nature (for example if Q.2 has part (a) from module 3 then
part (b) will be from any other module. (Randomly selected from all the modules.)
• Total four questions need to be solved.
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TE-IT: MEP Module 0 – Prerequisite
0 Module 0 – Prerequisite
0.1 Revision of Microcomputer System Terminologies
Numbering and Coding System
Number System Conversions
Logic Gates
Bit, Nibble, Byte, Word
Internal Organization of Computer
RAM/ROM
0.2 High level, Machine level and Assembly level Programming
Language
0.2.1 Machine Language
Machine Language is the language written as strings of binary 1’s and 0’s. It is the only language which
a computer understands without using a translation program.
A machine language instruction has two parts. The first part is the operation code which tells the
computer what function to perform and the second part is the operand which tells the computer
where to find or store the data which is to be manipulated.
A programmer needs to write numeric codes for the instruction and storage location of data.
Disadvantages —
1. It is machine dependant i.e. it differs from computer to computer.
2. It is difficult to program and write
3. It is prone to errors
4. It is difficult to modify
0.2.2 Assembly Language
It is a low-level programming language that allows a user to write a program using alphanumeric
mnemonic codes, instead of numeric codes for a set of instructions.
It requires a translator known as assembler to convert assembly language into machine language so
that it can be understood by the computer. It is easier to remember and write than assembly language.
Assembler — It is a computer program which converts or translates assembly language into machine
language. It assembles the machine language program in the main memory of the computer and
makes it ready for execution.
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TE-IT: MEP Module 0 – Prerequisite
Advantages —
1. It is easy to understand and use.
2. It is easy to locate and correct errors.
3. It is easier to modify.
Disadvantages —
1. It is machine dependant.
0.2.3 High level Language
It is a machine independent language. It enables a user to write programs in a language which
resembles English words and familiar mathematical symbols. COBOL was the first high level language
developed for business.
Each statement in a high-level language is a micro instruction which is translated into several machine
language instructions.
Compiler – is a translator program which translates a high-level programming language into
equivalent machine language programs. It compiles a set of machine language instructions for every
high-level language program.
Source code – It is the input or the programming instructor of a procedural language.
The compiler translates the source code into machine level language which is known as object code.
Object code can be saved and executed as and when desired by the user.
Source Code -> Language Translator Program -> Object code
High level language -> Machine level language
Linker – A program used with a compiler to provide links to the libraries needed for an executable
program. It takes one or more object code generated by a compiler and combines them into a single
executable program.
Interpreter – It is a translator used for translating high level language into the desired output. It takes
one statement, translates it into machine language instructions and then immediately executes the
result. Its output is the result of program execution.
Advantages of High-level Language —
1. It is machine independent.
2. It is easier to learn and use.
3. It is easier to maintain and gives few errors.
Disadvantages —
1. It lowers efficiency.
2. It is less flexible.
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TE-IT: MEP Module 0 – Prerequisite
0.3 Difference between Microprocessor and Microcontroller
Figure 1 Block Diagram of a Microprocessor
Figure 2 Block Diagram of Microcontroller [14]
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TE-IT: MEP Module 0 – Prerequisite
Sr. Microprocessor
Microcontroller
1 Figure 1 Block Diagram of a Microprocessor Figure 2 Block Diagram of Microcontroller
2 A microprocessor is a general-purpose digital Microcontroller is a true microcomputer on a
computer central processing unit (CPU). chip. Typically used for carrying out specific
tasks.
3 To make a complete microcomputer, one It incorporates all of the features found in a
must add memory, usually read-only program microprocessor CPU: ALU, PC, SP and
memory (ROM) and random-access data registers. It also has added the other features
memory (RAM), memory decoders, an needed to make a complete computer: ROM,
oscillator and a number of input/output (I/O) RAM, parallel I/O, serial I/O, counters, and a
devices, such as parallel and serial data ports. clock circuit.
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TE-IT: MEP Module 1 - Introduction to Embedded Systems
1 Module 1 - Introduction to Embedded Systems
1.1 Overview of Embedded System Architecture
An embedded system can be defined as a computing device that does a specific focused job.
Appliances such as the air-conditioner, VCD player, DVD player, printer, fax machine, mobile phone
etc. are examples of embedded systems. Each of these applications will have a processor and special
hardware to meet the specific requirement of the application along with the embedded software that
is executed by the processor for meeting for that specific requirement. The embedded software is also
called “firmware’’.
Every embedded system consists of custom-built hardware built around a Central Processing Unit
(CPU). This hardware also contains memory chips onto which the software is loaded. The software
residing on the memory chip is also called the ‘firmware’. The embedded system architecture can be
represented as a layered architecture as shown in Figure 3. The operating system runs above the
hardware, and the application software runs above the operating system. The same architecture is
applicable to any computer including a desktop computer. However, there are significant differences.
It is not compulsory to have an operating system in every embedded system. For small appliances such
as remote-control units, air-conditioners, toys etc., there is no need for an operating system and you
can write only the software specific to that application. For applications involving complex processing,
it is advisable to have an operating system. In such a case, you need to integrate the application
software with the operating system and then transfer the entire software on to the memory chip, the
software on to the memory chip. Once the software is transferred to the memory chip. Once the
software is transferred to the memory chip, the software will continue to run for a long time and you
don’t need to reload new software.
Figure 3 - Layered Architecture of an Embedded System
Now, let us see the details of the various building block of the hardware of an embedded system. As
shown in Figure 4, the building blocks are:
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TE-IT: MEP Module 1 - Introduction to Embedded Systems
• Central Processing Unit (CPU)
• Memory (Read-only Memory and Random-Access Memory)
• Input Devices
• Output devises
• Communication interfaces
• Application-specific circuitry
Figure 4 – Simplified Hardware Architecture of an Embedded System
Central Processing Unit (CPU): The Central Processing Unit (processor, in short) can be any of the
following: micro-controller, microprocessor or Digital Signal Processor (DSP). A micro-controller is a
low -cost processor. Its main attraction is that on the chip itself, there will be many other components
such as memory, serial communication interface, analog-to-digital converter etc. So, for small
applications, a micro-controller is the best choice as the number of external components required will
be very less. On the other hand, microprocessors are more powerful, but you need to use may external
components with them. DSP is used mainly for applications in which signal processing is involved such
as audio and video processing.
Memory: The memory is categorized as Random-Access Memory (RAM) and Read Only Memory
(ROM). The contents of the RAM will be erased if power is switched off to the chip, whereas ROM
retains the contents even if the power is switched off. So, the firmware is stored in ROM. When power
is switched on, the processor reads the ROM, the program is transferred to RAM and the program is
executed.
Input devices: Unlike the desktops, the input devices to an embedded system have very limited
capability. There will be no keyboard or a mouse, and hence interacting with the embedded system is
no easy task. Many embedded systems will have a small keypad-you press one key to give a specific
command. A keypad may be used to input only the digits. Many embedded systems used in process
control do not have any input device for used interaction; they take inputs from sensors of transducers
and produce electrical signals that are in turn fed to other systems.
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TE-IT: MEP Module 1 - Introduction to Embedded Systems
Output devices: The output devices of the embedded systems also have very limited capability. Some
embedded systems will have a few Light Emitting Diodes (LEDs) to indicate the health status of the
system modules, or for visual indication of alarms. A small Liquid Crystal Display may also be used to
display some important parameters.
Communication interfaces: The embedded systems may need to interact with other embedded
systems or they may have to transmit data to a desktop. To facilitate this, the embedded system is
provided with one or a few communication interfaces such as RS232, RS422, RS485, Universal serial
Bus (USB), IEEE 1394, Ethernet etc.
Application-specific circuitry: Sensors, transducers, special processing and control circuitry may be
required for an embedded system, depending on its application. This circuitry interacts with the
processor to carry out the necessary work.
The entire hardware must be given power supply either through the 230 volts main supply or through
a batter. The hardware must be designed in such a way that the power consumption is minimized.
IN Brief
The building blocks of an embedded system’s hardware are Central Processing Unit, memory,
input/output devices, communication interfaces and application-specific circuitry.
1.2 Application areas of Embedded Systems
Nearly 99 % of the processor manufactured end up in embedded systems. The embedded system
market is one of the highest growth areas as these systems are used in very market segment-
consumer electronics, office automation, industrial automation, biomedical engineering, wireless
communication, data communication, telecommunications, transportation, military and so on.
Consumer appliances: At home we use several embedded systems which include digital cameras,
digital diary, DVD player, electronic toys, microwave oven, remote controls for TV and air-conditioner,
VCD player, video game consoles, video recorders etc. Today’s high-tech car has about 20 embedded
systems for transmission control, engine spark control, air-conditioning, navigation etc. Even
wristwatches are now becoming embedded systems. The palmtops are powerful embedded systems
using which we can carry out many general-purpose tasks such as playing games and word processing.
Office automation: The office automation products using embedded systems are copying machine,
fax machine, key telephone, modern, printer, scanner etc.
Industrial automation: Today a lot of industries use embedded system for process control. These
include pharmaceutical, cement, sugar, oil exploration, nuclear energy, electricity generation and
transmission. The embedded systems for industrial use are designed to carry out specific tasks such
as monitoring the temperature, pressure, humidity, voltage, current etc., and then take appropriate
action based on the monitored levels to control other devices or to send information to a centralized
monitoring station. In hazardous industrial environment, where human presence must be avoided,
robots are used, which are programmed to do specific jobs. The robots are now becoming very
powerful and carry out many interesting and complicated tasks such as hardware assembly.’
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Medical electronics: Almost every medical equipment in the hospital is an embedded system. These
include diagnostic aids such as ECG, EEG, blood pressure measuring devices, X-ray scanners;
equipment used in blood analysis, radiation, colonoscopy, endoscopy, etc. Developments in medical
have paved way for more accurate diagnosis of diseases.
Computer networking: computer networking products such as bridges routers, integrated, services
digital networks (ISDN), Asynchronous Transfer Mode (ATM), X.25 and frame relay switches are
embedded system which implement the necessary data communication protocols. For example, a
router interconnects two networks. The two networks may be running different protocol. Most
networking equipment’s, other than the end-system (desktop computers) we use to access the
networks, are embedded systems.
Telecommunication: Computer networking products such as bridges, routers, integrated services
Digital Networks (ISDN), Asynchronous transfer Mode (ATM), X 25 and frame relay switches are
embedded system which implement the necessary data communication protocols. The router’s
function is to obtain the data packets from incoming ports, analyse the packets and send them
towards the destination after doing necessary protocol conversion. Most networking equipment,
other than the end-system (desktop computers) we use to access the networks, are embedded
systems.
Wireless technologies: Advances in mobile communication are paving way for many interesting
applications using embedded systems. The mobile phone is one of the marvels of the last decade of
the 20Th century. It is a very powerful embedded system that provides voice communication while we
are on the move. The personal digital assistants and the palmtops can now be used to access
multimedia services over the internet. Mobile communication infrastructure such as base station
controllers, mobile switching centres are also powerful embedded systems.
Instrumentation: Testing and measurements are the fundamental requirements in all scientific and
engineering activities. The measuring equipment we use in laboratories to measure parameters such
as weight, temperature, pressure, humidity, voltage, current etc, are all embedded system. Test
equipment such as oscilloscope, spectrum analyser, logic analyser, protocol analyser, radio
communication set etc. are embedded systems built around powerful processors. Thanks to
miniaturization. The test and measuring equipment are now becoming portable facilitating easy
testing and measurement in the field by field-personnel.
Security: Security of persons and information has always been a major issue. We need to protect our
homes and offices; and, the information we transmit and store. Developing embedded systems for
security applications is one of the most lucrative businesses nowadays. Security devise at homes,
offices, airports etc. for authentication and verification are embedded systems. Encryption devices are
used to encrypt the data/voice being transmitted on communication links such as telephone lines.
Biometric systems using fingerprint and face precognition are now being extensively used for user
authentication in banking application as well as for access control in high security buildings.
Finance: Financial dealing through cash and cheques are now slowly paying way for transactions using
smart card and ATM machine. Smart card, of the size of a credit card, has a small micro-controller and
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memory; and it interacts with the smart card reader/ATM machine and acts as an electronic wallet.
Smart card technology has the capability of ushering in a cashless society.
In brief
Nearly 99% of processors the are manufactured end up in embedded systems. Embedded systems
find applications in every industrial segment-consumer electronics, biomedical engineering,
manufacturing, process control and industrial automation, data communication, telecommunication,
defence, security etc.
1.3 Categories of Embedded Systems
Based on functionality and performance requirements, embedded systems can be categorized as:
• Stand-alone embedded systems
• Real-time systems
• Networked information appliances
• Mobile devise
In brief
Embedded systems can be categorized as stand - alone systems real – time systems networked
information appliances, and mobile devices.
1.3.1 Stand-alone embedded systems
As the name implies, stand-alone systems work in stand-alone mode. They take inputs, process them
and produce the desire output. The input can be electrical signals from transducers of commands from
a human being such as the pressing of a bottom. The output can be electrical signals to drive another
system, an LED display or LCD display for displaying of information to the users. Embedded systems
used in process control, automobiles, consumer electronic items etc. Fall into this category. In a
process control system, the inputs are from sensors that convert a physical entity such as temperature
of pressure into its equivalent electrical signal. These electrical signals are processed by the system
and appropriate electrical signals are produced using which an action is taken such as opening a valve.
A few embedded systems used at home are shown in Figure 5.
Figure 5 - Stand-alone Embedded Systems used at Home [21]
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TE-IT: MEP Module 1 - Introduction to Embedded Systems
1.3.2 Real-time systems
Embedded systems in which some specific work must be done in a specific time-period are called real-
time systems. For example, consider a system that must open a valve within 30 milliseconds when the
humidity crosses a particular threshold. If the valve is not opened within 30 milliseconds, a catastrophe
may occur, such systems with strict deadlines are called hard real-time systems. In some embedded
system, deadline is imposed, but not adhering to them once in a while may not lead to a catastrophe.
For example, consider a DVD player. Suppose, you give a command to the DVD player from a remote
control, and there is a delay of a few milliseconds in executing that command. But this delay won’t
lead to a serious implication. Such systems are called soft real-time systems.
Figure 6 - Hard Real Time Embedded System
Figure 6 shown a missile that must track and intercept an enemy aircraft. The missile contains an
embedded system that tracks the aircraft and generates a control signal that will launch the missile. If
there is a delay in tracking the aircraft and if the missile misses the deadline, the enemy aircraft may
drop a bomb and cause loss of many lives. Hence, this system is a hard-real-time embedded system.
In Brief
Real-time embedded systems must complete a specific task in a specified time period. Meeting the
deadlines is the most important requirement of real-time systems.
Notes
Real time system is categorized as hard real-time systems and soft real-time systems. In hard real-time
system, missing a deadline may lead to a catastrophe. In soft real-time systems, meeting the deadline
is important but missing the deadline will not lead to a catastrophe.
1.3.3 Networked information appliances
Embedded system that are provided with network interfaces and accessed by networks such as Local
Area Network or the Internet are called networked information appliances. Such embedded systems
are connected to a network, typically a network running TCP/IP (Transmission Control Protocol/
Internet Protocol) protocol suite, such as the Internet or a company’s Intranet. These systems have
emerged in recent years. These systems run the protocol TCP/IP stack and get connected either
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through PPP or Ethernet to a network and communicate with other nodes in the network. Here are
some examples of such systems.
• A networked process control system consists of several embedded systems connected as a
Local Area Network. Each embedded system can send real-time date to a central location form
where the entire process control system can be monitored. The monitoring can be done using
a web browser such as the Internet Explore.
• A web camera can be connected to the Internet. The web camera can send pictures in real-
time to any computer connected to the Internet. In such a case, the web camera must run the
HTTP server software in addition to the TCP/IP protocol stack.
• The door-lock of your home can be a small embedded system with TCP/IP and HTTP server
software running on it. When your children stand in front of the door-lock after they return
from school, the web camera in the door-lock will send an alert to your desktop over the
Internet and then you can open the door-lock through a click of the mouse.
Figure 7 - Network Information Appliance
Figure 7 shows a weather monitoring system connected to the Internet. TCP/IP protocol suite and
HTTP web server software will be running on this system. Any computer connected to the Internet
can access this system to obtain real-time weather information. The networked information
appliances need to run the complete TCP/IP protocol stack including the application layer protocols.
If the appliance must provide information over the Internet, HTTP web server software also needs to
run on the system.
1.3.4 Mobile devices
Mobile devices such as mobile phones, Personal Digital Assistants (PDAs), smart phone etc. are a
special category of embedded systems. Though the PDAs do many general-purpose tasks, they need
to be designed just like the ‘conventional’ embedded systems. The limitations of the mobile devices –
memory constraints, small size, lack of good user interfaces such as full-fledged keyboard and display
etc, - are same as those found in embedded systems discussed above. Hence, mobile devices are
considered as embedded systems. However, the PDAs are now capable of supporting general-purpose
application software such as word processors, games, etc.
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1.4 Specialties of Embedded Systems
As compared to desktop computers, workstations or mainframes, embedded systems have many
specialities. Developers need to keep these specialities in mind while designing embedded systems.
1.4.1 Reliability
When we use a desktop, sometimes the system ‘hangs’ and we need to reset the computer. Generally,
this does not cause any problem. However, this is not the case with the embedded systems used in
mission-critical applications. They must work with high reliability.
Reliability is of paramount importance in embedded systems. They should continue to work for
thousands of hours without break. Many embedded systems used in industrial control are
inaccessible. They are hidden in some other large-sized equipment; hence there will not be a reset
bottom on such systems! So, the design of the embedded system should be such that in case the
system has to be reset, the reset should be done automatically. Special hardware/software needs to
be built into the system to take care of it. This special module is known as watchdog timer.
Many embedded systems used in industrial automation and defence equipment need to work in
extreme environmental condition such as very high/low temperatures, high humidity. Besides, they
should be able to withstand bump and vibrations. Hence, very stringer environment specifications
must be met by such systems. The ability to work reliably in extreme environmental conditions is
known as ruggedness. Not only the military equipment, even the consumer appliances such as the
mobile phone need to be very rugged. Many people keep dropping their mobile phone on the floor,
but still it works because it is very rugged.
1.4.2 Performance
May embedded systems have time constraints. For instance, in a process control system, a constraint
can be: “if the temperature exceeds 40 degrees, open a valve within 10 milliseconds.” The system
must meet such deadlines. If the deadlines are missed, it may result in a catastrophe. You can imagine
the damage that can be done if such deadlines are not met in a safety system of a nuclear plant.
1.4.3 Power Consumption
Most of the embedded systems operate through a battery. To reduce the battery, drain and avoid
frequent recharging of the battery, the power consumption of the embedded systems must be very
low. To reduce power consumption such hardware components should be used that consume less
power. Besides, emphasis should be on reducing the components count of the hardware. To reduce
component count, the hardware designers have the option of using Programmable Logic Devices
(PLDs) and Field Programmable Gate Array (FPGAs). Reducing the components count apart from
reducing the power consumption also increases the reliability of the system.
1.4.4 Cost
For embedded systems used in safety applications of a nuclear plant or in a spacecraft, cost may not
be a very important factor. However, for embedded system used in consumer electronics or office
automation, the cost is of almost importance. Suppose you designed a toy in which the electronics will
cost US$20. By a careful analysis of the design, if you can find a way to reduce to cost to US$19, it will
be a great job. Don’t underplay the importance of that one dollar because when you sell 10 million
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toys, the cost reduction is $10 million! Not surprisingly, the hardware engineers debate on component
selection to reduce even $0.1.
1.4.5 Size
Size is certainly a factor for many embedded systems. We do not like a mobile phone that has to be
carried on our backs. The size and the weight are important parameters in embedded systems used in
aircraft, spacecraft, missiles etc. because in such cases, every inch and every gram matter. To reduce
the size and the weight, again the hardware engineers must design their boards by reducing the
component count to the maximum possible extent. During the initial development of mobile phone
base on GSM (Global System for Mobile Communication), GSM was expanded as “God, Send Mobiles”
because of the complexity of the mobile phone. Today, the mobile phone goes into our pockets,
thanks to developments in microelectronics.
1.4.6 Limited User Interface
Unlike desktops, which have full-fledged input/output devices, embedded systems do not have
sophisticated interfaces for input and output. Some embedded systems do not have and user interface
at all. They take electrical signals as input and produce electrical signals as output. In many embedded
systems, the input is through a small function keypad or a set of buttons. The output is displayed either
on a set of LEDs or a small LCD. For example, the mobile phone has a small display of 4 lines x 16
characters. The input is through a keypad and composing a small text message is not an easy task.
Developing a user-friendly interface with limitation of the input/put devices is a challenging tasked for
firmware developers.
1.4.7 Software Upgradation Capability
Embedded systems are meant for a very specific task. So, once the software is transferred to the
embedded system, the same software will run through its life. However, in some cases, it may be
necessary to upgrade the software. Consider the example of a Public Call Office (PCO). At the PCO, an
embedded system is used which displays the amount to be paid by a telephone user. The amount is
calculated by the firmware, based on the calling number and the duration of the call. From time to
time, the telecom operator will change the algorithm for the calculation of the bill amount. So, every
time there is a tariff change, the PCO operator must replace the program stored in the memory of the
embedded system with new program. This is very cumbersome, considering that a memory chip will
have to be replaced in thousands of PCOs. Nowadays, software upgradation is done by downloading
the software onto the embedded system through a network connection. In future, such an
upgradation may become. mandatory for many embedded systems.
In Brief
While designing embedded systems, the following aspects need to be considered by the developers:
reliability, performances, power consumption, cost, size, limited user interface and software
upgradation capability.
Notes
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TE-IT: MEP Module 1 - Introduction to Embedded Systems
By using PLDs and FPGAs, the number of components in an embedded system can be reduced.
Reducing the components count increases the system’s reliability and reduces the power
consumption.
1.5 Recent trends in Embedded Systems.
In good old days, developing embedded systems was confined to a very few ‘specialists. Most of the
embedded software was written only in assembly language and hence writing, debugging and
maintaining the code were very difficult and time consuming. With the availability of powerful
processors and advanced development tools, embedded software development is no longer ‘rocket
science’. In this section, we will review the advances in embedded systems.
1.5.1 Processor Power
The growing importance of embedded system can be gauged by the availability of processors. About
150 varieties of processors are available from around 50 semiconductor vendors. Powerful 8-bit, 16-
bit, 32- bit, 64-bit micro-controllers, and microprocessors are available to cater to the different market
segments. The clock speed and the memory addressing capability of these processors are also
increasing. Very powerful Digital Signal Processors are also available for real-time analysis of audio
and video signals. As a result, the power of desktop computers is now available on palmtops.
1.5.2 Memory
The cost of memory chip is reducing day by day. As a result, the embedded systems can be made
functionally rich by incorporating additional features such as networking protocols and even graphical
user incorporating interfaces. The cost of memory chips used to discourage developers from porting
an operating system onto the target hardware. As the memory chips are becoming cheaper, porting
and operating system is no longer an issue. Now, wristwatches with embedded Linux operating system
are available.
1.5.3 Operating Systems
Unlike the desktops on which the options for an operating system are limited (predominantly,
Windows), a variety of operating systems are available which can be ported onto the embedded
system. The main advantage of embedding an operating system is that the software development will
be very fast and maintaining the code is very easy. The software can be developed in a high-level
language such as C. So, time to market the system gets reduced. If real-time performance is required,
a real-time operating system can be used. In addition to many commercial embedded/real-time
operating systems, open source software campaign let to development of many open source
operating systems. The attraction of open source software is that it is free and also the complete
source code is available to customize the software as per your application needs.
1.5.4 Communication Interface and Network Capability
With the availability of low-cost chips, embedded systems can be provided networking capability
through communication interfaces such as Ethernet, 802.11 wireless LAN, and Infrared. Network-
enabling of an embedded system has many advantages: it can be accessed over a network for remote
control or monitoring. Besides, upgrading the embedded software is very easy as new version can be
uploaded through the network interface. Due to the enhanced memory capacities of the embedded
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systems, TCP/IP protocol stack and the HTTP server software can also be ported onto the system and
such system can be accessed over the internet from anywhere on the earth.
1.5.5 Programming Languages
Development of embedded software was done mostly in assembly languages. However, due to the
availability of cross-compliers, most of the development is now done in high level languages such as
C. The object-oriented language, like c++ and java, are now catching up. The main attraction of Java is
its platform independence. In fact, the development of Java programming language was initiated
mainly to address the embedded system market. Many exciting applications are possible by having a
Java Virtual Machine in an embedded system. It enables the system download Java applets from a
server execute them. Microsoft’s embedded visual tools can be used for development of embedded
software applications. People with experience in Microsoft visual studio can become embedded
software developers with very little training.
1.5.6 Development Tools
Availability of several tools for development, debugging and testing as well as for modelling the
embedded system is now paving way for fast development of robust and reliable systems.
Development tools such as MATLAB and Simulink can be used to model and embedded system as well
as to generate code, substantially reducing the development time. Development tool such as BREW
(Binary Runtime Environment for Wireless), Java 2 Micro Edition (J2ME) development tools, Wireless
Application Protocol (WAP) development tools facilitate easy development of applications for mobile
devices. The Protocol (WAP) development tools facilitate easy development of application of mobile
device. The entire application can be developed and tested on desktop computers, and then deployed
in the field.
1.5.7 Programming Hardware
Programmable logic devices (PLDs) and field programmable gate arrays (FPGAs) pave the way for
reducing the components on an embedded system, leading to small, low-cost systems. After
developing the prototype of an embedded system, for mass production, a FPGA can be developed
which will have all the functionality of the processor, peripherals as well as the application-specific
circuitry. “System-on-Chip” is the catchword that reflects the current developments in programmable
hardware-single chip is the embedded system!
In Brief
Advances in processor power, memory devices, operating systems, networking interfaces,
programming languages, development tools and programmable hardware are paving way for very
powerful embedded system and faster and easier development as compared to olden days.
1.6 Brief Introduction to Embedded microcontroller cores CISC, RISC,
ARM, DSP and SoC.
1.6.1 CISC vs RISC
The simplest way to examine the advantages and disadvantages of RISC architecture is by contrasting
it with its predecessor: CISC (Complex Instruction Set Computers) architecture.
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Multiplying Two Numbers in Memory
On the right is a diagram representing the storage
scheme for a generic computer. The main memory is
divided into locations numbered from (row) 1:
(column) 1 to (row) 6: (column) 4. The execution unit
is responsible for carrying out all computations.
However, the execution unit can only operate on data
that has been loaded into one of the six registers (A,
B, C, D, E, or F). Let's say we want to find the product
of two numbers - one stored in location 2:3 and
another stored in location 5:2 - and then store the
product back in the location 2:3.
The CISC Approach
The primary goal of CISC architecture is to complete a
task in as few lines of assembly as possible. This is
achieved by building processor hardware that can
understand and executing a series of operations. For
this task, a CISC processor would come prepared with
a specific instruction (we'll call it "MULT"). When executed, this instruction loads the two values into
separate registers, multiplies the operands in the execution unit, and then stores the product in the
appropriate register. Thus, the entire task of multiplying two numbers can be completed with one
instruction:
MULT 2:3, 5:2
MULT is what is known as a "complex instruction." It operates directly on the computer's memory
banks and does not require the programmer to explicitly call any loading or storing functions. It closely
resembles a command in a higher-level language. For instance, if we let "a" represent the value of 2:3
and "b" represent the value of 5:2, then this command is identical to the C statement "a = a * b."
One of the primary advantages of this system is that the compiler must do very little work to translate
a high-level language statement into assembly. Because the length of the code is relatively short, very
little RAM is required to store instructions. The emphasis is put on building complex instructions
directly into the hardware.
The RISC Approach
RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the
"MULT" command described above could be divided into three separate commands: "LOAD," which
moves data from the memory bank to a register, "PROD," which finds the product of two operands
located within the registers, and "STORE," which moves data from a register to the memory banks. To
perform the exact series of steps described in the CISC approach, a programmer would need to code
four lines of assembly:
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LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
At first, this may seem like a much less efficient way of completing the operation. Because there are
more lines of code, more RAM is needed to store the assembly level instructions. The compiler must
also perform more work to convert a high-level language statement into code of this form.
CISC RISC However, the RISC strategy also brings
Emphasis on hardware Emphasis on software some very important advantages. Because
each instruction requires only one clock
Includes multi-clock Single-clock, cycle to execute, the entire program will
execute in approximately the same
complex instructions reduced instruction only amount of time as the multi-cycle "MULT"
Memory-to-memory: Register to register: command. These RISC "reduced
"LOAD" and "STORE" "LOAD" and "STORE" instructions" require less transistors of
incorporated in instructions are independent instructions hardware space than the complex
code instructions, leaving more room for
Small sizes, Low cycles per second, general purpose registers. Because all the
high cycles per second large code sizes instructions execute in a uniform amount
Transistors used for storing Spends more transistors of time (i.e. one clock), pipelining is
possible.
complex instructions on memory registers
Separating the "LOAD" and "STORE"
instructions reduces the amount of work
that the computer must perform. After a CISC-style "MULT" command is executed, the processor
automatically erases the registers. If one of the operands needs to be used for another computation,
the processor must re-load the data from the memory bank into a register. In RISC, the operand will
remain in the register until another value is loaded in its place.
The Performance Equation
The following equation is commonly used for expressing a computer's performance ability:
The CISC approach attempts to minimize the number of instructions per program, sacrificing the
number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the
cost of the number of instructions per program.
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- RISC CISC
1 RISC stands for Reduced Instruction Set CISC stands for Complex Instruction Set
Computer Computer
2 RISC processors have simple instructions CISC processors have complex instructions that
taking about one clock cycle. The average take up multiple clock cycles for execution. The
Clock cycles Per Instruction (CPI) of a RISC average Clock cycles Per Instruction of a CISC
processor is 1.5 processor is between 2 and 15
3 There are hardly any instructions that refer Most of the instructions refer memory
memory.
4 RISC processors have a fixed instruction CISC processors have variable instruction
format format.
5 The instruction set is reduced i.e. it has only The instruction set has a variety of different
few instructions in the instruction set. Many instructions that can be used for complex
of these instructions are very primitive. operations.
6 RISC has fewer addressing modes and most CISC has many different addressing modes and
of the instructions in the instruction set have can thus be used to represent higher level
register to register addressing mode. programming language statements more
efficiently.
7 Complex addressing modes are synthesized CISC already supports complex addressing
using software. modes
8 Multiple register sets are present Only has a single register set
9 RISC processors are highly pipelined They are normally not pipelined or less
pipelined
10 The complexity of RISC lies in the compiler The complexity lies in the micro program
that executes the program.
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- RISC CISC
11 The most common RISC microprocessors are Examples of CISC processors are the
Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, System/360, VAX, PDP-11, Motorola 68000
Power Architecture, and SPARC. family, AMD and Intel x86 CPUs.
1.6.2 ARM
Advanced RISC Machines would be covered in depth in module IV.
1.6.3 DSP
One of the biggest bottlenecks in executing DSP algorithms is transferring information to and from
memory. This includes data, such as samples from the input signal and the filter coefficients, as well
as program instructions, the binary codes that go into the program sequencer. For example, suppose
we need to multiply two numbers that reside somewhere in memory. To do this, we must fetch three
binary values from memory, the numbers to be multiplied, plus the program instruction describing
what to do.
Figure 28-4a shows how this seemingly simple task is done in a traditional microprocessor. This is often
called a Von Neumann architecture, after the brilliant American mathematician John Von Neumann
(1903-1957). Von Neumann guided the mathematics of many important discoveries of the early
twentieth century. His many achievements include: developing the concept of a stored program
computer, formalizing the mathematics of quantum mechanics, and work on the atomic bomb. If it
was new and exciting, Von Neumann was there!
As shown in (a), a Von Neumann architecture contains a single memory and a single bus for
transferring data into and out of the central processing unit (CPU). Multiplying two numbers requires
at least three clock cycles, one to transfer each of the three numbers over the bus from the memory
to the CPU. We don't count the time to transfer the result back to memory, because we assume that
it remains in the CPU for additional manipulation (such as the sum of products in a FIR filter). The Von
Neumann design is quite satisfactory when you are content to execute all the required tasks in serial.
In fact, most computers today are of the Von Neumann design. We only need other architectures
when very fast processing is required, and we are willing to pay the price of increased complexity.
This leads us to the Harvard architecture, shown in (b). This is named for the work done at Harvard
University in the 1940s under the leadership of Howard Aiken (1900-1973). As shown in this
illustration, Aiken insisted on separate memories for data and program instructions, with separate
buses for each. Since the buses operate independently, program instructions and data can be fetched
at the same time, improving the speed over the single bus design. Most present-day DSPs use this dual
bus architecture.
Figure (c) illustrates the next level of sophistication, the Super Harvard Architecture. This term was
coined by Analog Devices to describe the internal operation of their ADSP-2106x and new ADSP-211xx
families of Digital Signal Processors. These are called SHARC® DSPs, a contraction of the longer
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term, Super Harvard Architecture. The idea is to build upon the Harvard architecture by adding
features to improve the throughput. While the SHARC DSPs are optimized in dozens of ways, two areas
are important enough to be included in Fig. 28-4c: an instruction cache, and an I/O controller.
First, let's look at how the instruction cache improves the performance of the Harvard architecture. A
handicap of the basic Harvard design is that the data memory bus is busier than the program memory
bus. When two numbers are multiplied, two binary values (the numbers) must be passed over the
data memory bus, while only one binary value (the program instruction) is passed over the program
memory bus. To improve upon this situation, we start by relocating part of the "data" to program
memory. For instance, we might place the filter coefficients in program memory, while keeping the
input signal in data memory. (This relocated data is called "secondary data" in the illustration). At first
glance, this doesn't seem to help the situation; now we must transfer one value over the data memory
bus (the input signal sample), but two values over the program memory bus (the program instruction
and the coefficient). In fact, if we were executing random instructions, this situation would be no
better at all.
However, DSP algorithms generally spend most of their execution time in loops, such as instructions
6-12 of Table 28-1. This means that the same set of program instructions will continually pass from
program memory to the CPU. The Super Harvard architecture takes advantage of this situation by
including an instruction cache in the CPU. This is a small memory that contains about 32 of the most
recent program instructions. The first time through a loop, the program instructions must be passed
over the program memory bus. This results in slower operation because of the conflict with the
coefficients that must also be fetched along this path. However, on additional executions of the loop,
the program instructions can be pulled from the instruction cache. This means that all the memory to
CPU information transfers can be accomplished in a single cycle: the sample from the input signal
comes over the data memory bus, the coefficient comes over the program memory bus, and the
program instruction comes from the instruction cache. In the jargon of the field, this efficient transfer
of data is called a high memory-access bandwidth.
Figure 28-5 presents a more detailed view of the SHARC architecture, showing the I/O
controller connected to data memory. This is how the signals enter and exit the system. For instance,
the SHARC DSPs provides both serial and parallel communications ports. These are extremely high-
speed connections. For example, at a 40 MHz clock speed, there are two serial ports that operate at
40 Mbits/second each, while six parallel ports each provide a 40 Mbytes/second data transfer. When
all six parallel ports are used together, the data transfer rate is an incredible 240 Mbytes/second.
This is fast enough to transfer the entire text of this book in only 2 milliseconds! Just as important,
dedicated hardware allows these data streams to be transferred directly into memory (Direct Memory
Access, or DMA), without having to pass through the CPU's registers. In other words, tasks 1 & 14 on
our list happen independently and simultaneously with the other tasks; no cycles are stolen from the
CPU. The main buses (program memory bus and data memory bus) are also accessible from outside
the chip, providing an additional interface to off-chip memory and peripherals. This allows the SHARC
DSPs to use a four Gigaword (16 Gbyte) memory, accessible at 40 Mwords/second (160
Mbytes/second), for 32-bit data. Wow!
Asst. Prof. Selvin Furtado [32]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 1 - Introduction to Embedded Systems
This type of high speed I/O is a key characteristic of DSPs. The overriding goal is to move the data in,
perform the math, and move the data out before the next sample is available. Everything else is
secondary. Some DSPs have on-board analog-to-digital and digital-to-analog converters, a feature
called mixed signal. However, all DSPs can interface with external converters through serial or parallel
ports.
Now let's look inside the CPU. At the top of the diagram are two blocks labelled Data Address
Generator (DAG), one for each of the two memories. These controls the addresses sent to the
program and data memories, specifying where the information is to be read from or written to. In
simpler microprocessors this task is handled as an inherent part of the program sequencer and is quite
transparent to the programmer. However, DSPs are designed to operate with circular buffers, and
benefit from the extra hardware to manage them efficiently. This avoids needing to use precious CPU
clock cycles to keep track of how the data are stored. For instance, in the SHARC DSPs, each of the two
DAGs can control eight circular buffers. This means that each DAG holds 32 variables (4 per buffer),
plus the required logic.
Why so many circular buffers? Some DSP algorithms are best carried out in stages. For instance, IIR
filters are more stable if implemented as a cascade of liquids (a stage containing two poles and up to
two zeros). Multiple stages require multiple circular buffers for the fastest operation. The DAGs in the
SHARC DSPs are also designed to efficiently carry out the Fast Fourier transform. In this mode, the
DAGs are configured to generate bit-reversed addresses into the circular buffers, a necessary part of
the FFT algorithm. In addition, an abundance of circular buffers greatly simplifies DSP code generation-
both for the human programmer as well as high-level language compilers, such as C.
The data register section of the CPU is used in the same way as in traditional microprocessors. In the
ADSP-2106x SHARC DSPs, there are 16 general purpose registers of 40 bits each. These can hold
intermediate calculations, prepare data for the math processor, serve as a buffer for data transfer,
hold flags for program control, and so on. If needed, these registers can also be used to control loops
and counters; however, the SHARC DSPs have extra hardware registers to carry out many of these
functions.
Asst. Prof. Selvin Furtado [33]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 1 - Introduction to Embedded Systems
The math processing is broken into three sections, a multiplier, an arithmetic logic unit (ALU), and
a barrel shifter. The multiplier takes the values from two registers, multiplies them, and places the
result into another register. The ALU performs addition, subtraction, absolute value, logical operations
(AND, OR, XOR, NOT), conversion between fixed and floating-point formats, and similar functions.
Elementary binary operations are carried out by the barrel shifter, such as shifting, rotating, extracting
and depositing segments, and so on. A powerful feature of the SHARC family is that the multiplier and
the ALU can be accessed in parallel. In a single clock cycle, data from registers 0-7 can be passed to
the multiplier, data from registers 8-15 can be passed to the ALU, and the two results returned to any
of the 16 registers.
There are also many important features of the SHARC family architecture that aren't shown in this
simplified illustration. For instance, an 80-bit accumulator is built into the multiplier to reduce the
round-off error associated with multiple fixed-point math operations. Another interesting
Asst. Prof. Selvin Furtado [34]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 1 - Introduction to Embedded Systems
feature is the use of shadow registers for all the CPU's key registers. These are duplicate registers that
can be switched with their counterparts in a single clock cycle. They are used for fast context switching,
the ability to handle interrupts quickly. When an interrupt occurs in traditional microprocessors, all
the internal data must be saved before the interrupt can be handled. This usually involves pushing all
the occupied registers onto the stack, one at a time. In comparison, an interrupt in the SHARC family
is handled by moving the internal data into the shadow registers in a single clock cycle. When the
interrupt routine is completed, the registers are just as quickly restored.
1.6.4 SoC
A system-on-a-chip (SoC) is a microchip with all the necessary electronic circuits and parts for a given
system, such as a smartphone or wearable computer, on a single integrated circuit (IC).
An SoC for a sound-detecting device, for example, might include an audio receiver, an analog-to-digital
converter (ADC), a microprocessor, memory, and the input/output logic control for a user - all on a
single chip.
System-on-a-chip technology is used in small, increasingly complex consumer electronic devices. Some
such devices have more processing power and memory than a typical 10-year-old desktop computer.
Asst. Prof. Selvin Furtado [35]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 1 - Introduction to Embedded Systems
In the future, SoC-equipped nanorobots (robots of microscopic dimensions) might act as
programmable antibodies to fend off previously incurable diseases. SoC video devices might be
embedded in the brains of blind people, allowing them to see and SoC audio devices might allow deaf
people to hear. Handheld computers with small whip antennas might someday be capable of browsing
the Internet at megabit-per-second speeds from any point on the surface of the earth.
1.7 Design Challenge — Optimizing Design Metrics
The embedded-system designer must of course construct an implementation that full fills
desired functionality, but a difficult challenge is to construct an implementation that
simultaneously optimizes numerous design metrics.
1.7.1 Common Design Metrics
For our purposes, an implementation consists either of a microprocessor with an accompanying
program, a connection of digital gates, or some combination thereof. A design metric IS a
measurable feature of a system’s implementation. Commonly used metrics include:
1. NRE cast (nonrecurring engineering cost): The one-time monetary cost of designing the
system. Once the system is designed, any number of units can be manufactured without
incurring any additional design cost; hence the term nonrecurring.
2. Unit cost: The monetary cost of manufacturing each copy of the system, excluding NRE
cost.
3. Size: The physical space required by the system, often measured in bytes for software,
and gates or transistors for hardware.
4. Performance: The execution time of the system.
5. Power: The amount of power consumed by the system, which may determine the
lifetime of a battery, or the cooling requirements of the IC, since more power means
more heat.
6. Flexibility: The ability to change the functionality of the system without incurring
heavy NRE cost. Software is typically considered very flexible.
7. Time-to-prototype: The time needed to build a working version of the system, which
may be bigger or more expensive than the final system implementation, but it can be
used to verify the system’s usefulness and correctness and to refine the system’s
functionality.
8. Time-to-market: The time required to develop a system to the point that it can be
released and sold to customers. The main contributors are design time, manufacturing
time, and testing time.
9. Maintainability: The ability to modify the system after its initial release, especially by
designers who did not originally design the system.
10. Correctness: Our confidence that we have implemented the system’s functionality
correctly. We can check the functionality throughout the process of designing the
system, and we can insert test circuitry to check that manufacturing was correct.
11. Safety: The probability that the system will not cause harm.
Asst. Prof. Selvin Furtado [36]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 1 - Introduction to Embedded Systems
Metrics typically compete with one another: Improving one often leads to worsening of
another. For example, if we reduce an implementation’s size, the implementation's
performance may suffer. Some observers have compared this phenomenon to a wheel with
numerous pins, as illustrated in Figure 1. If you push one pin in, such as size, then the other
pins pop out. To best meet this optimization challenge, the designer must be comfortable with
a variety of hardware and software implementation technologies. and must be able to migrate
from one technology to another, in order to find the best implementation for a given application
and constraints. Thus, a designer cannot simply be a hardware expert or a software export, as
is commonly the case today; the designer must have expertise in both areas.
Figure 8: Design metric competition - improving one may
worsen other.
Asst. Prof. Selvin Furtado [37]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
2 Module 2 - The Microcontroller Architecture and Programming of 8051
2.1 Introduction to 8051 Microcontroller
In 1981, Intel Corporation introduced an 8-bit microcontroller called 8051. This microcontroller had
128 bytes of RAM, 4K bytes of on-chip ROM, two timers, one serial port, and four ports (each 8-bits
wide) all on a single chip. At the time it was referred to as a “system on a chip”. The 8051 is an 8-bit
processor, meaning that the CPU can work on only 8-bits of data at a time. Data larger than 8 bits must
be broken down into 8-bit pieces to be processed by the CPU. The 8051 has a total of four I/O ports,
each 8 bits wide. See Figure 9.
The 8051 became widely popular after Intel allowed other manufacturers to make and market any
flavours of the 8051, they please, with condition that they remain code-compatible with the 8051.
This has led to many versions of the 8051 with different speeds and amounts of on-chip ROM
marketed by more than half a dozen manufacturers.
2.2 Architecture
Figure 9 - 8051 Microcontroller Block Diagram
2.2.1 ALU
Arithmetic and logic unit of 8051 performs arithmetic and logical operations on 8-bit operands.
Accumulator is the register, which gets the output of the ALU in most of the arithmetic and logical
operations with few exceptions. Apart from addition and subtraction operation, the 8051 hardware
Asst. Prof. Selvin Furtado [38]
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
also performs multiplication and division operations. Each of the logical operations involves digital
gates. AND, OR, NOT, Exclusive OR operations are possible.
2.2.2 Boolean Processor
There is a separate Boolean processor integrated within the 8051 microcontrollers. It has its own
instruction set, accumulator and bit addressable RAM. Carry flag serves as the accumulator. The
instructions allow bit manipulations like complement bit, set bit, clear bit. There are also conditional
branch instructions like jump if bit set, etc. Logical bitwise AND, OR operations are also supported. The
results of these bitwise logical operations are stored into the carry bit, which works as an accumulator.
2.3 Program and Data Memories
There are two separate program and data memories. The code is typically stored in ROM/EPROM. The
program storage is one of the factors that differentiate among the various members of the 8051
family. The program memory of 80C51 is 4K ROM.
Data memory can be internal RAM and off-chip external data RAM. Internal data RAM, for example,
in 80C51 is 128 bytes. Some of the internal on-chip RAM locations are also used for controlling the
operations of the peripherals such as timers/counters, serial ports, interrupts, etc. called as special
function registers (SRFs). The external off-chip memory space is accessible in most of the 8051
members. To access the off-chip data RAM, 16-bit address is used. The address (Port 0) and address –
data (Port 2) buses hold this address. The lower order byte of the address-data bus is time-
multiplexed. Multiplexing reduces the pin count, but it also reduces the speed of memory access. This
is the reason that the external data memory1 access is always slower as compared to accessing the
on-chip RAM. Further, to access the external memory, it is necessary to load the data pointer, which
requires one extra instruction.
2.3.1 Stack Pointer and Program Counter
2.3.1.1 Stack Pointer
Stack pointer of 8051 is 8-bit wide. It is incremented during push or call operations and is decremented
during pop or return operation. It may be initialized anywhere in the available on-chip data RAM. After
the RESET operation, the stack pointer is initialized to 07H, causing the stack to begin at 08H.
2.3.1.2 Program Counter (PC)
Instructions opcode bytes are fetched from the program memory locations addressed by the program
counter. The program counter in 8051 is 16-bit wide, and it can address 64K code bytes. PC always
points to the instruction to be fetched and is automatically incremented after fetching the instruction.
PC is affected by call and jump instructions. Note that only PC register has no (internal) on-chip RAM
address.
Asst. Prof. Selvin Furtado [39]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
Figure 10 - Four Register Banks and their Locations in the On-Chip RAM
Figure 11 - Stack Operation [40]
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Asst. Prof. Selvin Furtado
Dept. Electronic & Telecommunication Engg.
TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
Register symbol Register name Address
SP (8) Stack Pointer 81H
PC (16) Program Counter
NO ADDRESS
Table 1 - Stack Pointer and Program Counter
2.3.2 Special Function Registers (SFR)
The 128 bytes of on-chip additional RAM locations from 80H to 0FFH are reserved for the special
functions and therefore these are called as Special Function Registers (SFRs). These SFRs are used for
control or to show the status of various functions done by 8051 microcontrollers. All SFRs are directly
addressable and can be read or written to as well. Note that SFR space is only reserved for the special
functions and cannot be used for any other purpose. The available SFRs are listed in Table 2. Some
SFRs are bit addressable and allow their individual bits to be set or cleared by instructions. For
example, one can set (or clear) the Port 1-bit P1.1 using an instruction SETB P1.0 (or CLR P1.0). The
address of P1.1 bit is 91H. Port 1 has 90H as its byte address, and it is byte addressable too. To change
all the 8-bits of Port 1 in a single stroke, it is required to write (or move) a byte to address 90H.
However, there are some SFRs like timer mode control register (TMOD) which is accessible as a byte
only.
Asst. Prof. Selvin Furtado [41]
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
SFR symbol
Register name Address
ACC* Accumulator 0E0H
B* B-register 0F0H
P0* Port 0 80H
P1* Port 1 90H
P2* Port 2 0A0H
P3* Port 3 0B0H
IP* Interrupt Priority Control 0B8H
IE* Interrupt Enable Control 0A8H
TMOD Timer/Counter Mode Control 89H
TCON* Timer/Counter Control 88H
TH0 Timer/Counter 0 (high byte) 8CH
TL0 Timer/Counter 0 (low byte) 8AH
TH1 Timer/Counter 1 (high byte) 8DH
TL1 Timer/Counter 1 (low byte) 8BH
SCON* Serial Control 98H
SBUF Serial Data Buffer 99H
PCON Power Control 97H
PSW* Program Status Word 0D0H
DPTR Data Pointer
DPH Data Pointer (high byte) 83H
DPL Data Pointer (lower byte) 82H
Registers marked with * are bit as well as byte addressable
Table 2 – Special Function Registers
Asst. Prof. Selvin Furtado [42]
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
Program Status Word (PSW)
Program status word, or simply PSW, is an 8-bit register. Figure 12 shows the PSW register. It
consists of carry, auxiliary carry, overflow, and parity flags. There are bits RS1 and RS0 for register
bank selection. PSW is a bit addressable register. Each of the PSW bits is referred as PSW.X. Thus,
PSW.0 is the least significant bit (LSB), which is a parity flag, and the most significant bit (MSB) PSW.7
is the carry flag.
Figure 12 - Program Status Word
Carry Flag (PSW.7)
Carry flag is set when there is a cash out of 7th boy of result due to certain arithmetic and logical
operations. For example, 8-bit addition or substation affects carry flag. Let us add two numbers
11000010B (0C2H) and 10101010B (0AAH). The addition (6CH) with carry out of 7th bit. This will set
the carry flag.
Similarly, SETB C and CLR C instructions can also change carry bit.
Auxiliary Carry Flag (PSW.6)
Auxiliary Carry flag (AC) is set when there is a carry out of 3rd bit, during addition or subtraction
operation and otherwise cleared This is useful in BCD arithmetic. For example, addition of numbers
11001000B (0C0H) and 00001000B (08H) will set the AC flag, because there is a carry out of 3rd bit.
F0 (PSW.5) [43]
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Asst. Prof. Selvin Furtado
Dept. Electronic & Telecommunication Engg.
TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
F0 is available to user as a general-purpose flag. This flag can be set/cleared by software, or its status
can be observed by software. The user can define its role.
Register Bank Select bits RS1 and RS0 (PSW.4 and PSW.3, respectively)
These are boots for selecting one of the four register banks. Each of these register banks consists of
registers R0 through R7. The register banks are selected as below. As seen earlier, it must be noted
that at power-up-reset, bank 0 is selected as the default register bank and both RS1, RS0 bits are
cleared. Table 3 shows the address range of four register banks along with RS1, RS0 bits.
RS1 RS0 Register bank selected Address range in the on-chip RAM
00 Bank 0 00-07 H
01 Bank 1 08-0F H
10 Bank 2 10-17 H
11 Bank 3 18-1F H
Table 3 – Register Bank Select Bits
Overflow Flag (PSW.2)
Overflow flag (OV) is set because of an arithmetic operation (addition, subtraction, multiplication and
division), provided there is a carry out of bit 6, but not out of bit 7 or a carry out of bit 7 but not out
of bit 6; otherwise it is cleared. In the above example of addition two numbers 11000010B (0C2H) and
10101010B (0AAH), the addition results into a carry out of bit 7 but not out of bit 6. Therefore, the OV
flag will be set along with the carry flag.
Asst. Prof. Selvin Furtado [44]
Dept. Electronic & Telecommunication Engg. Top↑
TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
Parity Flag (PSW.0)
Parity flag indicates the number of ‘1’s in accumulator. If there are odd number of ‘1’s in accumulator,
then this odd parity will set the parity flag (P) to 1. For even parity, the parity flag will be cleared.
Data Pointer (DPTR)
DPTR is a 16-bit register consisting of two bytes. The higher byte is referred to as DPH, whereas the
lower byte is referred to as DPL. The data pointer is used for addressing the off-chip data and code,
with the MOVX and MOVC commands, respectively. With 16-bit pointer DPTR, a maximum of 64 K of
off-chip data memory and a maximum of 64 K of off-chip program memory can be addressed. It may
be used as a general-purpose register also. There is an instruction “INC DPTR" for incrementing 16-bit
contents of DPTR. However, there is no such instruction in 8051 to decrement the DPTR. It is also
possible to load the DPTR with a 16-bit immediate data using the MOV instruction.
Timer Registers
Register pairs (TH0, TL0), (TH1, TL1). (TH2. TL2) form 16-bit time/counter registers 0, 1, 2, respectively.
There are instructions for reading and writing these registers byte-wise. Timer/Counter 2 is only
available in 8052. The operation may be timing or counting. Further, there are various modes in which
timers can be configured. For this purpose, there are timer control (TCON) and timer mode registers
(TMOD).
Ports 0 to 3
P0, P1. P2. P3 are the SFRs corresponding to four I/O ports respectively. Each of these ports is bit
addressable as well as byte addressable.
Control Registers
TCON. TMOD, IE, IP, SCON, PCON contain the control and status for interrupts, serial I/O and
timer/counters.
Asst. Prof. Selvin Furtado [45]
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
2.4 Pin configuration
Figure 13: Pin Diagram of 8051
XTAL2 (Pin 18)
Output of inverting amplifier that forms a part of the oscillator and input to the internal clock
generator. In case of external clock, it must be connected to XTAL2.
XTAL1 (Pin 19)
XTAL1 is the input to the inverting amplifier that forms part of the oscillator circuit. In case of external
clock, this pin must be connected to ground.
Vcc (Pin 40)
Vcc pin is connected to +5V power supply. Rated power supply current for 8031/8051 is 125mA. The
maximum power dissipation rating is 1 W.
Vss (Pin 20)
Vss is the circuit ground. All the voltages are specified with respect to this pin. For example, voltage on
any pin with respect to Vss should be within —0.5 to +7V range.
Asst. Prof. Selvin Furtado [46]
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
Port 0 (Pins 32-39)
Port 0 is an 8-bit true bi-directional open drain I/O. Low order address and data bus is also multiplexed
with Port 0. Port 0 is open drain and must be pulled high externally through a pull-up resistor1.
Port 1 (Pins 1-8)
Port 1 is an 8-bit quasi-bidirectional I/O. The term quasi-bidirectional port is due to the fact that Port
1 pins are internally pulled high with fixed pull-up resistors. One has to configure it either as input or
output. Writing a '1' In the port latch causes it to act as input. When configured as input, the port pin
is pulled high and will source current if it is made low externally.
Part 2 (Pins 21-28)
Port 2 is also an 8-bit quasi-bidirectional I/0 port. Port pins are pulled high internally. It is multiplexed
with the higher order address bus.
Port 3 (Pins 10-17)
Port 3 is again an 8-bit quasi-bi-directional I/O port. Port pins are pulled high internally. There are
other functions multiplexed with Part 3 pins. The alternate functions are listed in Table 4. These
alternate functions of Port 3 pins are related to external interrupts, serial port, timer/ counter and
read/write control signals.
Table 4: Alternate functions of Port 3 pins
P3.0 RXD serial input
1 Pull-up resistor ensures that, given no other input, a port pin assumes a default value of '1' and prevents input
lines from floating. For an open drain connection pull-up is must. (Resistor also defines the current flowing
through the pull-up circuit; a strong pull-up means low resistance and a weak pull-up means a high resistance.)
Similarly, in other applications, a pull-down resistor may be required.
Asst. Prof. Selvin Furtado [47]
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
P3.1 TXD serial output
P3.2 ̅I̅N̅̅T̅̅0̅ external interrupt
P3.3 I̅̅N̅̅T̅̅1̅ external interrupt
P3.4
P3.5 T0 timer/counter 0 external input
P3.6
P3.7 T1 timer/counter 0 external input
̅W̅̅̅R̅ external data memory write strobe
R̅̅̅D̅ external data memory read strobe
Pin 9 (RST)
For resetting the device, the RST pin of 8051 is made high for two machine cycles, while the oscillator
is running. A power-on-reset circuit is shown in Fig. 3.2. A pull-down resistor of 8.2KΩ from the RST
pin to Vss and a capacitor of 10 µF from the RST pin to Vcc form the reset circuit. These component
values are sufficient to provide a delay, so as to make the RST line high for 24 oscillator periods. To
support the manual reset function, if desired do, a switch may be added across the 10µF capacitor.
Asst. Prof. Selvin Furtado [48]
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
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TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
2.5 Memory Organization
The 8051 has 64K external data memory, 64K program memory and 256 bytes of internal data
memory. The program memory map of 8051 is shown in Figure 15. The 64K program memory space
of 8051 is divided into internal and external memory. If the E̅̅̅A̅ pin is high, then 8051 executes from
the internal program memory until the address exceeds 0FFFH.
After that, locations 1000H through 0FFFFH are executed from the external memory portion. If ̅E̅̅A̅ pin
is held low, then 8051 executes instructions from external memory only. Table 3.2 shows this. The
external 64 K of data memory can be accessed using MOVX instruction. Figure 14 shows the internal
and external data memory of 8051.
Present in 8052
families only
Figure 14 - Internal and External Data Memory of 8051.
Figure 15 - Program Memory of 8051.
The internal data memory of 8051 is 256 bytes, which is divided into two parts again. The lower 128
bytes (00H through 7FH) called as the internal data RAM and the upper 128 bytes (80H through FFH)
consists of special function registers (SFRs). In case of 8032/52, the upper 128 bytes of internal data
memory are also addressable. Even though the SFRs and upper 128 bytes of RAM have the same
address space, they are different and accessed through different addressing modes. The lower 128
bytes of on-chip RAM are shown in Figure 16.
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