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Published by Rahul Rahi, 2019-11-14 09:12:27

MEP

MEP

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

Figure 16 - On-Chip RAM (Lower 128 bytes)

Asst. Prof. Selvin Furtado [51]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.6 Input /Output Ports

The four Ports 0, 1, 2 and 3 (P0, P1, P2, P3) each use 8 pins, making them 8-bit ports. All the ports

upon RESET are configured as input, since P0-P3 have value FFH on them.

2.6.1 Port 0

Port 0 pins may serve as inputs, outputs, or, when used together, as a bi-directional low-order address
and data bus for external memory. For example, when a pin is to be used as an input, a 1 must be
written to the corresponding port 0 latch by the program, thus turning both of the output transistors
off, which in turn causes the pin to “float” in a high-impedance state and the pin is essentially
connected to the input buffer.

When used as an output, the pin latches that are programmed to a 0 will turn on the lower FET,
grounding the pin. All latches that are programmed to a 1 still float; thus, external pullup resistors will
be needed to supply a logic high when using port 0 as an output.

When port 0 is used as an address bus to external memory, internal control signals switch the address
lines to the gates of the Field Effect Transistors (FETs). A logic 1 on an address bit will turn the upper
FET on and the lower FET off to provide a logic high at the pin. When the address bit is a zero, the
lower FET is on and the upper FET off to provide a logic low at the pin. After the address has been
formed and latched into external circuits by the Address Latch Enable (ALE) pulse, the bus is turned
around to become a data bus. Port 0 now reads data from the external memory and must be
configured as an input, so a logic 1 is automatically written by internal control logic to all port 0 latches.

Asst. Prof. Selvin Furtado [52]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.6.2 Port 1

Port 1 pins have no dual functions. Therefore, the output latch is connected directly to the gate of the

lower FET, which has an FET circuit labelled “Internal FET Pullup” as an active pullup load.

Used as an input, a 1 is written to the latch, turning the lower FET off; the pin and the input to the pin
buffer are pulled high by the FET load. An external circuit can overcome the high impedance pullup
and drive the pin low to input a 0 or leave the input high for a 1.

If used as an output, the latches containing a 1 can drive the input of an external circuit high through
the pullup. If a 0 is written to the latch, the lower FET is on, the pull-up is off, and the pin can drive the
input of the external circuit low.

To aid in speeding up switching times when the pin is used as an output, the internal FET pullup has
another FET in parallel with it. The second FET is turned on for two oscillator time periods during a
low-to-high transition on the pin, as shown in Figure 2.7 This arrangement provides a low impedance
path to the positive voltage supply to help reduce rise times in charging any parasitic capacitances in
the external circuitry.

Asst. Prof. Selvin Furtado [53]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

Asst. Prof. Selvin Furtado [54]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

Asst. Prof. Selvin Furtado [55]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

Asst. Prof. Selvin Furtado [56]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.7 Counter and Timers

Asst. Prof. Selvin Furtado [57]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.7.1 Timer Counter Interrupts [58]
Top↑
2.7.2 Timing

Asst. Prof. Selvin Furtado
Dept. Electronic & Telecommunication Engg.

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.7.3 Timer Modes of Operation [59]
2.7.3.1 Timer Mode 0 Top↑

2.7.3.2 Timer Mode 1

Asst. Prof. Selvin Furtado
Dept. Electronic & Telecommunication Engg.

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051
2.7.3.3 Timer Mode 2

Asst. Prof. Selvin Furtado [60]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.7.3.4 Timer Mode 3

2.7.4 Timer Program

Assuming crystal frequency = 11.0592 MHz, write an assembly language program for 8051 to
generate square wave of 2 kHz at pin P2.5. Show necessary delay calculation. (Use Timer-0, Mode-
0)

The timer works with a clock frequency of 1/12 of the XTAL frequency; therefore, we have 11.0592
MHz / 12 = 921.6 kHz as the timer frequency. As a result, each clock has a period of T = 1 / 921.6 kHz
= 1.085 (is. In other words, Timer 0 counts each 1.085 us resulting in delay = number of counts x 1.085
us.

Square wave frequency should be 2kHz, i.e. time period of 0.5msec. This implies 0.25ms ON and 0.25
msec OFF.

Therefore, if resulting delay = 0.25msec, then number of counts = 0.25m sec / 1.085usec = ~230.41

Rounding to 230 => 0E6H

The number of counts for the rollover is 1FFFH* – E6H – 1 =1F19H (1 1111 0001 1001b). Here, we
subtract one to E6 because of the extra clock needed when it rolls over from FFFF to 0 and raises the
TF flag.

Now lower 5 bits are to be loaded in TLx and upper 8 bits are to be loaded in THx, therefore
TL0=XXX11001b ( replacing don’t care bits (XXX) by 000, TL0=19H, and TH0= F8H.

Count value to be loaded in THTL = 1F18H

Asst. Prof. Selvin Furtado [61]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

*Since mode 0 is 13 bit timer it’ll count from 0000H to 1FFFH.

HERE: MOV TMOD,#00H ;Timer 0, mode 0, (13bit mode)
MOV TL0, #19H ;TL0 = XXH, the Low byte
MOV TH0, #F8H ;THO = FFH, the High byte
CPL P2.5 ;toggle P2.5
ACALL DELAY
SJMP HERE ;load TH, TL again

; ——delay using Timer 0 ;start Timer 0
;monitor Timer 0 flag until
DELAY: ;it rolls over
;stop Timer 0
SETB TR0 ;clear Timer 0 flag

AGAIN: JNB TF0, AGAIN

CLR TR0
CLR TF0
RET

2.7.5 Counting

Asst. Prof. Selvin Furtado [62]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.8 Serial Communication

Computers must be able to communicate with other computers in modern multiprocessor distributed

system. One cost-effective way to communicate is to send and receive data bits serially. The 8051 has

a serial data communication circuit that uses register SBUF to hold data. Register SCON controls data

communication, register PCON controls data rates, and pins RXD (P3.0) and TXD (P3.1) connect to the

serial data network.

2.8.1 Serial Data Interrupt [63]
Top↑
2.8.2 Data Transmission

Asst. Prof. Selvin Furtado
Dept. Electronic & Telecommunication Engg.

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.8.3 Data Reception

Asst. Prof. Selvin Furtado [64]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

Asst. Prof. Selvin Furtado [65]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.8.4 Serial Data Transmission Modes

2.8.4.1 Serial Data Mode 0 – Shift Register Mode

Asst. Prof. Selvin Furtado [66]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.8.4.2 Serial Data Mode 1 – Standard UART

Asst. Prof. Selvin Furtado [67]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.8.4.2.1 Mode 1 Baud Rates

2.8.4.3 Serial Data Mode 2 – Multiprocessor Mode

Asst. Prof. Selvin Furtado [68]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

certain messages, while other receivers ignore those messages. Only those 8051’s that have SM2 set
to 0 will be interrupted by received data which has the ninth data bit set to 0; those with SM2 set to
1 will not be interrupted by message with data bit 9 at 0. All receivers will be interrupted by data
words that have the ninth data bit set to 1; the state of SM2 will not block reception of such messages.

This scheme allows the transmitting computer to “talk” to select receiving computers without
interrupting other receiving computers. Receiving computers can be commanded by the “talker” to
“listen” or “deafen” by transmitting coded byte(s) with the ninth bit set to 1. The 1 in data bit 9
interrupts all receivers, instructing those that are programmed to respond to the coded byte(s) to
program the state of SM2 in their respective SCON registers. Selected listeners then respond to the
bit 9 set to 0 messages, while all other receivers ignore these messages. The talker can change the mix
of listeners by transmitting bit 9 set to 1 message that instruct new listeners to set SM2 to 0, while
others are instructed to set SM2 to 1.

2.8.4.4 Serial Mode 3
Mode 3 is identical to mode 2 except that the baud rate is determined exactly as in mode 1, using
Timer 1 to generate communication frequencies.

Asst. Prof. Selvin Furtado [69]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.9 Interrupts

Asst. Prof. Selvin Furtado [70]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

Asst. Prof. Selvin Furtado [71]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.9.1 Timer Interrupt Flag

2.9.2 Serial Port Interrupt

2.9.3 External Interrupts

Asst. Prof. Selvin Furtado [72]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.9.4 Reset

2.9.5 Interrupt Control [73]
Top↑
Asst. Prof. Selvin Furtado
Dept. Electronic & Telecommunication Engg.

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.9.6 Interrupt Enable/Disable

2.9.7 Interrupt Priority

Asst. Prof. Selvin Furtado [74]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.9.8 Interrupt Destinations

2.9.9 Software Generated Interrupts

Asst. Prof. Selvin Furtado [75]
Dept. Electronic & Telecommunication Engg. Top↑

TE-IT: MEP Module 2 - The Microcontroller Architecture and Programming of 8051

2.10Instruction Set with Examples

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