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ABCDXY
e)
ABCDEXY
0000
0 100
0100
0111
1111
1100
1110
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2.3 BOOLEAN LAWS AND THEOREMS
In digital system, there are several methods to simplify the logic circuit and one of them is
Boolean laws. The laws and expressions are stated in Table 2.1.
In Boolean algebra,
0̅ = 1, 1̅ = 0
If X = 1, then ̅ = 0
If X = 0, then ̅ = 1
Table 2.1 : Boolean laws and theorems
BOOLEAN BOOLEAN
ALGEBRA BOOLEAN EXPRESSION ALGEBRA BOOLEAN EXPRESSION
RULES LAWS
Addition Rules Commutative Laws
1 A+0=A 1 A+B=B+A
2 A+1=1 2 AB = BA
3 A+A=A
4 A + A̅ = 1 Associative Laws
Multiplication Rules 3 A + (B + C) = (A + B) + C
5 A•0=0
6 A•1=A 4 A(BC) = (AB)C
7 A•A=A Distributive Laws
8 A • A̅ = 0
5 A(B + C) = AB + AC
Involution / Complement Rules
9 A = A̿ (A + B)(C + D) =
6
Other Rules
AC + AD + BC + BD
10 A + AB = A DeMorgan’s Theorem
11 A + A̅B = A + B 1 A̅̅̅+̅̅̅B̅ = A̅•B̅
12 A̅ + AB = A̅ + B 2 A̅̅̅⦁̅̅̅B̅ = A̅+B̅
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Example 1:
Based on Boolean expression F = ̅ ̅ ̅̅ ̅̅+̅̅̅̅ ̅ ̅̅ ̅ . ( + ) ,
i. Draw the logic diagram.
ii. Simplified the equation by using Boolean laws and theorems.
iii. Redraw the simplified version.
i.
ii. ̅ ̅ ̅̅ ̅̅+̅̅̅̅ ̅ ̅̅ ̅ . ( + ) = (̅ ̅ ̅ ̅ . ̅ ̅ ̅̅ ̅ ) ( + ) Apply DeMorgan
= ( ̅ + ̿ )( ̿ + ̅ )( + ) Apply Involution
= ( ̅ + )( + ̅ )( + ) Apply Distributive
= ( ̅ + ̅ ̅ + + ̅ ) ( + ) Apply Multiplication
= (0 + ̅ ̅ + + 0) ( + ) & Distributive again
= ̅ ̅ + ̅ ̅ + + Apply Multiplication
= 0 + 0 + BA + BA Apply Addition
= BA
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iii.
Example 2:
Show that Q = ( ̅ ( + ) + ̅ ̅ ). = ̅ and draw its simplification diagram.
Z = ( ̅ ( + ) + ̅ ̅ ) . Apply Distributive
= ( ̅ + ̅ + ̅ ̅ ) .
= ̅ + 0 + ̅ ̅ Apply Distributive &
= ̅ + ̅ ̅ Multiplication
= ̅ ( + ̅ )
= ̅ (1) = ̅ Apply Distributive
Apply Multiplication
Apply Addition
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Example 3:
Show that Z = ̅(̅(̅ ̅̅̅ ̅̅.̅̅ ̅̅ ̅̅.̅̅̅ ̅ ̅̅)̅̅+̅̅̅ ̅̅ ̅̅). . ( ̅̅ ̅+̅̅̅̅ ̅ ̅̅̅) = ̅
Z = (̅̅̅(̅̅ ̅̅̅̅ ̅̅.̅̅̅̅̅ ̅̅̅ ̅̅̅.̅̅̅̅ ̅̅ ̅̅̅)̅̅̅̅+̅̅̅̅̅̅ ̅̅ ̅)̅ . . (̅ ̅ ̅+̅̅̅̅ ̅ ̅̅̅) Apply Involution &
= (̅ ̅ ̅ ̅ ̅ ̅ + ) . . ( ̅ . ̿) DeMorgan
= ( ̅ + ̿ + ̅ + ) . ( ̅ )
Apply DeMorgan, Involution
& Associative
Apply Distributive
= ̅ ̅ + ̅ + ̅ ̅ + ̅ Apply Multiplication
= ̅ + ̅ + 0 + ̅ Apply Addition
= ̅ = ̅
1. Draw the combinational logic diagrams based on the given expressions and simplify them by using
the Boolean’s laws. Then, redraw the simplified version.
a) = ( ̅ + )( + )
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b) = + ( + ) + ( + )
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c) = [ ̅ ( + ) + ̅ ̅ ]
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d) = ( ̅ + )( + + ) ̅
e) = (̅̅ ̅ ̅ ̅ ̅̅+̅̅̅ ̅̅ ̅)̅̅+̅̅̅(̅̅ ̅ ̅̅+̅̅̅ ̅̅)
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f) = ̅̅̅ ̅̅̅+̅̅̅̅̅̅ ̅̅ ̅̅ ̅̅ ̅̅+̅̅̅̅ ̅ ̅ ̅̅
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2. Prove that the left Boolean expression is similar to the right Boolean expression.
a) ̅ + + ̅ ̅ = ̅ +
b) ̅ ̅ + ̅ + ̅ = ̅ + ̅
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c) ( + + ) . ( ̅ + + ) = +
d) ̅̅ ̅ ̅ + + ̅ = 1
e) (̅ ̅ ̅̅ ̅ ̅̅+̅̅̅ ̅ ̅̅̅) ( + ) = ( + ̅ )
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f) (̅ ̅ ̅ ̅̅+̅̅̅̅ ̅ ̅ ̅ ̅̅) ( + ̅ + ) = ̅ + ̅ + ̅
2.4 REPRESENTATION OF BOOLEAN EXPRESSIONS (SOP AND POS)
Minterms and Maxterms
There are two ways to express the Boolean expressions which are:
1) Minterms Input terms that are equal to 1
2) Maxterms Input terms that are equal to 0
The concept of minterms or sometimes can also call as Sum of Product (SOP) represents
the product terms (AND) are connected by summation operator (OR). In other words, it is
the addition of multiplication terms.
The SOP can be presented based on output 1.
Y = ̅ + ̅
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The concept of maxterms or sometimes can also call as Product of Sum (POS) represents
the sum terms (OR) are connected by multiplication operator (AND). In other words, it is
the multiplication of addition terms.
The POS can be presented based on output 0.
Y = ( + ̅ + ). ( ̅ + + )
Example:
Obtain the minterms and maxterms for the input below and write the Boolean expression in SOP and POS form.
ABQ
001
010
101
110
ABQ Minterms Maxterms
001 ̅ ̅
010 ̅ +
101 ̅ + ̅
110 ̅ ̅ ̅ +
̅ + ̅
∴ SOP expression : Q = ̅ ̅ + ̅
- The SOP is gathered from output, Q = 1
∴ POS expression : Q = ( + ̅ )( ̅ + ̅ ) - The POS is gathered from output, Q = 0
-
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1. Complete the table of Minterm and Maxterm below and express in both SOP and POS forms the
Boolean function of Q(A,B,C).
A B C Q Minterms Maxterms
0001
0010
0101
0110
1001
1010
1100
1111
∴ SOP expression :
∴ POS expression :
2. Given the truth table of a function F(X,Y,Z). Write the SOP and POS expression from the following
truth table.
XY Z F
0000
0010
0101
0111
1000
1011
1101
1110
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∴ SOP expression :
∴ POS expression :
2.5 MINIMIZATION OF LOGIC CIRCUIT (KARNAUGH MAP)
There are many ways to simplify the logic circuit such as by using Boolean Laws and Karnaugh
Map (K-Map).
A K-Map is a graphical method in facilitating to minimize the logic circuit based on truth table.
Sometimes, it is simpler than Boolean algebra as the expression can be derived directly from the
map created. However, it is no longer practical for more than six inputs.
In creating a K-Map, the label of input variables should come along with their complements. It
can be constructed with the arrangement of input variables either like the following maps or the
other way around.
The K-Map is then filled up with output values.
For a two-variable K-Map, the K-Map designed is :
A B Product ̅
term ̅ ̅ ̅
̅
0 0 ̅ ̅ ̅
0 1 ̅
1 0 ̅
1 1
Note: It can be switched so
that variable ̅ and are
located at the left column
and variable ̅ and are
located at the upper row.
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For a three-variable K-Map, the K-Map designed is :
A B C Product ̅
term ̅ ̅ ̅ ̅ ̅
̅ ̅ ̅
0 0 0 ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ ̅ ̅
0 0 1 ̅ ̅
0 1 0 ̅ ̅ ̅
0 1 1 ̅
1 0 0 ̅ ̅
1 0 1 ̅
1 1 0 ̅
1 1 1
For a four-variable K-Map, the K-Map designed is :
A B C D Product ̅ ̅ ̅ ̅
term ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
0 0 0 0 ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
0 0 0 1 ̅ ̅ ̅
0 0 1 0 ̅ ̅ ̅
0 0 1 1 ̅ ̅
0 1 0 0 ̅ ̅ ̅
0 1 0 1 ̅ ̅
0 1 1 0 ̅ ̅
0 1 1 1 ̅
1 0 0 0 ̅ ̅ ̅
1 0 0 1 ̅ ̅
1 0 1 0 ̅ ̅
1 0 1 1 ̅
1 1 0 0 ̅ ̅
1 1 0 1 ̅
1 1 1 0 ̅
1 1 1 1
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In order to perform the grouping, there are some rules to follow which are:
1) No zeros allowed – each group should contain only number 1 and every number 1 must be
included in group.
̅ ̅
̅ 1 1 ̅ 1 1
0 0 0 1
2) No diagonals or random shapes.
̅ ̅ ̅ ̅ ̅
̅ ̅ 0 1
̅ 1 0 ̅ ̅ 0 0 00
0 1
̅ 1 ̅ 1 1 11
1
1 1 11
̅ 0 0 00
̅
̅ ̅ 1 1
̅ 1 1
0 0
̅ 1 1
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3) The groups should be as large as it can create – only 2 for each group. (x stands for number
of variables. That means 24, 23, 22, 21, 20 or 16, 8, 4, 2, 1. If it is 5 variables K-Map, then
the largest group is 25 = 32.
When there are four variables (A, B, C and D), the largest size of group is 24 = 16. If
group of 16 is not available, then create the right group of 8 and so on.
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ 0 0 00 ̅ ̅ 0 0 00
̅ 1 1 11 ̅ 1 1 11
1 1 11 1 1 11
̅ 0 0 00 ̅ 0 0 00
̅ ̅ ̅ ̅ ̅
̅ ̅ 1 0
̅ ̅ 1 1 11 ̅ 1 0
1 0
̅ 1 1 11 ̅ 0 1
0 0 11
̅ 0 0 11
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4) Overlapping and wrapped around are allowed.
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ 1 1 10 ̅ ̅ 1 1 10
̅ 1 1 10 ̅ 1 1 10
0 0 10 0 0 10
̅ 0 0 00 ̅ 0 0 00
̅ ̅
̅ ̅ 1 0 ̅ ̅ 1 0
̅ 1 0 ̅ 1 0
1 0 1 0
̅ 0 1 ̅ 0 1
̅ ̅
̅ ̅ 0 1 ̅ ̅ 0 1
̅ 1 0 ̅ 1 0
0 1 0 1
̅ 1 ̅ 1
1 1
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̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ 1 0 01 ̅ ̅ 1 0 01
̅ 0 1 10
̅ 0 1 10
0 1 10 0 1 10
̅ 1 0 01 ̅ 1 0 01
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ 1 0 01 ̅ ̅ 1 0 01
̅ 1 1 11 ̅ 1 1 11
1 1 11 1 1 11
̅ 1 0 01 ̅ 1 0 01
̅ ̅
̅ ̅ 1 1 ̅ ̅ 1 1
̅ 1 1 ̅ 1 1
0 0 0 0
̅ 1 ̅ 1
1 1
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5) Fewest numbers of groups possible.
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ 1 1 00 ̅ ̅ 1 1 00
̅ 1 1 10 ̅ 1 1 10
0 0 10 0 0 10
̅ 0 0 00 ̅ 0 0 00
̅ ̅ ̅ ̅ ̅ ̅ ̅ ̅
̅ ̅ 0 0 00 ̅ ̅ 0 0 00
̅ 0 1 11 ̅ 0 1 11
0 0 10 0 0 10
̅ 0 0 00 ̅ 0 0 00
̅ ̅
̅ ̅ 1 1 ̅ ̅ 1 1
̅ 1 0 ̅ 1 0
0 1 0 1
̅ 0 ̅ 0 1
1
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Example:
Determine the minimum Boolean expression for the truth table below by using:
a) Boolean Law
b) Karnaugh Map
CBAQ
0000
0011
0101
0111
1000
1011
1101
1110
a) Boolean Law The equation is obtained
from the output Q = 1
= ̅ ̅ + ̅ ̅ + ̅ + ̅ + ̅
= ̅ ( ̅ + ) + ̅ ( ̅ + ) + ̅
= ̅ + ̅ + ̅
= ( ̅ + ̅ ) + ̅
= ( ̅ + ̅ ) + ̅
= ̅ + ̅ + ̅
= ̅ + ̅ + ̅
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b) Karnaugh Map K-Map obtained:
1
K-Map template: ̅ 1
̅ ̅ 0 0
̅ ̅ 1
̅ ̅ 1 1
̅ ̅ 0
̅
= ̅ ̅ + ̅ + ̅ ̅ + ̅ + ̅ ̅ + ̅
= ̅ ( ̅ + ) + ̅ ( ̅ + ) + ̅ ( ̅ + )
= ̅ + ̅ + ̅
= ̅ + ̅ + ̅
1. Design a logic circuit based on the given truth table below by using:
XY Z Q
0000
0011
0100
0111
1001
1011
1100
1111
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a) Boolean Law
b) Karnaugh Map
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2. Obtain the SOP Boolean expression from the given truth table and draw its simplified logic diagram.
CBAQ
0001
0010
0101
0110
1001
1010
1100
1111
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3. Compare the simplified expression of = ̅ ̅ ̅ + ̅ ̅ ̅ + ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ +
̅ + and its logic diagram by using:
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a) Boolean Law
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b) Karnaugh Map
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4. Use a Karnaugh Map to simplify the SOP Boolean expression of = ( ̅ ̅ + ) + ̅ + and
draw its logic circuit.
73
5. Design a logic circuit corresponding to the truth table below: DIGITAL SYSTEM
ABCD Q
0000 1
0001 0
0010 1
0011 0
0100 1
0101 1
0110 X
0111 1
1000 1
1001 0
1010 X
1011 0
1100 X
1101 1
1110 1
1111 0
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6. Minimize the following Boolean expressions by using a Karnaugh Map
a) Q = ̅ ̅ ̅ + ̅ ̅ + ̅
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b) Y = ̅ ̅ ̅ + ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ ̅ + ̅ ̅ + ̅ ̅ + ̅
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3.0 INTRODUCTION
It is where the output of the logic circuit depends on its present input and previous output as
illustrated in Figure 3.1.
Previous Present
output input
Output
Figure 3.1 : Concept of sequential logic circuit
The sequential logic circuit is based on flip-flop which is a bistable multivibrator that consists of
two stable state either 0 (LOW) or 1 (HIGH). It serves as one bit of memory to store the input.
Figure 3.2 show the general symbol of a flip-flop.
Inputs Normal output
̅ Inverted output
Figure 3.2 : General symbol of flip-flop
Some flip-flops only have one input which are D and T flip-flop whereas the others have two
inputs. However, there are two types of flip-flops that are called as latches.
Both flip-flops and latches serve to store data but they differ as in Table 3.1.
Table 3.1 : Main characteristic of both latch and flip-flop
LATCH FLIP-FLOP
The outputs are affected by each input. The output depends on the changes in
the clock signal.
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The sequential logic can operate either as asynchronous system or synchronous system.
An asynchronous system is when the change of output occurs anytime and depends on the state
changes in the inputs. It means that, the latches are asynchronous system.
Meanwhile a synchronous system is a system which has exact time to change the output and in
this case it is changed by a signal called as clock pulse.
Clock pulse signal is edge triggered and represented in a rectangular pulse train or square wave. It
consists of two types which are Positive Going Transition (PGT) and Negative Going Transition
(NGT).
Whenever the flip-flop is controlled by the clock pulse, the outputs can only change their states
when the clock signals do the transition either from 0 to 1 (PGT) or from 1 to 0 (NGT) as in
Figure 3.3.
PGT NGT
CLK
̅
CLK
̅
Figure 3.3 : The concept of clock signals
3.1 SR NAND GATE LATCH
It is constructed by using two NAND gates.
It has two inputs S (Set) and R (Reset). The set input will set the normal output, Q to 1 and the
reset input will reset the normal output, Q to 0.
Also known as Active Low flip-flop due to :
___________________________________________
___________________________________________
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S R Q ̅ Status
Logic circuit Truth table
Example:
Determine the output waveform of Q and ̅ for the given SR input below.
QDraw the dash-lines
for each change in
SR inputs and read
the value for every
column.
It is prohibited since
it tries to set and clear
simultaneously and
produces Q = ̅ = 1
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Sketch the output waveforms of Q and ̅ for the given inputs.
a)
b)
c) Q initial = 0
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d) 0 = 1
3.2 SR NOR GATE LATCH
It is constructed by using two NOR gates.
As similar to SR NAND gate latch in terms of the circuit connection and its principle operation, it
differs in its truth table. When S = 1 and R = 1, the condition is illegal due to the circuit needs to
set and reset at the same time therefore generate the same value of Q and ̅ which is 0.
Also known as Active High flip-flop due to :
___________________________________________
___________________________________________
S R Q ̅ Status
Logic circuit Truth table
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Example:
Generate the output waveforms of Q and ̅ for the given SR input below.
Draw the dash-lines
for each change in
SR inputs and read
the value for every
column.
Sketch the output waveforms of Q and ̅ for the given inputs.
a)
83
b) 0 = 1 DIGITAL SYSTEM
c) 84
d) Q initial = 0
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3.3 CLOCKED SR FLIP-FLOP
It is the basic clocked flip-flop which the output changes exactly upon the clock triggered.
Logic symbol (PGT) Logic symbol (NGT)
Logic circuit
S R Q Status
Truth table
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Example:
Draw the expected output waveforms of Q and ̅ for the PGT clocked SR input below and explain the operations
for every clock pulse. Assume the output Q initially HIGH.
Draw the dash-lines
and its up-arrow to
show the PGT. Take
the first value after
each dash line and
read from the table.
Explanations : Please note that, to draw the output for
every clock pulse (CP), we must recall
the output for previous CP (Q) first,
then, draw the output based on .
.
For CLK 1 (PGT 1) : When S = 0, R = 1, the previous output Q = 1, so the current output is 0. (R)
For CLK 2 (PGT 2) : When S = 0, R = 1, the previous output Q = 0, so the current output is 0. (R)
For CLK 3 (PGT 3) : When S = 1, R = 0, the previous output Q = 0, so the current output is 1. (S)
For CLK 4 (PGT 4) : When S = 1, R = 1, the previous output Q = 1, so the current output is 1.
(INVALID)
For CLK 5 (PGT 5) : When S = 0, R = 1, the previous output Q = 1, so the current output is 0. (R)
For CLK 6 (PGT 6) : When S = 1, R = 0, the previous output Q = 0, so the current output is 1. (S)
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1. Predict the output waveforms of Q and ̅ for the given inputs.
a) PGT, Q initial is LOW
b) NGT, 0 = 1
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2. Draw the output waveform of Q and explain its operation for each clock pulse.
a) PGT, 0 = 1
b) NGT, Q initially cleared.
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3.4 CLOCKED SR FLIP-FLOP WITH ASYNCHRONOUS INPUTS PRESET AND CLEAR
It is one of the synchronous flip-flops as it outputs depend on the clock signal.
However, the presence of the other inputs which are Preset and Clear can change the state of the
output regardless of the clock signal status.
The input Preset is used to set the output of the flip-flop to 1 while the input Clear is used to reset
it to be 0.
The symbol of this asynchronous input SR flip-flop and its truth table are shown in Figure 3.4.
CLK PRE Preset Clear Status
SQ 1 1 Synchronous *
R ̅ 0 1
1 0 Q=1
0 0 Q=0
Prohibited
CLR Truth table
Logic symbol
Figure 3.4 : Logic symbol and truth table for asynchronous input SR flip-flop
When Preset = Clear = 1, the output waveform of Q is determined by the Synchronous* inputs of
clocked SR flip-flop.
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Example:
Determine the output, Q of the following NGT clocked SR inputs which the output is initially cleared.
Draw the dash lines for each NGT and for
every starting transition of PRE/CLR.
(Reminder: Be sure the value of
PRE/CLEAR ahead!)
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Sketch the timing diagram of output Q based on the stated conditions and logic symbols:
a) Q initial is HIGH
PRE
CLK SQ
R ̅
CLR
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b) 0 = 1
CLK PRE
SQ
R ̅
CLR
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3.5 JK FLIP-FLOP
It is the most flexible flip-flop as it improves the characteristic of SR flip-flop. When both inputs
are equal to 1, it has toggle state in order to disregard the ambiguous state in SR flip-flop.
Therefore, JK flip-flop usually can be used to design other flip-flops such as D and T flip-flops.
Logic symbol (PGT) Logic symbol (NGT)
Logic circuit
J K Q Status
Truth table
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There are few major differences between JK and SR flip-flop such as in Table 3.2.
Table 3.2 : Differences between JK and SR flip-flop
JK FLIP-FLOP SR FLIP-FLOP
Example:
Determine the expected output waveforms of Q for the NGT JK flip-flop. Assume the output Q initially reset.
It applies the
same concept
of SR flip-
flop.
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