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Predict the output Q of the following JK inputs based on the stated conditions.
a) PGT, 0 = 1
b) NGT, Q initial is LOW
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c) PGT, Q initially cleared
d) NGT, 0 = HIGH
3.6 T FLIP-FLOP
T flip-flop stands for Toggle flip-flop. It has an input only which can be constructed by
connecting both J and K input to HIGH.
When the input is 1, it will toggle either from 1 to 0 or vice versa.
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Logic symbol Logic symbol with JK connection
Logic circuit
T Q Status
Truth table
Example:
Determine the output of Q and ̅ for the given T input waveform and explain its operation. Assume that Q
initially cleared.
TQ
D
CLK
̅
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Operation :
For CLK 1 (NGT 1), when T = 1, it will toggle to 1 from the previous output 0.
For CLK 2 (NGT 2), when T = 1, it will toggle to 0 from the previous output 1.
For CLK 3 (NGT 3), when T = 0, it has no changes from the previous output 0.
For CLK 4 (NGT 4), when T = 1, it will toggle to 1 from the previous output 0.
For CLK 5 (NGT 5), when T = 1, it will toggle to 0 from the previous output 1.
1. Determine the timing diagram for output Q and ̅ of the given T input if the flip-flop is:
a) PGT, Q initial is HIGH
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b) NGT, 0 = 0
c) NGT, Q initially HIGH
2. Explain the operation of the system below based on the output obtained.
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3.7 D FLIP-FLOP
It is also known as Data or Delay flip-flop.
This flip-flop consists of a single input to serve as a storage element for a single binary bit hence;
it can be constructed by adding an inverter into the SR or JK inputs.
It will reset the output when input is 0 and set the output when input is 1.
Logic symbol Logic symbol with JK connection
Logic circuit
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D Q Status
Truth table
Example:
Determine the output of Q and ̅ for the given PGT D flip-flop. Assume that 0 = 1.
D flip-flop has the simplest
operation! The output exactly
follows the input data after each
clock.
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Draw the timing diagram for output Q of the following D input.
a) NGT, Q initial is HIGH
b) PGT, 0 = 1
c) PGT, Q initially reset to 0
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4.0 INTRODUCTION
A counter is a sequential logic circuit contains a connection of flip-flops which can go through a
predetermined sequence of states upon the application of clock pulses.
There are two types of counter which are compared in Table 4.1.
Table 4.1 : Types of counter
ASYNCHRONOUS COUNTER SYNCHRONOUS COUNTER
The first flip-flop is driven by a clock signal All flip-flops are driven by the same clock
(CLK) while the consecutive flip-flops are signal (CLK).
driven by the output of preceding flip-flop.
The outputs do not change state simultaneously The outputs change state at the same time due
as they have to wait for each clock signal from to the same clock pulse triggered
the output of prior flip-flop. simultaneously.
Simpler circuit connection. Requires more circuitry.
Cannot count random number. (Up, down or Able to count random number.
up/down only)
It can be constructed by any type of flip-flop. However, JK flip-flop is the most suitable to use
due to its stability condition.
4.1 ASYNCHRONOUS COUNTER
It is also known as ripple counter due to the clock signal receives through the counter makes the
propagation delay in processing the input. The flip-flops cannot change state until the preceding
one has done so.
The accumulate delay from one flip-flop to another will generate false counts especially in MSB
in that counter.
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In the constructed timing diagram, it does not seem like the counter has ripple effect (glitch).
However, in a real situation, for example up counter, it supposedly counts up from 101 to 110 (5
to 6). Yet, it immediately ripples from 101 to 100 then 110 like the illustration below:
Delay
n-number of flip-flops can build up a MOD 2 counter. MOD (Modulus) is the number of states
it counts in a complete cycle before return to the initial state.
Let say the flip-flop, n = 3;
23 = 8
∴ MOD 8
For 3 flip-flops, we can design a MOD 8 asynchronous counter which can count up to
111 (7) either in up counter or down counter or up/down counter.
In order to design either up or down counter, the circuit connection of the clock pulse should be
like :
UP DOWN
PGT ̅
NGT ̅
4.1.1 ASYNCHRONOUS UP COUNTER
For MOD-N up counter, it will count from 0 up to (N – 1). When it reaches the N state, the
counter will reset to the origin 0. Usually, the CLEAR buttons are connected together so that it
can clear all the flip-flops before counting starts.
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Example 1:
Design a MOD 4 up counter by using JK flip-flops with negative edge triggered.
Step 1 : Number of flip-flop & bit used
MOD 4 2 = 4
n = log 4
M
O log 2
D
n=2
Step 2 : State transition diagram (0 to (N – 1)) 00
4 11 01
0 10
31
2
Step 3 : Truth table CLOCK OUTPUT
Step 4 : Logic circuit 1 0
0 00
1 01
2 10
3 11
4 00
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Example 2:
Based on the Example 1, draw the timing diagram to show its state transition.
Please read the timing 00 01 10 11 00 01
diagram data from 01 230 1
bottom to top
(MSB LSB)
Example 3:
Design a MOD 4 up counter by using several positively edge clock of JK flip-flops and predict its timing
diagram.
Step 1 : Number of flip-flop & bit used
MOD 4 2 = 4
n = log 4
log 2
n=2
Step 2 : State transition diagram (0 to (N – 1)) 00
11 01
0
31 10
2
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Step 3 : Truth table CLOCK OUTPUT
Step 4 : Logic circuit 1 0
0 00
1 01
2 10
3 11
4 00
Step 5 : Timing diagram
01 10 11 00 01 10
The input is T even though the 301 2
circuit used JK flip-flops. 12
(Refer to 3.6)
The data is taken only from the
normal output, Q0 and Q1.
The ̅ ̅ ̅0̅ is used ONLY to
provide clock for Q1.
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1. Design a MOD 8 up counter with PGT JK flip-flops and draw the timing diagram it should be generated.
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2. Construct a MOD 16 up counter using NGT JK flip-flops connection.
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4.1.2 ASYNCHRONOUS DOWN COUNTER
For MOD-N down counter, it will count from (N – 1) downward to 0.
Example:
Design a MOD 4 down counter by using PGT JK flip-flops and draw the supposedly generated timing
diagram.
Step 1 : Number of flip-flop & bit used
MOD 4 2 = 4
n= log 4
log 2
n=2
Step 2 : State transition diagram ((N – 1) to 0) 11
00 10
3
02 01
1
Step 3 : Truth table
CLOCK OUTPUT
1 0
0 11
1 10
2 01
3 00
4 11
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Step 4 : Logic circuit
Step 5 : Timing diagram
11 10 01 00 11 10
3 2 101 2
1. Find the operated MOD for the given circuit and sketch the timing diagram for all outputs.
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2. Construct an octal down counter by using NGT JK flip-flops with the following steps:
a) Number of flip-flops and bits used
b) State transition diagram
c) Truth table
d) Logic circuit
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4.1.3 ASYNCHRONOUS UP / DOWN COUNTER
Similar to up or down counter, this asynchronous up/down counter is designed so that, it can
count in either up to down or vice versa in a sequence.
Anyhow, in order to make it possible to count both, there are another two control input signals
which are UP and DOWN.
Upward Sequence
The counter will count upward, when the UP input is 1 whereas DOWN input is 0.
Hence, the NAND gates between FF0 and FF1 will pass the normal output, Q of FF 0 to
the clock input of FF 1.
Thus the UP/DOWN counter performs up counting.
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Downward Sequence
The counter will count in descending order, when the DOWN input is 1 while UP input is
0.
Therefore, the NAND gates between FF0 and FF1 will pass the inverted output, ̅ of FF
0 to the clock input of FF 1.
Thus the UP/DOWN counter performs down counting.
This counter is slower than an individual up and down counter because of the extra propagation
delay in NAND gate networks.
Example:
For a 2-bit up/down counter below, sketch the complete timing diagram to show its counting sequence.
The counter is initially reset.
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NGT clock triggered. 01 10 11 00 01 10
Count upward :
- UP is 1, DOWN is 0
- Clock at FF1 is from
normal output, Q0.
NGT clock triggered. 11 10 01 00 11 10
Count downward :
- UP is 0, DOWN is 1
- Clock at FF1 is from
inverted output, ̅̅ ̅0̅.
UP
DOWN
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Draw the circuit diagram for MOD 8 asynchronous up/down counter with PGT clock and its square
waveform attained.
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4.1.4 ASYNCHRONOUS COUNTER WITH MOD ≠
This counter is similar in its concept with the previous counters. However, the former counters
are presented in MOD 2 , where n is equal to the number of flip-flops.
In order to count less than 2 , the CLEAR pin is needed to reset all outputs to 0.
The outputs of flip-flop which produce logic 1 are connected to a NAND gate and it is then
required to connect to CLEAR pin.
Example:
Design a MOD 5 up counter by using JK flip-flops with positive edge triggered and prove its correct
transition by the timing diagram.
Step 1 : Number of flip-flop & bit used
MOD 5 2 = 5
n= log 5
log 2
n = 2.32 ≈ 3
Step 2 : State transition diagram (0 to (N – 1)) 000
100 001
0
41
32 011 010
Step 3 : Truth table
CLOCK 2 OUTPUT 0
0 1 0
0 0 0 1
1 0 0 0
2 0 1 1
3 1 1 0
4 0 0 0
5 0
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Step 4 : Logic circuit DIGITAL SYSTEM
LSB MSB
1 01
Step 5 : Timing diagram
000 001 010 011 100 000
0
0 1 2340
Note that:
At the fifth PGT clock, the NAND gate will reset to
000 when it detects the logic 1 from Q0 and Q2
although the Q2 does not receive the clock at that
time from ̅ ̅ ̅1̅.
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1. Create a decade down counter by using PGT JK flip-flops and show its produced transition
waveform.
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2. Draw a logic diagram of MOD 14 up counter with negative edge triggered.
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4.1.5 ASYNCHRONOUS COUNTER AS A FREQUENCY DIVIDER
In any counter, the output frequency for each flip-flop is exactly one half (1⁄2) from the input
frequency for each flip-flop.
1= 2= 1 3= 2
2 2 2
4 = 3
2
In other words, instead of finding the frequency as mention above, another way to determine the
output frequency for each flip-flop is :
= ; where n = number of flip-flop & bit
2
1= 2= 3=
21 22 23
4=
24
Eventually, the frequency of the last flip-flop, is equal to the input frequency divided by the MOD
of the counter
=
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1. The output frequency, for a 5-bit asynchronous counter is 12.5 kHz. Find the output frequency:
a) for the second flip-flop b) for the fourth flip-flop
2. The input frequency of an asynchronous counter is 1 MHz. If the output frequency, is 50 kHz,
calculate:
a) The modulus of the counter b) The number of flip-flop used
= Recall that, MOD =
2 where n = number
of flip-flop.
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3. The output frequency, for an asynchronous counter is 47.5 kHz. Given the input frequency is
617.5 kHz.
a) Calculate the modulus of the counter b) Determine the number of flip-flop used
c) Sketch the suitable asynchronous down counter circuit for negative going transition based on
information above.
When the number of MOD and
flip-flops are available, then,
the similar concept is applied
as in previous sections.
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4. Design an asynchronous up counter for positive edge triggered JK flip-flop if the input frequency is
1.155 MHz and its output frequency, is 105 kHz.
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4.2 SYNCHRONOUS COUNTER
It is also known as parallel counter. This counter is designed to overcome the limitation in
asynchronous counter by changing its clock connection. The clock is connected with the common
input pulse hence; it helps the flip-flops triggered and change states simultaneously.
Even though it requires more circuitry than asynchronous counter, some of the advantages of
using a synchronous counter are it eliminates the cumulative propagation delay besides it can be
used to count any MOD numbers in forward, reverse or irregular sequence.
Figure 4.1 shows the five important steps to design a synchronous counter:
Figure 4.1 : Steps to design synchronous counter
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In order to complete step 3, Table 4.2 shows excitation state for each flip-flop.
Table 4.2 : Excitation table for each flip-flop
PRESENT STATE NEXT STATE SRJK D T
( ) ( + ) 0
1
0 0 0X0X 0 1
0
0 1 10 1X 1
1 0 0 1X1 0
1 1 X0X0 1
Example 1:
Develop a MOD 6 synchronous down counter by using NGT JK flip-flop.
Step 1 : Number of flip-flop & bit used
MOD 6 2 = 6
n= log 6
log 2
n = 2.58 ≈ 3
Step 2 : State transition diagram ((N – 1) to 0) 101
000 100
5
04 001 011
010
13
2
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Step 3 : Excitation table
PRESENT STATE NEXT STATE INPUT J, K
C B A C B A
101100 X 0 0 X X 1
100011 X 1 1 X 1 X
011010 0 X X 0 X 1
010001 0 X X 1 1 X
001000 0 X 0 X X 1
Step 4 : K-Map
K-Map template: ̅
X ̅ ̅ X 0
̅ ̅ 0 0
̅ ̅ X X X
̅ ̅ X X
X
̅ = 0
̅ = ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅
̅ ̅ X X
̅ X X = ̅ ̅ ( ̅ + ) + ̅ ( + ̅ )
X X
̅ 1 0 = ̅ ̅ + ̅
= ̅ ( ̅ + ) Read the position
= ̅ from Present State
and fill in the K-
Map with the input
data respectively.
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DIGITAL SYSTEM
̅ = ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅
̅ ̅ X 0 = ̅ ̅ ( ̅ + ) + ̅ ( + ̅ )
̅ X X = ̅ ̅ + ̅
X X = ̅ ( ̅ + )
̅ 1 0 = ̅
̅ = ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅
̅ ̅ X X = ̅ ̅ ( ̅ + ) + ̅ ( + ̅ )
̅ 1 0 = ̅ ̅ + ̅
X X = ̅ ( ̅ + )
̅ X X = ̅
̅ = ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ + ̅ ̅ +
̅ ̅ X X ̅ + + ̅
̅ 1 X
X X = ̅ ̅ ( ̅ + ) + ̅ ( + ̅ ) +
̅ 1 X ̅ ( ̅ + ) + ( + ̅ )
= ̅ ̅ + ̅ + ̅ +
= ̅ ( ̅ + ) + ( ̅ + )
= ̅ +
=1
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̅ = ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ + ̅ ̅ +
̅ ̅ X 1 ̅ + + ̅
̅ X 1
X X = ̅ ̅ ( ̅ + ) + ̅ ( + ̅ ) +
̅ X 1 ̅ ( ̅ + ) + ( + ̅ )
Step 5 : Logic circuit = ̅ ̅ + ̅ + ̅ +
= ̅ ( ̅ + ) + ( ̅ + )
From the K-Map; = 0 = ̅ +
=1
= ̅
= ̅ MSB
= ̅
= 1
= 1
LSB
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Example 2:
Design a counter with the irregular count sequence of 12, 5, 13, 6, 9 and 7 continuously by using PGT T
flip-flop.
Step 1 : Number of flip-flop & bit used
2 = 13
log 13
n = log 2
n = 3.7 ≈ 4
Step 2 : State transition diagram
12 1100
75
0111 0101
9 13
6 1001 1101
0110
Step 3 : Excitation table
PRESENT STATE NEXT STATE INPUT J, K
D C B A D C B A
11000101 1 0 0 1
01011101 1 0 0 0
11010110 1 0 1 1
01101001 1 1 1 1
10010111 1 1 1 0
01111100 1 0 1 1
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Step 4 : K-Map
K-Map template:
̅ ̅ ̅ ̅
̅ ̅ X X XX
̅ X
X X
̅ X XX
̅ ̅ ̅ ̅
̅ ̅ X X XX = ̅ ̅ ̅ ̅ + ̅ ̅ ̅ + ̅ ̅ + ̅ ̅ ̅ +
̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ +
̅ X 1 1 1 ̅ ̅ + ̅ + + ̅ +
̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅
1 1 XX
= ̅ ̅ ̅ ( ̅ + ) + ̅ ̅ ( + ̅) +
̅ X 1 XX ̅ ̅ ( + ̅) + ̅ ( + ̅) +
̅ ( ̅ + ) + ( + ̅) +
̅ ̅ ( ̅ + ) + ̅ ( + ̅)
= ̅ ̅ ̅ + ̅ ̅ + ̅ ̅ + ̅ +
̅ + + ̅ ̅ + ̅
= ̅ ̅ ( ̅ + ) + ̅ ( ̅ + ) +
( ̅ + ) + ̅ ( ̅ + )
= ̅ ̅ + ̅ + + ̅
= ̅ ( ̅ + ) + ( + ̅)
= ̅ +
=1
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DIGITAL SYSTEM
̅ ̅ ̅ ̅
̅ ̅ X X XX = ̅ ̅ ̅ ̅ + ̅ ̅ ̅ + ̅ ̅ + ̅ ̅ ̅ +
̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ +
̅ X 0 0 1 ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅
0 0 XX = ̅ ̅ ̅ ( ̅ + ) + ̅ ̅ ( + ̅) +
̅ ̅ ( ̅ + ) + ̅ ( + ̅) +
̅ X 1 XX ̅ ̅ ( ̅ + ) + ̅ ( + ̅)
= ̅ ̅ ̅ + ̅ ̅ + ̅ ̅ + ̅ +
̅ ̅ + ̅
= ̅ ̅ ( ̅ + ) + ̅ ( ̅ + ) +
̅ ( ̅ + )
= ̅ ̅ + ̅ + ̅
= ̅ ( ̅ + ) + ̅
= ̅ + ̅
̅ ̅ ̅ ̅
̅ ̅ X X X = ̅ ̅ + ̅ + + ̅ +
X ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ +
̅ X 0 1 1 ̅ + + ̅ ̅ + ̅
0 1 XX = ̅ ( ̅ + ) + ( + ̅) +
̅ X 1 XX ̅ ̅ ( ̅ + ) + ̅ ( + ̅) +
( ̅ + ) + ̅ ( ̅ + )
= ̅ + + ̅ ̅ + ̅ +
+ ̅
= ( ̅ + ) + ̅ ( ̅ + ) +
( + ̅)
= + ̅ +
= ( + ̅) +
= +
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DIGITAL SYSTEM
̅ ̅ ̅ ̅ = ̅ ̅ + ̅ + + ̅ +
̅ ̅ X X XX ̅ ̅ ̅ + ̅ ̅ + ̅ + ̅ ̅ +
̅ X 0 11 ̅ ̅ + ̅ + + ̅
1 1 XX
̅ X 0 XX = ̅ ( ̅ + ) + ( + ̅) +
̅ ̅ ( ̅ + ) + ̅ ( + ̅) +
Step 5 : Logic circuit ̅ ( ̅ + ) + ( + ̅)
= ̅ + + ̅ ̅ + ̅ +
̅ +
= ( ̅ + ) + ̅ ( ̅ + ) +
( ̅ + )
= + ̅ +
= ( + ̅) +
= +
From the K-Map; = 1 = +
= +
= ̅ + ̅
LSB MSB
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1. Construct a synchronous counter with sequential counting number 13, 7, 6, 12 and 4 continuously by
using NGT JK flip-flop.
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2. Design a parallel counter which has the sequence of 2, 5, 3 and 7 continuously by using PGT D flip-
flop.
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3. Draw a synchronous counter that counts the following sequence :
100, 000, 001, 101, 011 and return to 100 continuously by using PGT SR flip-flop.
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4. Design a parallel counter with the irregular binary count sequence of 1011, 1111, 0011, 0001 and
1000 continuously by using NGT T flip-flop.
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5.0 INTRODUCTION
Register is constructed using several flip-flops in such a way to store and transfer binary data
upon the clock pulse triggered which flip-flops D and JK are usually used as storage elements.
When the input data is applied to the first input terminal, the data will be stored at Q during the
edge transition of clock pulse. It is then moved to the next flip-flop when receiving the signal.
The binary data can be transferred either in serial or parallel movement. Table 5.1 differentiates
between both movements.
Table 5.1 : Serial vs parallel data movements
SERIAL PARALLEL
The operation is slow. The operation is faster.
Movement of n-bit data requires n It requires only one clock pulse to
number of clock pulses. shift all n-bit of data.
Simpler connection Complex connection.
Only one flip-flop is required to It needs n number of connection to
connect at the output terminal, Q. the output terminal, Q which is
proportional to the number of bit.
Figure 5.1 shows the main types of data movements in a shift register and their block diagrams.
Figure 5.1 : Types of shift register
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DIGITAL SYSTEM
5.1 SERIAL IN / SERIAL OUT (SISO)
It has a clock, a serial input and a serial output, which data is getting in and out in serial form.
The circuit connection of 4-bit SISO shift register is shown in Figure 5.2. It works so that during
each clock pulse, one bit is transferred through the shift register from left to right.
Figure 5.2 : SISO shift register
When the first clock triggered, the LSB will first enter the FF0 and store in .
The output in is shifted to FF1 and stored in 1 while the next bit entered FF0 during the
second clock pulse.
At the third clock pulse, the third bit will enter the FF0, as the output in 0 is now shifted to
FF1 while the output in 1 is moved to FF2 and allocated in 2.
The final bit which is MSB now entered the FF0 during the fourth clock pulse whereas the
others bit moved one step to the right of the flip-flop.
Table 5.2 elaborates the basic operation of SISO based on the circuit above. After receiving four
clock pulses, all flip-flops are now filled in with data.
Table 5.2 : Truth table of data transition
CLK DATA, D (Data out)
0 0 0 0
0 0 LSB 0 0 0
1 LSB 2nd LSB LSB 0 0
2 2nd LSB 3rd LSB 2nd LSB LSB 0
3 3rd LSB 3rd LSB 2nd LSB
4 MSB MSB LSB
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DIGITAL SYSTEM
After all, the data is accessible to read from the register bit by bit upon the clock triggered
individually at the fourth clock pulse and so on.
Example :
Draw the waveform of Figure 5.2 as the input data applied is 1001. The shift register is initially cleared.
Q0 received the data from D input
(Not yet shifted).
Q1, Q2 and Q3 will shift the data
from previous output respectively.
The diagram below shows the data
that has been read completely so that
the register is reset to 0000.
Q3 is a serial data output. Hence,
it is read sequentially from left to
right, MSB LSB (no longer
from bottom to top as usual).
144