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Assume a set of binary data 10110 is shifted to the right in the circuit given. Based on the circuit;
a) generate a truth table to show the data is completely transferred to the device.
b) sketch its timing diagram.
The initial data in the shift register is cleared.
a) Truth table
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b) Timing diagram
5.2 SERIAL IN / PARALLEL OUT (SIPO)
It has a clock and a serial input with n parallel outputs. The data enters the register bit by bit with
n clock pulses and exits in parallel form simultaneously once after all bits are stored.
The Figure 5.3 shows the circuit connection of 4-bit SIPO shift register.
Figure 5.3 : SIPO shift register
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When the first clock triggered, the LSB will first enter the FF0 and store in .
The output in is shifted to FF1 and stored in 1 while the next bit entered FF0 during the
second clock pulse.
At the third clock pulse, the third bit will enter the FF0, as the output in 0 is now shifted to
FF1 while the output in 1 is moved to FF2 and allocated in 2.
The final bit which is MSB now entered the FF0 during the fourth clock pulse whereas the
others bit moved one step to the right of the flip-flop.
As compared to SISO, the only difference in its operation is at the fourth clock pulses, all data are
ready to read concurrently. The clock is no more required to access the data.
The above steps are illustrated in Figure 5.4 by taking into account the input data is 1001. The
data 1001 is available at output lines at final clock pulse (fourth), hence the speed operation of
SIPO is similar to SISO as it required four cycles to load the data.
Figure 5.4 : Example of data movement in SIPO
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Example :
Figure 5.4 represents the movement of binary input 1001 for each clock. Assume the shift register is
initially cleared; illustrate that figure in waveform to explain the concept of SIPO.
1. A set of binary data 10100 is shifted to the right in the circuit given. Based on the circuit;
a) create a truth table to show the data transferred to the device.
b) draw its timing diagram.
Assume the initial data in the shift register contains all 0s.
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a) Truth table
b) Timing diagram
It works like SISO
unless its truth table does
not require any clock
pulse after the fifth!
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2. Sketch a 5 bit serial in / parallel out shift register circuit using JK flip-flops.
Recall how D flip-
flop is constructed
by using JK flip-
flop. (Section 3.7)
5.3 PARALLEL IN / SERIAL OUT (PISO)
It consists of a clock, three inputs which are a serial input, n parallel inputs and a shift/l̅o̅̅a̅̅d̅ input
with a serial output.
The data is loaded together into the register in parallel form, while it is retrieved from it serially.
It can be constructed in various ways by adding an inverter(s), AND gates and OR gates to the n-
numbers of flip-flops connection.
The shift/l̅o̅̅a̅̅d̅ input works as an operating controller which is used to select amongst shift or load
data at a given instant of time as illustrates in Figure 5.5.
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Figure 5.5 : PISO shift register
It operates in either load mode or shift mode. In order to load the data into the flip-flops, the
shift/̅lo̅̅a̅̅d̅ input is made LOW (0) to activate G2, G4 and G6 AND gates. Meanwhile, when the
shift/l̅o̅̅a̅̅d̅ input is HIGH (1), it is ready to move the data to the subsequent flip-flops, thus it
enables G1, G3 and G5 AND gates and disables the former gates.
At the first clock cycle, when the shift/l̅o̅̅a̅̅d̅ input is LOW (shift is 0 and load is 1 due to the
inverter there), the gates G2, G4 and G6 are enables and allowing data B, C and D to appear
in their respective gates and flip-flops (FF1, FF2 and FF3). Data A is already available in FF0
as it does not involve in the control line.
At the next clock cycle, when the shift/̅lo̅̅a̅̅d̅ input is HIGH, it triggers gates G1, G3 and G5
and inactivates the other AND gates, therefore the loading process is hold. At the same time,
it starts to shift the data from Q0 D1, Q1 D2 and Q2 D3.
When the third clock pulse is applied, (still the shift/̅lo̅̅a̅̅d̅ input is HIGH), the process of
shifting keeps ongoing from one flip-flop to another.
At the fourth clock cycle, the MSB will appear at Q3 where the entire bits of data are now
readable as the serial output.
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Table 5.3 interprets the basic operation of PISO based on the Figure 5.5 above. At the second
clock pulse, when the control line (shift/̅lo̅̅a̅̅d̅) is HIGH, there is no more data loading into the
flip-flop.
Table 5.3 : Truth table of PISO data transition
CLK SHIFT/̅ ̅ ̅ ̅̅ ̅ ̅ ̅ (Data out)
0 0
0 0 A (LSB) B 00
1 0 0 A C D (MSB)
2 1 0 0 BC
3 1 0 0 AB
4 1 0A
Example :
Based on Figure 5.5, show the retrieval data process of 1011 at Q3 in waveform.
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Sketch the output waveform of PISO data transition process for 10011 by assuming the NGT shift
register initially contains all 0s which is interpreted from the corresponding truth table.
a) Truth table
b) Output waveform
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5.4 PARALLEL IN / PARALLEL OUT (PIPO)
As similar to SISO shift register concept, it comprises of a clock, n parallel inputs and outputs. It
loads and reads data synchronously at a single clock pulse.
Figure 5.6 shows the logic diagram for 4-bit PIPO register.
Figure 5.6 : PIPO register
Once the register is clocked, all the data A, B, C and D entered their input pins D0, D1, D2 and
D3 then, they are read at their respective output pins within the common clock pulse. Therefore,
this register emphasizes that it needs only a clock pulse to store and recover all the bits.
While both data loading and unloading occur at the same time, it just a temporary storage device
and it is called as PIPO register due to it does not shift any bits as shown in Table 5.4.
Table 5.4 : Data entered and read process
CLK (Data out) (Data out) (Data out) (Data out)
0
1 0000
A (LSB) B C D (MSB)
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Example :
Present the Table 4.4 in timing diagram form for input data 1010. The register is initially cleared.
Construct a logic diagram of PIPO register to load and unload data 110 and draw its square waveform
to show the process. The register contains all 0s at first.
a) Logic diagram
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b) Output waveform
5.5 SHIFT REGISTER AS ARITHMETIC CIRCUITS
In addition to normal data transfer, the shift registers can actually be used as digital arithmetic
circuits to perform operations such as multiplication and division; both in the operation by - 2 .
5.5.1 MULTIPLIER CIRCUITS
The data is shifted to the left to carry out multiplication process with the next incoming
input is always 0. For example, the entering four bits data register is 0011. When the clock
is applied, the data started to move left gradually as in Table 5.5.
Table 5.5 : Multiplied - by - 2 process
OPERATION BINARY DATA DECIMAL
MSB LSB DATA
Initial 0011 3
1st Operation 0 1 1 0 6 (3 × 21) Shift 1 bit data
Shift 2 bits data
2nd Operation 1 1 0 0 12 (3 × 22)
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Figure 5.7 illustrates the circuit connection for shift left register which can be used to
perform the above operation. The LSB is moved one place to the left for each clock. As a
result, the MSB is shifted to the place of LSB.
Figure 5.7 : SISO shift left register
5.5.2 DIVIDER CIRCUITS
The division process is implemented by shifting data to the right with the next incoming input
is always 0. For example, the entering four bits data register is 1010. When the clock is
applied, the data started to transfer to the right bit by bit as in Table 5.6.
Table 5.6 : Divided - by - 2 process
OPERATION BINARY DATA DECIMAL
MSB LSB DATA
Initial 1010 10
1st Operation 0 1 0 1 5 (10 ÷ 21) Shift 1 bit data
Shift 2 bits data
2nd Operation 0 0 1 0 2.5 (10 ÷ 22)
When CLK 3 is applied, it gives
0010 which equals to 2 in decimal
number. The 0.5 is truncated as it is
a whole number.
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The operation and logic diagram are similar as in Figure 5.2 which the MSB is shifted first
one place to the right. Hence, the LSB is shifted to the place of MSB.
1. A 7-bit register contains initial data 1101010. Determine the contents of each shift after shifted four
times to the right.
2. The data is 101000 after shifted to the left three times. What is the initial data for this 6-bit shift
register? Perform the operation by using both modes of shifting.
a) Shift left b) Shift right
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3. An arithmetic circuit is one of the applications of shift register. With the aid of suitable diagram,
briefly explain the operation of shift left register. Then, show the arithmetic operation for the number
30 in 4 clocks triggered.
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5.6 SHIFT REGISTER COUNTERS
A shift register counter is classified as a counter which basically a type of serial shift registers
with the output being fed back to the input to count a specific unique sequence.
Ring Counter
It is a circuit connection with the last serial normal output, is connected back to the first
serial input, 0 as shown in Figure 5.8.
Figure 5.8 : 4-bit ring counter
In order to power-up, only the first flip-flop is connecting to preset (HIGH state) whereas
the others are cleared (LOW state) due to unpredictable starting operation. This can be
done before the clock pulses are applied.
The sequence for the above diagram recorded in Table 5.7 shows the counter states when
the negative clock pulses are applied.
Table 5.7 : Sequence table of a 4-bit ring counter
CLK
0 0
0 1 (LSB) 0 00
1 0 1 0 0 (MSB)
2 0 0 00
3 0 0 10
4 1 0 01
5 00
6 0 1 00
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As it is a circulating shift register which circulate the input bit within the clock pulses, then, it
is called a ring counter.
It can be constructed for n modulus counter which uses n number of flip-flop. Therefore, for
the same MOD numbers, it requires more flip-flops than a binary counter.
Regardless of its lengthy circuitry of flip-flops arrangement, it is self-decoding without the
use of decoding gates to determine the states in the counter.
Johnson Counter
It also known as twisted ring counter due to the last serial inverted output, ̅̅ ̅ ̅ is fed back to
the first serial input, 0 as shown in Figure 5.9.
In contrast to the ring counter, the MOD number of Johnson counter is always equal to twice
number of flip flops.
Let say the flip-flop, n = 4;
MOD = 2n = 2(4)
∴ MOD 8
Figure 5.9 : 4-bit Johnson counter
When the positive clocks triggered, the data in Q0 Q1, Q1 Q2, Q2 Q3 and the
inverse data in Q3, ̅ ̅ ̅3̅ regulates back into Q0.
Table 5.8 shows the state sequence of the above circuit connection for each positive clock
pulse.
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Table 5.8 : Sequence table of a 4-bit Johnson counter
CLK
0 0
0 1 (LSB) 0 00
1 1 1 0 0 (MSB)
2 1 1 00
3 1 1 10
4 0 1 11
5 0 11
6 0 0 11
7 0 01
8 0 00
0
Despite of its simpler flip-flops connection, it requires decoding gates circuitry for each
count.
Nonetheless, both shift register counters are varying to a binary counter as for the number of flip-
flops, they carried out different MOD numbers like given Table 5.9. It means, to produce the
same MOD numbers for instance MOD 16, a ring counter requires 16 flip-flops connection, while
a Johnson counter needs 8 flip-flops and a binary counter should have only 4 flip-flops.
Number of flip-flop RING JOHNSON BINARY
MOD number COUNTER COUNTER COUNTER
4 4 4
4 8 16
Table 5.9 : Comparison between shift register counters and a binary counter
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1. The shift register counters can be categorized into two types. Differentiate these two types.
2. Generate the waveforms to illustrate the data transfer that are recorded in Table 4.7 and Table 4.8
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3. Draw a positive edge triggered 3-bit ring counter circuit which uses D flip-flops. From the diagram,
determine its truth table and sketch the timing diagram for five clock cycles.
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5.7 APPLICATIONS OF SHIFT REGISTER
Shift register works as a memory element in most digital electronic devices. Figure 5.10 shows
various uses of the shift registers in communication technologies hence; they benefit human
beings.
Figure 5.10 : Some applications of shift registers
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6.0 INTRODUCTION
In the era of globalization, many electronic devices are widely used in different areas and fields.
They compromise with a lot of instruments which can be categorized into analog and digital
system.
It is undeniable that the digital world is sophisticated growing from time to time yet; most
physical variables such as temperature, sound, position, light intensity and speed are basically still
in analog world. The information and signals from them require interfaces to be translated from
the physical forms into the digital world of electronics and need to convert back into the analog
forms like voltage or current for us to use them.
Analog data may be defined as a continuous function which its exact value is substantial. For
instance, a measured displacement of 4.3m may represent a specific pressure, thus, the different
measurement of displacement will produce another value of pressure. In contrast, digital data may
consist of discrete or discontinuous pulse. It carries specified possibilities either HIGH or LOW,
true or false, 1 or 0 and so forth. For the same measured displacement of 4.3m, let say it gives
logic 1. It means, the other displacements result in logic 0.
Therefore, the analog-to-digital data converters (ADC) are vital so that the signals can be
processed in the digital system and they need digital-to-analog data converters (DAC) for the
control systems as in Figure 6.1. It illustrates the five elements needed to control analog signals in
both interface devices.
Figure 6.1 : Block diagram of analog-digital interface
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There are various types of converters used to complete the data acquisition and control system
which are listed in Figure 6.2. Basically, the concept of DAC is simpler than ADC. For this
reason, several ADC methods utilize the processes of DAC methods.
Figure 6.2 : Types of DAC and ADC
Based on your knowledge, elaborate the functions of each device involved in analog input physical
signal processing as in Figure 6.1
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6.1 DIGITAL-TO-ANALOG CONVERSION (DAC)
A DAC processes a digital signal (binary number) and converts it into a corresponding analog
signal in terms of voltage or current.
The basic symbol of a DAC is shown in Figure 6. 3. It consists of an input for a voltage reference,
, the digital inputs and an analog output voltage. For n numbers of bits, they represent the
total of 2 analog outputs voltage.
Let say the digital inputs, n = 4;
Number of analog outputs = 2
∴ 2 = 24 = 16
Figure 6.3 : Symbol of a DAC
Analog Output
As for 4-bit digital input, it produces 16 output voltages as in Table 6.1. In this case, the
proportionality factor, K is assumed as 1. K is the constant value for a given DAC and it
depends on the reference voltage.
Once the value of K is varied, the analog output voltages also changed. The value for
can be determined for any digital inputs.
Analog output = K × Digital input
Let say, K = 1,
Digital inputs = 10012 = 910;
∴ = 1 × 9 = 9V
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DIGITAL SYSTEM
Table 6.1 : Output voltages table
D Digital Inputs A
(MSB) (LSB) (Volts)
CB
0 0 0
0 00 1 1
0 00 0 2
0 01 1 3
0 01 0 4
0 10 1 5
0 10 0 6
0 11 1 7
1 11 0 8
1 00 1 9
1 00 0 10
1 01 1 11
1 01 0 12
1 10 1 13
1 10 0 14
1 11 1 15
11
Example :
For a 5-bit DAC, the digital input of 10010 produces an output current of 12.6mA. Determine the analog
output for a digital input 11001.
12.6m = K × 18 18 is decimal
number of digital
12.6
input 10010.
K = 18 = 0.7mA
∴ 110012 = 2510
= 0.7mA × 25
= 17.5mA
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Weighted Inputs
All the digital inputs are weighted according to their position in binary number. It is weighted
based on its output voltage. For example, in Table 6.1, the weight for A is 1V as it carries
data 0001 while the weight for C is 4V due to input data 0100. For digital input 1110, the
weight is 14V.
Resolution (Step size)
The proportionality factor, K also can be considered as the resolution (step size). It is defined
as the smallest changes achieved in the analog output due to the changes in digital input.
The resolution or step size is usually referred to the weight of LSB as it is the incremental step
in a set of analog outputs as in Figure 6.4 (the data is taking from Table 6.1). in short, it the
changes in one step to next step.
15V
LSB 5V
0V 4V
3V
2V
}1V K
} K = Resolution = Step size = 1V (assumed)
Figure 6.4 : Concept of step size
171
Another way to interpret the value of K is : DIGITAL SYSTEM
K= is the analog
(2 −1) full-scale output ; n
is the number of bit.
Percentage Resolution
It is more practical to express the resolution as a percentage which is given by :
% resolution = × 100% % resolution = 1 × 100%
Total number of
step = 2 ̶−1
Example :
For a 5-bit DAC, the digital input of 10010 produces an output current of 12.6mA. Determine the full
scale output voltage and the percentage resolution for the converter.
Full scale output voltage Method 2
Method 1
12.6m = K × 18 12.6m = K × 18
12.6 12.6
K = 18 = 0.7mA K = 18 = 0.7mA
Full scale output = digital input is 111112 = 3110 K= ;
(2 −1)
= 0.7mA × 31
= 21.7mA = K × (2 − 1)
= 0.7mA × (25 − 1) = 21.7mA
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DIGITAL SYSTEM
Percentage resolution Method 2
Method 1
% resolution = × 100% % resolution = 1 × 100%
% resolution = 0.7 × 100% % resolution = 1 × 100%
21.7 (2 −1)
= 3.23%
% resolution = 1 × 100%
31
= 3.23%
1. Find the total number of output voltages for 3-bit DAC and build the output voltage table with the
resolution 0.25mV.
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2. Calculate the largest value of the output voltage from a 4-bit DAC that produces 6.5mA for a digital
input of 1011.
3. A 6-bit DAC has an output voltage 4.3V of a digital input 101011.
a) Compute the resolution and full scale voltage output of the DAC.
b) Calculate its percentage resolution.
c) Determine the weight of its MSB.
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6.1.1 BINARY WEIGHTED RESISTOR
It consists of parallel resistors, a feedback resistor, and summing amplifier which produces the
weighted sum of the input voltage.
Figure 6.5 shows the basic circuit connection of a 4-bit weighted binary resistor DAC. The
weighted resistors are determined by the value of (2 −1)R, where n counts started with 1 until it
reaches the number of bits.
Figure 6.5 : A basic weighted binary resistor circuit
The MSB input resistor value is always the lowest resistor value which is 1R whereas the LSB
input resistor value will be (2 −1)R. n refers to the number of bit or in the other word; it is the
highest value of resistor depending on its number of bit.
The output voltage, in Figure 6.5 can be obtained by :
As Ohm’s Law, V = IR
I = ;
3 = 2 = 1 = 0 =
2 4 8
= 3 + 2 + 1 + 0
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( 1( 4 ) DIGITAL SYSTEM
2 b is the input weight or
+ + += 3( ) 2 ) 0( 8 ) in other word; the bit
value where 3 is MSB
= ( 3 + 2 + 1 + 0)
2 4 and 0 is LSB.
1 8
= (2 03 + 2 + 1 + 2 30)
21 22
∴ = ̶− .
Negative sign is = − [ (2 03 + 2 + 1 + 2 03)] .
present because of 21 22
the polarity- = − (2 03 + 2 + 1 + 2 30)
inverting amplifier. 21 22
For n-bits;
= − ( 2 0 + −1 + −2 +⋯+ 2 0 )
21 22
Example :
Diagram below shows a circuit for 4-bit binary weighted resistor DAC. If is 10V, find the values of:
The MSB now is at the
bottom arrangement
while LSB is at the top!
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DIGITAL SYSTEM
a) if data input is 0110
= − (2 03 + 2 + 1 + 2 30)
21 22
= − 10 (10 ) (200 + 1 + 1 + 203) The value for R
25 21 22 is belongs to
MSB resistor.
value.
= − 4 (3)
4
= − 3V
b) The converter step size
2nd method
= − (2 30 + 2 + 1 + 2 03)
21 22 K = (2 −1)
= − 10 (10 ) (200 + 0 + 0 + 213) is when data input equals to 1111
25 21 22
= − 4 (1) = − 10 (10 ) (210 + 1 + 1 + 213)
21 22
8 25
= − 0.5V Why the = − 4 (15)
input value is
8
0001?
1st method = − 7.5V
− 7.5
K = (24−1) = − 0.5V
c) The percentage resolution
% resolution = 1 × 100%
(2 −1)
= 1 × 100% = 6.67%
(24−1)
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DIGITAL SYSTEM
1. By assuming the input low is 0V and high is 5V, compute the weight of each input bit of figure below.
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2. A binary weighted DAC circuit has the components of :
5 = 80kΩ where it is the value for LSB
= 5kΩ
= 5V
a) Sketch and label the circuit.
b) Calculate the value of 1, 2, 3 and 4.
c) Determine the output voltage, for binary input 11001.
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DIGITAL SYSTEM
3. Figure below shows the circuit of 4-bit binary weighted resistor DAC. The input has the values
between 0V and 10V.
a) Calculate the output voltage, if the binary input is
i. 0011
ii. 0110
iii. 1011
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DIGITAL SYSTEM
b) Construct the output voltage table for each input
c) Find the percentage resolution
d) Determine the full-scale output if the value for is reduced to 7.5kΩ
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6.1.2 R-2R LADDER
As most of the components are similar to binary weighted resistor, it consists of series and
parallel resistors, a feedback resistor, and summing amplifier.
However, the construction is a solution to overcome the limitations in the former type of DAC. In
previous section, it works in theory but it is practically improper as it has large differences in
resistor values between LSB and MSB.
Therefore, R-2R ladder is created in order to satisfy the requirement of having close values of
resistor as illustrates in Figure 6.6. It is the basic connection of a 4-bit R-2R ladder network
which uses only two resistor values, R and 2R.
Figure 6.6 : A basic 4-bit R-2R ladder circuit
The output voltage, in Figure 6.6 can be obtained by :
As I = ;
3 = 2 = 3 = 1 = 2 = 0 = 1 =
2 2 4 2 8 2 16
= 3 + 2 + 1 + 0
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DIGITAL SYSTEM
1( 8 )
+ + += 3( 2 ) 0( 1 6 )
2 ( )
4
= ( 3 + 2 + 1 + 0)
2 1 2 4 8
= (2 30 + 2 + 1 + 2 30)
2 21 22
∴ = ̶− .
= − [ (2 03 + 2 + 1 + 2 03)] .
2 21 22
= − (2 03 + 2 + 1 + 2 03) The only difference in
2 21 22 formulae between the
binary weighted and R-2R
ladder is at the value of R.
For n-bits;
= − ( 2 0 + −1 + −2 +⋯+ 2 0 )
2 21 22
Example :
Calculate the output voltage, of the R-2R ladder circuit for input value 1010. Given that; = 15V,
= 5kΩ and R = 15kΩ.
= − (2 03 + 2 + 1 + 2 30)
2 21 22
= − 15 (5 ) (210 + 0 + 1 + 203)
2(15 ) 21 22
= − 2.5 (5)
4
= − 3.125V
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DIGITAL SYSTEM
1. A 5-bit R-2R ladder network has the parallel resistors of 10kΩ and the feedback resistor of 15kΩ. If
the = 5V, determine :
a) The value of series resistors.
b) The full-scale output voltage.
c) The resolution of the converter.
d) The percentage resolution of the converter.
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DIGITAL SYSTEM
2. A 4-bit R-2R ladder DAC has 25kΩ series resistors. Given that; the reference voltage. is 15V
and the binary input 1001.
a) Draw the circuit configuration of the DAC.
b) Determine the total current, of the circuit.
c) Calculate the output voltage, for the given binary input.
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DIGITAL SYSTEM
d) Find the step size of the converter and build its output voltage table.
6.2 ANALOG-TO-DIGITAL CONVERSION (ADC)
An ADC inputs an analog signal such as voltage or current and converts it into a digital signal
(binary number) as represented in Figure 6.7. Some ADC employs a DAC as part of their
circuitry.
Figure 6.7 : Basic symbol of an ADC
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DIGITAL SYSTEM
It requires two steps of data processing to obtain the digital data as in Figure 6.8 which are:
i. Sampling and holding
ii. Quantizing and encoding
Figure 6.8 : Basic ADC conversion process
Sample and hold (S/H) circuit is used to sample an analog signal at regular discrete interval of
time and to hold on its last sampled value until the input signal is sampled again which the
process shown in Figure 6.9.
SHSH
Figure 6.9 : Overview of S/H process
Quantization takes the sampled analog value and converts it to the nearest binary value. Then, the
encoding operation reduces the result of the conversion to a binary code acceptable to be
processed by a digital system.
There are two ways to best improve the accuracy of A-D conversion:
By increasing the resolution which improves the accuracy in measuring the amplitude of
the analog signal.
By increasing the sampling rate which increases the maximum frequency that can be
measured.
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DIGITAL SYSTEM
6.2.1 DIGITAL RAMP
It is also known as the stair-step ramp or simply counter A/D converter. Figure 6.10 shows the
circuit diagram of a digital ramp DAC. It uses a binary counter as a register to drive a DAC.
Figure 6.10 : A digital ramp ADC circuit connection
The start pulse resets the counter and blocks the clock to avoid the data enter/shift. At the
end of the start pulse, the counter starts.
The counter increases the output voltage of the DAC, until it reaches the input voltage,
. The output of DAC is connected to another terminal of the comparator. The
comparator output will be HIGH if the > .
When ≥ , the comparator goes LOW and stops the count. It then holds the digital
value until the next start pulse triggers a new conversion.
With this method of conversion, it is one of the simplest ADC to use but it has several limitations.
The output of the DAC will start all over again from zero at the beginning of each count cycle to
the desired value makes relatively slow sampling of the analog signal. Hence, it is going to take
longer to produce a correct output for higher voltages than for lower voltages as illustrates in
Figure 6.11.
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DIGITAL SYSTEM
Figure 6.11 : Output produced of a digital ramp ADC
Example :
Assume the following values for a 5-bit input digital ramp ADC:
Clock frequency = 10MHz
DAC full-scale output voltage = 2.5V
a) Determine the digital equivalent obtained for = 0.78V
b) Compute the conversion time
c) Find the percentage resolution of this converter
a) The digital equivalent obtained for = 0.78V.
Step 1 : Number of converter step size
Number of step = (2 − 1);
K = (2 −1)
∴ (2 − 1) =
2.5
K = (25−1) = 0.08V Assume = 0.78V at the
desired .
Step 2 : Number of step at = 0.78V
Number of step = = 0.78 = 9.75 ≈ 10 steps
0.08
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DIGITAL SYSTEM
Step 3 : Binary equivalent of 10 steps (Depending on the answer in Step 2)
Convert to binary 5 bit!
10
01010
b) The conversion time.
11
T = = 10 = 0.1µs
At 10 steps, the conversion time, T = 0.1µs × 10 = 1µs
c) The percentage resolution.
% resolution = 1 × 100%
(25−1)
= 3.23%
1. A 7-bit digital ramp ADC has the full-scale output 3.56V and clock frequency 7MHz. Based on
Figure 6.10, the is 0.1mV. Determine :
a) The digital equivalent obtained for = 1.5V.
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b) The conversion time.
c) The percentage resolution of the converter.
2. An 8-bit digital ramp converter has a resolution of 110mV and a clock frequency of 6.5MHz. Find out :
a) The full-scale output voltage.
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b) The digital equivalent obtained for = 3.56V.
c) The conversion time of the converter.
d) The maximum conversion time.
6.2.2 SUCCESSIVE APPROXIMATION (SAC)
A successive approximation ADC is used to overcome the shortcomings of a digital ramp ADC.
Even though it has a complex circuitry than the latter, the shorter conversion time contributes to
its reliability and high speed. The conversion time is constant and independent on the value of
analog input signal.
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While the digital ramp ADC needs to search all the range of input values in binary sequence, the
successive approximation ADC compares all values of bits from the MSB until the LSB in a
serial format. Thus, for n bit data, it requires only n clock cycles to compute the digital output.
Figure 6.12 shows the arrangement of a SAC. It uses a successive approximation register (SAR)
instead of a counter like in a digital ramp ADC.
Figure 6.12 : A successive approximation ADC circuit connection
The control logic is initially cleared. The first data to compare is MSB where the MSB is
set to 1 whereas the remaining bits are 0 in the SAR.
The register provides the input to the DAC to obtain the analog equivalent data, which
is connected to another terminal of the comparator. It is compared with the analog input
voltage . The comparator output will be HIGH if the < and vice versa.
The signal from the comparator will tell the control logic the setting either to retain the
MSB at 1 or to reset it to 0.
Then, the next bit enters the control logic at value 1. It does the same process by bringing
the correct previous data together and the lower bits are set as 0.
The iteration processes continues till all the bits up to LSB are scanned and the digital
output of the SAR is equivalent to .
Despite of some benefits, its accuracy in data conversion is less accurate than the former ADC.
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Example 1:
An analog voltage = 6.3V is converted by a 6-bit successive approximation ADC. Show its
conversion process and find the digital value of . The voltage reference, range is 0 ̶ 10V.
10 5V < 6.3V 1 Data 1=
7.25V > 6.3V 0 21
2 = 5V 6.25V < 6.3V 1
6.88V > 6.3V 0 Data 2 = Data 1 +
10 6.56V > 6.3V 0 22
6.41V > 6.3V 0
5V + 4 = 7.25V Data 3 = Data 1 +
23
10
Data 4 = Data 3 +
5V + 8 = 6.25V 24
10 Data 5 = Data 3 +
25
6.25V + 16 = 6.88V
Data 6 = Data 3 +
10 26
6.25V + 32 = 6.56V
10
6.25V + 64 = 6.41V
The data added in front is
taken from the latest digital
value which is equal to 1!
= FS = 10V
7.25V 6.88V 6.56V 6.41V
6.25V
6.3V
5V
10 1 0 00
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∴ The digital value for = 101000