Section 2.10 Binary Codes for Decimal Numbers 45
Ta b l e 2 - 9 Decimal codes.
DO NOT COPYDecimal digit BCD (8421) 2421
Excess-3 Biquinary 1-out-of-10
0 0000 0000 0011 0100001 1000000000
DO NOT COPY3 0001 0100
1 0001 0100010 0100000000
2 0010 0010 0101 0100100 0010000000
0011 0011 0110 0101000 0001000000
4 0100 0100 0111 0110000 0000100000
DO NOT COPY750101 1011 1000
1000001 0000010000
6 0110 1100 1001 1000010 0000001000
0111 1101 1010 1000100 0000000100
8 1000 1110 1011 1001000 0000000010
9 1001 1111 1100 1010000 0000000001
DO NOT COPY1010
Unused code words
0101 0000 0000000 0000000000
1011 0110 0001 0000001 0000000011
11000111 0010 0000010 0000000101
11011000 1101 0000011 0000000110
1001 1110 0000101 0000000111
DO NOT COPY1110
1111 1010 1111 ⋅⋅⋅ ⋅⋅⋅
tions, 0000 through 1001. The code words 1010 through 1111 are not used.
DO NOT COPYConversions between BCD and decimal representations are trivial, a direct sub-
stitution of four bits for each decimal digit. Some computer programs place two
BCD digits in one 8-bit byte in packed-BCD representation; thus, one byte may
represent the values from 0 to 99 as opposed to 0 to 255 for a normal unsigned 8-
bit binary number. BCD numbers with any desired number of digits may be
DO NOT COPYobtained by using one byte for each two digits.
packed-BCD
representation
As with binary numbers, there are many possible representations of nega-
DO NOT COPYtive BCD numbers. Signed BCD numbers have one extra digit position for the
BINOMIAL The number of different ways to choose m items from a set of n items is given by
-------------n---!--------------
m! ⋅ (n – m!)
COEFFICIENTS NOT COPYdaebciinmoamlicaoldceo,etfhfiecrieenatr,eden11o06teddifmfnere,nwt whoasyesvalueis.Fora4-bit
code
DO to choose 10 out of 16 4-bit
words, and 10! ways to assign each different choice to the 10 digits. So there are
-----1---6---!----- ⋅ 10! or 29,059,430,400 different 4-bit decimal codes.
10! ⋅ 6!
Copyright © 1999 by John F. Wakerly Copying Prohibited
46 Chapter 2 Number Systems and Codes
sign. Both the signed-magnitude and 10’s-complement representations are pop-
ular. In signed-magnitude BCD, the encoding of the sign bit string is arbitrary; in
DO NOT COPY10’s-complement, 0000 indicates plus and 1001 indicates minus.
BCD addition Addition of BCD digits is similar to adding 4-bit unsigned binary numbers,
except that a correction must be made if a result exceeds 1001. The result is cor-
rected by adding 6; examples are shown below:
5 0101
DO NOT COPY+ 9 + 1001
4 0100
+ 5 + 0101
14 9 1001
DO NOT COPY10+4
1110
+ 0110 — correction
1 0100
8 1000 9 1001
NOT COPY+ 8
−16
DO + 1000 + 9 + 1001
1 0000 18 1 0010
+ 0110 — correction + 0110 — correction
10+6 1 0110 10+8 1 1000
Notice that the addition of two BCD digits produces a carry into the next digit
position if either the initial binary addition or the correction factor addition pro-
duces a carry. Many computers perform packed-BCD arithmetic using special
DO NOT COPYinstructions that handle the carry correction automatically.
weighted code Binary-coded decimal is a weighted code because each decimal digit can
DO NOT COPY8421code
be obtained from its code word by assigning a fixed weight to each code-word
bit. The weights for the BCD bits are 8, 4, 2, and 1, and for this reason the code
is sometimes called the 8421 code. Another set of weights results in the 2421
2421 code code shown in Table 2-9. This code has the advantage that it is self-
self-complementing complementing, that is, the code word for the 9s’ complement of any digit may
code
DO NOT COPYexcess-3code
be obtained by complementing the individual bits of the digit’s code word.
Another self-complementing code shown in Table 2-9 is the excess-3 code.
Although this code is not weighted, it has an arithmetic relationship with the
BCD code—the code word for each decimal digit is the corresponding BCD
code word plus 00112. Because the code words follow a standard binary count-
ing sequence, standard binary counters can easily be made to count in excess-3
code, as we’ll show in Figure 8-37 on page 600.
Decimal codes can have more than four bits; for example, the biquinary
DO NOT COPYbiquinarycode
code in Table 2-9 uses seven. The first two bits in a code word indicate whether
the number is in the range 0–4 or 5–9, and the last five bits indicate which of the
five numbers in the selected range is represented.
One potential advantage of using more than the minimum number of bits in
DO NOT COPYa code is an error-detecting property. In the biquinary code, if any one bit in a
code word is accidentally changed to the opposite value, the resulting code word
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 2.11 Gray Code 47
does not represent a decimal digit and can therefore be flagged as an error. Out
of 128 possible 7-bit code words, only 10 are valid and recognized as decimal
DO NOT COPYdigits; the rest can be flagged as errors if they appear.
A 1-out-of-10 code such as the one shown in the last column of Table 2-9 is 1-out-of-10 code
the sparsest encoding for decimal digits, using 10 out of 1024 possible 10-bit
code words.
DO NOT COPY2.11 Gray Code
In electromechanical applications of digital systems—such as machine tools,
automotive braking systems, and copiers—it is sometimes necessary for an
input sensor to produce a digital value that indicates a mechanical position. For
DO NOT COPYexample, Figure 2-5 is a conceptual sketch of an encoding disk and a set of con-
tacts that produce one of eight 3-bit binary-coded values depending on the
rotational position of the disk. The dark areas of the disk are connected to a sig-
nal source corresponding to logic 1, and the light areas are unconnected, which
the contacts interpret as logic 0.
DO NOT COPYThe encoder in Figure 2-5 has a problem when the disk is positioned at cer-
tain boundaries between the regions. For example, consider the boundary
between the 001 and 010 regions of the disk; two of the encoded bits change
here. What value will the encoder produce if the disk is positioned right on the
DO NOT COPYtheoretical boundary? Since we’re on the border, both 001 and 010 are accept-
able. However, because the mechanical assembly is not perfect, the two right-
hand contacts may both touch a “1” region, giving an incorrect reading of 011.
Likewise, a reading of 000 is possible. In general, this sort of problem can occur
at any boundary where more than one bit changes. The worst problems occur
DO NOT COPYwhen all three bits are changing, as at the 000–111 and 011–100 boundaries.
The encoding-disk problem can be solved by devising a digital code in
which only one bit changes between each pair of successive code words. Such a
DO NOT COPYcode is called a Gray code; a 3-bit Gray code is listed in Table 2-10. We’ve rede- Gray code
111 000 Figure 2-5
A mechanical encoding
disk using a 3-bit binary
DO NOT COPY110 001 code.
001
DO NOT COPY101 010
100 011
Copyright © 1999 by John F. Wakerly Copying Prohibited
48 Chapter 2 Number Systems and Codes
DO Ta ble 2 -10 Decimal Binary Gray
DO A comparison of 3-bitnumbercode code
binary code and
0 000 000
NOT COPYGraycode.
1 001 001
NOT COPY2 010 011
3 011 010
4 100 110
5 101 111
DO NOT COPY6 110 101
7 111 100
signed the encoding disk using this code as shown in Figure 2-6. Only one bit of
the new disk changes at each border, so borderline readings give us a value on
one side or the other of the border.
There are two convenient ways to construct a Gray code with any desired
DO NOT COPYnumber of bits. The first method is based on the fact that Gray code is a reflected
reflected code code; it can be defined (and constructed) recursively using the following rules:
1. A 1-bit Gray code has two code words, 0 and 1.
2. The first 2n code words of an n+1-bit Gray code equal the code words of
DO NOT COPYan n-bit Gray code, written in order with a leading 0 appended.
3. The last 2n code words of an n+1-bit Gray code equal the code words of an
n-bit Gray code, but written in reverse order with a leading 1 appended.
If we draw a line between rows 3 and 4 of Table 2-10, we can see that rules 2
DO NOT COPYand 3 are true for the 3-bit Gray code. Of course, to construct an n-bit Gray code
for an arbitrary value of n with this method, we must also construct a Gray code
DO NOT COPYof each length smaller than n.
Figure 2-6 100 000
A mechanical encoding101 COPY001
disk using a 3-bit Gray
DO NOTcode.
001
DO NOT COPY111 011
110 010
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *2.12 Character Codes 49
The second method allows us to derive an n-bit Gray-code code word
directly from the corresponding n-bit binary code word:
DO NOT COPY1. The bits of an n-bit binary or Gray-code code word are numbered from
right to left, from 0 to n − 1.
2. Bit i of a Gray-code code word is 0 if bits i and i + 1 of the corresponding
binary code word are the same, else bit i is 1. (When i + 1 = n, bit n of the
DO NOT COPYbinary code word is considered to be 0.)
Again, inspection of Table 2-10 shows that this is true for the 3-bit Gray code.
*2.12 Character Codes
DO NOT COPYAs we showed in the preceding section, a string of bits need not represent a num-
ber, and in fact most of the information processed by computers is nonnumeric.
The most common type of nonnumeric data is text, strings of characters from text
some character set. Each character is represented in the computer by a bit string
DO NOT COPYaccording to an established convention.
The most commonly used character code is ASCII (pronounced ASS key), ASCII
the American Standard Code for Information Interchange. ASCII represents
each character with a 7-bit string, yielding a total of 128 different characters
shown in Table 2-11. The code contains the uppercase and lowercase alphabet,
DO NOT COPYnumerals, punctuation, and various nonprinting control characters. Thus, the
text string “Yeccch!” is represented by a rather innocuous-looking list of seven
7-bit numbers:
DO NOT COPY1011001 1100101 1100011 1100011 1100011 1101000 0100001
2.13 Codes for Actions, Conditions, and States
The codes that we’ve described so far are generally used to represent things that
we would probably consider to be “data”—things like numbers, positions, and
characters. Programmers know that dozens of different data types can be used in
DO NOT COPYa single computer program.
In digital system design, we often encounter nondata applications where a
string of bits must be used to control an action, to flag a condition, or to represent
the current state of the hardware. Probably the most commonly used type of code
DO NOT COPYfor such an application is a simple binary code. If there are n different actions,
conditions, or states, we can represent them with a b-bit binary code with
b = log2 n bits. (The brackets denote the ceiling function—the smallest
integer greater than or equal to the bracketed quantity. Thus, b is the smallest ceiling function
integer such that 2b ≥ n.)
DO NOT COPYFor example, consider a simple traffic-light controller. The signals at the
intersection of a north-south (N-S) and an east-west (E-W) street might be in any
Copyright © 1999 by John F. Wakerly Copying Prohibited
50 Chapter 2 Number Systems and Codes
Ta b l e 2 - 1 1 American Standard Code for Information Interchange (ASCII), Standard No.
DO NOT COPYX3.4-1968 of the American National Standards Institute.
b6b5b4 (column)
DO NOT COPY0000
b3b2b1b0 Row 000 001 010 011 100 101 110 111
(hex) 0 1 2 3456 7
0 NUL DLE SP 0 @P‘ p
0001 1 SOH DC1 ! 1AQa q
0010 2 STX DC2
0011 3 ETX DC3
0100 4 EOT DC4
5 ENQ NAK
DO NOT COPY0101
" 2BRb r
# 3CSc s
$ 4DTd t
% 5EUe u
0110 6 ACK SYN & 6FVf v
0111
1000
DO NOT COPY1001
7 BEL ETB ’ 7GWg w
8 BS CAN ( 8HXh x
9 HT EM ) 9IYi y
1010 A LF SUB * :JZj z
1011 B VT ESC + ;K[k {
1100
1101 C
D
DO NOT COPY1110E
FF FS , <L\l |
CR GS – =M]m }
SO RS . >N^n ~
1111 F SI US / ? O _ o DEL
NUL
DO NOT COPYSOH
Null Control codes
Start of heading
DLE Data link escape
DC1 Device control 1
STX Start of text DC2 Device control 2
Device control 3
Device control 4
Negative acknowledge
Synchronize
ETX DC3
EOT DC4
ENQ NAK
SYN
DO NOT COPYACK
End of text
End of transmission
Enquiry
Acknowledge
BEL Bell ETB End transmitted block
BS Backspace CAN
HT Horizontal tab EM
SUB
DO NOT COPYLF Linefeed
Cancel
End of medium
Substitute
VT Vertical tab ESC Escape
FF Form feed FS File separator
CR Carriage return
SO Shift out
DO NOT COPYSI Shiftin
GS Group separator
RS Record separator
US Unit separator
SP Space DEL Delete or rubout
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 2.13 Codes for Actions, Conditions, and States 51
Ta b l e 2 - 1 2 States in a traffic-light controller.
DO NOT COPYLights
N-S N-S N-S E-W E-W E-W Code
State green NOT COPYyellow red green yellow red word
N-S go ON off off off off ON 000
off ON off off off ON 001
DON-S wait
N-S delay off off ON off off ON 010
E-W go NOT COPYoff ON ON
off off ON off
DOE-W wait off off off 100
ON off 101
E-W delay off off ON off off ON 110
of the six states listed in Table 2-12. These states can be encoded in three bits, as
DO NOT COPYshown in the last column of the table. Only six of the eight possible 3-bit code
words are used, and the assignment of the six chosen code words to states is arbi-
trary, so many other encodings are possible. An experienced digital designer
chooses a particular encoding to minimize circuit cost or to optimize some other
parameter (like design time—there’s no need to try billions and billions of pos-
DO NOT COPYsibleencodings).
Another application of a binary code is illustrated in Figure 2-7(a). Here,
we have a system with n devices, each of which can perform a certain action.
The characteristics of the devices are such that they may be enabled to operate
only one at a time. The control unit produces a binary-coded “device select”
DO NOT COPYword with log2 n bits to indicate which device is enabled at any time. The
“device select” code word is applied to each device, which compares it with its
own “device ID” to determine whether it is enabled.Although its code words
have the minimum number of bits, a binary code isn’t always the best choice for
encoding actions, conditions, or states. Figure 2-7(b) shows how to control n
DO NOT COPYdevices with a 1-out-of-n code, an n-bit code in which valid code words have one
1-out-of-n code
bit equal to 1 and the rest of the bits equal to 0. Each bit of the 1-out-of-n code
word is connected directly to the enable input of a corresponding device. This
simplifies the design of the devices, since they no longer have device IDs; they
need only a single “enable” input bit.
DO NOT COPYThe code words of a 1-out-of-10 code were listed in Table 2-9. Sometimes
an all-0s word may also be included in a 1-out-of-n code, to indicate that no
device is selected. Another common code is an inverted 1-out-of-n code, in inverted 1-out-of-n code
which valid code words have one 0~bit and the rest of the bits equal to 1.
DO NOT COPYIn complex systems, a combination of coding techniques may be used. For
example, consider a system similar to Figure 2-7(b), in which each of the n
devices contains up to s subdevices. The control unit could produce a device
Copyright © 1999 by John F. Wakerly Copying Prohibited
52 Chapter 2 Number Systems and Codes
Control COPY
DO NOTUnit
binary-coded device select
DO NOT COPY(a)compare device compare device compare device
ID ID ID
device device device
enable enable enable
DO NOT COPYDevice Device Device
1-out-of-n coded device select
Control
DO NOT COPYUnit
device NOTdevice COPYdevice
enable enable
DO(b) enable Device Device
Device
Figure 2-7 Control structure for a digital system with n devices: (a) using
a binary code; (b) using a 1-out-of-n code.
DO NOT COPYselect code word with a 1-out-of-n coded field to select a device, and a log2 s-
bit binary-coded field to select one of the s subdevices of the selected device.
DO NOT COPYm-out-of-ncode
An m-out-of-n code is a generalization of the 1-out-of-n code in which
valid code words have m bits equal to 1 and the rest of the bits equal to 0. A valid
m-out-of-n code word can be detected with an m-input AND gate, which produc-
es a 1 output if all of its inputs are 1. This is fairly simple and inexpensive to do,
yet for most values of m, an m-out-of-n code typically has far more valid code
DO NOT COPYbinomial
words than a 1-out-of-n code. The total number of code words is given by the
coefficient n , which has the value -------------n----!------------- . Thus, a 2-out-of-4
m m! ⋅ (n – m)!
code has 6 valid code words, and a 3-out-of-10 code has 120.
An important variation of an m-out-of-n code is the 8B10B code used in the
DO NOT COPY8B10Bcode
802.3z Gigabit Ethernet standard. This code uses 10 bits to represent 256 valid
code words, or 8 bits worth of data. Most code words use a 5-out-of-10 coding.
However, since 5 is only 252, some 4- and 6-out-of-10 words are also used to
10
complete the code in a very interesting way; more on this in Section 2.16.2.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *2.14 n-Cubes and Distance 53
DO NOT COPY10 11
Figure 2-8
n-cubes for n = 1, 2,
3, and 4.
01
DO NOT COPY1-cube
00 01
2-cube
1110 1111
110 111 0110
NOT COPY0010 1011
DO010 011 0111 1010
100 101 1100
DO000 001 0011 1101
3-cube
1000
0100 0101
NOT COPY0000 1001
0001
4-cube
*2.14 n-Cubes and Distance
DO NOT COPYAn n-bit string can be visualized geometrically, as a vertex of an object called an n-cube
n-cube. Figure 2-8 shows n-cubes for n = 1, 2, 3, 4. An n-cube has 2n vertices,
each of which is labeled with an n-bit string. Edges are drawn so that each vertex
is adjacent to n other vertices whose labels differ from the given vertex in only
one bit. Beyond n = 4, n-cubes are really tough to draw.
DO NOT COPYFor reasonable values of n, n-cubes make it easy to visualize certain coding
and logic minimization problems. For example, the problem of designing an
n-bit Gray code is equivalent to finding a path along the edges of an n-cube, a
path that visits each vertex exactly once. The paths for 3- and 4-bit Gray codes
DO NOT COPYareshowninFigure 2-9.
1110 1111
110 111 NOT0110 Figure 2-9
0010 Traversing n-cubes
DO010 011 in Gray-code order:
DO100 101 (a) 3-cube;
0111 COPY1011
000 001
1010
1100
0011 1101 (b) 4-cube.
NOT COPY0100 0101 1000
1001
0000 0001
(a) (b)
Copyright © 1999 by John F. Wakerly Copying Prohibited
54 Chapter 2 Number Systems and Codes
distance
DO NOT COPYHammingdistance
Cubes also provide a geometrical interpretation for the concept of dis-
tance, also called Hamming distance. The distance between two n-bit strings is
the number of bit positions in which they differ. In terms of an n-cube, the dis-
tance is the minimum length of a path between the two corresponding vertices.
Two adjacent vertices have distance 1; vertices 001 and 100 in the 3-cube have
distance 2. The concept of distance is crucial in the design and understanding of
error-detecting codes, discussed in the next section.
An m-subcube of an n-cube is a set of 2m vertices in which n − m of the bits
DO NOT COPYm-subcube
have the same value at each vertex, and the remaining m bits take on all 2m com-
binations. For example, the vertices (000, 010, 100, 110) form a 2-subcube of the
3-cube. This subcube can also be denoted by a single string, xx0, where “x”
denotes that a particular bit is a don’t-care; any vertex whose bits match in the
non-x positions belongs to this subcube. The concept of subcubes is particularly
DO NOT COPYdon’t-care
useful in visualizing algorithms that minimize the cost of combinational logic
functions, as we’ll show in Section 4.4.
DO NOT COPY*2.15 Codes for Detecting and Correcting Errors
error An error in a digital system is the corruption of data from its correct value to
failure
temporary failure
DO NOT COPYpermanentfailure
some other value. An error is caused by a physical failure. Failures can be either
temporary or permanent. For example, a cosmic ray or alpha particle can cause
a temporary failure of a memory circuit, changing the value of a bit stored in it.
Letting a circuit get too hot or zapping it with static electricity can cause a per-
manent failure, so that it never works correctly again.
error model
independent error
DO NOT COPYmodel
The effects of failures on data are predicted by error models. The simplest
error model, which we consider here, is called the independent error model. In
this model, a single physical failure is assumed to affect only a single bit of data;
single error the corrupted data is said to contain a single error. Multiple failures may cause
multiple errors—two or more bits in error—but multiple errors are normally
assumed to be less likely than single errors.
2.15.1 Error-Detecting Codes
DO NOT COPYmultipleerror
Recall from our definitions in Section 2.10 that a code that uses n-bit strings
need not contain 2n valid code words; this is certainly the case for the codes that
we now consider. An error-detecting code has the property that corrupting or
garbling a code word will likely produce a bit string that is not a code word (a
noncode word).
error-detecting code
DO NOT COPYnoncodeword
A system that uses an error-detecting code generates, transmits, and stores
only code words. Thus, errors in a bit string can be detected by a simple rule—if
the bit string is a code word, it is assumed to be correct; if it is a noncode word,
it contains an error.
DO NOT COPYAn n-bit code and its error-detecting properties under the independent
error model are easily explained in terms of an n-cube. A code is simply a subset
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *2.15 Codes for Detecting and Correcting Errors 55
110 111
DO NOT COPY010 011
110 111 Figure 2-10
010 011 Code words in two
different 3-bit codes:
= code word (a) minimum distance
= 1, does not detect
all single errors;
(b) minimum distance
= 2, detects all single
DO NOT COPY=noncodeword
100 101 100 101
000 001 000 001
errors.
(a) (b)
of the vertices of the n-cube. In order for the code to detect all single errors, no
DO NOT COPYcode-word vertex can be immediately adjacent to another code-word vertex.
For example, Figure 2-10(a) shows a 3-bit code with five code words.
Code word 111 is immediately adjacent to code words 110, 011 and 101. Since
a single failure could change 111 to 110, 011 or 101 this code does not detect all
single errors. If we make 111 a noncode word, we obtain a code that does have
DO NOT COPYthe single-error-detecting property, as shown in (b). No single error can change
one code word into another.
The ability of a code to detect single errors can be stated in terms of the
concept of distance introduced in the preceding section:
DO NOT COPY• A code detects all single errors if the minimum distance between all possi- minimum distance
ble pairs of code words is 2.
In general, we need n + 1 bits to construct a single-error-detecting code
with 2n code words. The first n bits of a code word, called information bits, may
be any of the 2n n-bit strings. To obtain a minimum-distance-2 code, we add one
DO NOT COPYmore bit, called a parity bit, that is set to 0 if there are an even number of 1s
information bit
parity bit
among the information bits, and to 1 otherwise. This is illustrated in the first two
columns of Table 2-13 for a code with three information bits. A valid n+1-bit
code word has an even number of 1s, and this code is called an even-parity code. even-parity code
DO NOT COPYInformation Even-parity
Odd-parity Table 2-13
Bits Code Code Distance-2 codes with
three information bits.
DO NOT COPY010
000 000 0 000 1
001 001 1 001 0
010 1 010 0
011 011 0 011 1
DO NOT COPY110100100 1 100 0
101 101 0 101 1
110 0 110 1
111 111 1 111 0
Copyright © 1999 by John F. Wakerly Copying Prohibited
56 Chapter 2 Number Systems and Codes
odd-parity code
DO NOT COPY1-bitparitycode
We can also construct a code in which the total number of 1s in a valid n+1-bit
code word is odd; this is called an odd-parity code and is shown in the third col-
umn of the table. These codes are also sometimes called 1-bit parity codes, since
they each use a single parity bit.
The 1-bit parity codes do not detect 2-bit errors, since changing two bits
does not affect the parity. However, the codes can detect errors in any odd num-
ber of bits. For example, if three bits in a code word are changed, then the
DO NOT COPYresulting word has the wrong parity and is a noncode word. This doesn’t help us
much, though. Under the independent error model, 3-bit errors are much less
likely than 2-bit errors, which are not detectable. Thus, practically speaking, the
1-bit parity codes’ error detection capability stops after 1-bit errors. Other codes,
DO NOT COPYwith minimum distance greater than 2, can be used to detect multiple errors.
2.15.2 Error-Correcting and Multiple-Error-Detecting Codes
By using more than one parity bit, or check bits, according to some well-chosen
rules, we can create a code whose minimum distance is greater than 2. Before
showing how this can be done, let’s look at how such a code can be used to cor-
rect single errors or detect multiple errors.
DO NOT COPYcheckbits
Suppose that a code has a minimum distance of 3. Figure 2-11 shows a
fragment of the n-cube for such a code. As shown, there are at least two noncode
DO NOT COPYwords between each pair of code words. Now suppose we transmit code words
0001010 1011000
DOFigure 2-11 NOT COPY1001011
0001001 1011011 0011001
Some code words
and noncode words in 1011001
a 7-bit, distance-3 NOT COPY0001011 0001111 1111001
0101011 1001001
DOcode. 0000011 1011101
DO 1010011
NOT COPY0011011 1010001
0010010 1010000
1010010 1010110
DO NOT COPY= codeword
1110010 1011010
= noncode word
1000010
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *2.15 Codes for Detecting and Correcting Errors 57
and assume that failures affect at most one bit of each received code word. Then
a received noncode word with a 1-bit error will be closer to the originally trans-
DO NOT COPYmitted code word than to any other code word. Therefore, when we receive a
noncode word, we can correct the error by changing the received noncode word error correction
to the nearest code word, as indicated by the arrows in the figure. Deciding
which code word was originally transmitted to produce a received word is called
decoding, and the hardware that does this is an error-correcting decoder.
DO NOT COPYA code that is used to correct errors is called an error-correcting code. In
decoding
decoder
error-correcting code
general, if a code has minimum distance 2c + 1, it can be used to correct errors
that affect up to c bits (c = 1 in the preceding example). If a code’s minimum dis-
tance is 2c + d + 1, it can be used to correct errors in up to c bits and to detect
errors in up to d additional bits.
DO NOT COPYFor example, Figure 2-12(a) shows a fragment of the n-cube for a code
with minimum distance 4 (c = 1, d = 1). Single-bit errors that produce noncode
words 00101010 and 11010011 can be corrected. However, an error that produc-
es 10100011 cannot be corrected, because no single-bit error can produce this
DO NOT COPYnoncode word, and either of two 2-bit errors could have produced it. So the code
can detect a 2-bit error, but it cannot correct it.
When a noncode word is received, we don’t know which code word was
originally transmitted; we only know which code word is closest to what we’ve
received. Thus, as shown in Figure 2-12(b), a 3-bit error may be “corrected” to
DO NOT COPYthe wrong value. The possibility of making this kind of mistake may be accept-
able if 3-bit errors are very unlikely to occur. On the other hand, if we are
concerned about 3-bit errors, we can change the decoding policy for the code.
Instead of trying to correct errors, we just flag all noncode words as uncorrect-
able errors. Thus, as shown in (c), we can use the same distance-4 code to detect
DO NOT COPYup to 3-bit errors but correct no errors (c = 0, d = 3).
2.15.3 Hamming Codes
In 1950, R. W. Hamming described a general method for constructing codes
with a minimum distance of 3, now called Hamming codes. For any value of i, Hamming code
DO NOT COPYhis method yields a 2i−1-bit code with i check bits and 2i − 1 − i information
bits. Distance-3 codes with a smaller number of information bits are obtained by
deleting information bits from a Hamming code with a larger number of bits.
The bit positions in a Hamming code word can be numbered from 1
through 2i−1. In this case, any position whose number is a power of 2 is a check
DO NOT COPYbit, and the remaining positions are information bits. Each check bit is grouped
with a subset of the information bits, as specified by a parity-check matrix. As parity-check matrix
DO NOT COPYDECISIONS, The names decoding and decoder make sense, since they are just distance-1 pertur-
DECISIONS bations of deciding and decider.
Copyright © 1999 by John F. Wakerly Copying Prohibited
58 Chapter 2 Number Systems and Codes
DO NOT COPYdetectable2-biterrors
(a)
Figure 2-12
Some code words and 00101010 11010011
noncode words in an 8-bit,
distance-4 code:
DO NOT COPY(a) correcting 1-bit and
10100011
detecting 2-bit errors; 00101011 11000011
(b) incorrectly “correcting” 00100011 11100011
a 3-bit error;
(c) correcting no errors but
DO NOT COPYdetecting up to 3-bit errors.
DO NOT COPYdetectable2-biterrors
correctable 1-bit errors
(b)
DO 00101010 11010011
NOT COPY00101011
10100011
00100011 11100011 11000011
DO NOT COPY3-biterror
looks like a
1-bit error
(c)
DO NOT COPY00101011
11000011
DO NOT COPYall1-to3-biterrors
are detectable
shown in Figure 2-13(a), each check bit is grouped with the information posi-
tions whose numbers have a 1 in the same bit when expressed in binary. For
example, check bit 2 (010) is grouped with information bits 3 (011), 6 (110), and
DO NOT COPY7 (111). For a given combination of information-bit values, each check bit is
chosen to produce even parity, that is, so the total number of 1s in its group is
even.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *2.15 Codes for Detecting and Correcting Errors 59
(a) Bit positionC C1 OPY
DO NOT7 6 5 4 3 2
GroupB COPYGroups Figure 2-13
A Parity-check matrices
DO NOTname for 7-bit Hamming
codes: (a) with bit
positions in
numerical order;
(b) Bit position COPYCheck bits
(b) with check bits
DO NOT7 6 5 3 4 2
1 and information bits
separated.
C
GroupB COPYGroups
DO NOTnameA
DO NOT COPYTraditionally, the bit positions of a parity-check matrix and the resultingCheck bits
Information bits
code words are rearranged so that all of the check bits are on the right, as in
Figure 2-13(b). The first two columns of Table 2-14 list the resulting code words.
We can prove that the minimum distance of a Hamming code is 3 by prov-
ing that at least a 3-bit change must be made to a code word to obtain another
DO NOT COPYcode word. That is, we’ll prove that a 1-bit or 2-bit change in a code word yields
a noncode word.
If we change one bit of a code word, in position j, then we change the parity
of every group that contains position j. Since every information bit is contained
DO NOT COPYin at least one group, at least one group has incorrect parity, and the result is a
noncode word.
What happens if we change two bits, in positions j and k? Parity groups that
contain both positions j and k will still have correct parity, since parity is unaf-
fected when an even number of bits are changed. However, since j and k are
DO NOT COPYdifferent, their binary representations differ in at least one bit, corresponding to
one of the parity groups. This group has only one bit changed, resulting in incor-
rect parity and a noncode word.
If you understand this proof, you should also see how the position number-
ing rules for constructing a Hamming code are a simple consequence of the
DO NOT COPYproof. For the first part of the proof (1-bit errors), we required that the position
numbers be nonzero. And for the second part (2-bit errors), we required that no
Copyright © 1999 by John F. Wakerly Copying Prohibited
60 Chapter 2 Number Systems and Codes
DO NOT COPYTa ble 2-1 4 Code words in distance-3 and distance-4 Hamming
codes with four information bits.
Minimum-distance-3 code Minimum-distance-4 code
DO NOT COPYInformation Parity Bits Information Parity Bits
Bits000Bits 0000
0000
0000
0001 011 0001 0111
DO NOT COPY0010 101 0010 1011
0011 110 0011 1100
0100 110 0100 1101
DO NOT COPY0101 101 0101 1010
01100110110 0110
01110000111 0001
1000 111 1000 1110
DO NOT COPY1001 100 1001 1001
1010 010 1010 0101
1011 001 1011 0010
DO NOT COPY1100 001 1100 0011
11010101101 0100
11101001110 1000
1111 111 1111 1111
two positions have the same number. Thus, with an i-bit position number, you
DO NOT COPYcan construct a Hamming code with up to 2i − 1 bit positions.
error-correcting The proof also suggests how we can design an error-correcting decoder for
DO NOT COPYdecoder
a received Hamming code word. First, we check all of the parity groups; if all
have even parity, then the received word is assumed to be correct. If one or more
groups have odd parity, then a single error is assumed to have occurred. The pat-
syndrome tern of groups that have odd parity (called the syndrome) must match one of the
columns in the parity-check matrix; the corresponding bit position is assumed to
contain the wrong value and is complemented. For example, using the code
defined by Figure 2-13(b), suppose we receive the word 0101011. Groups B and
DO NOT COPYC have odd parity, corresponding to position 6 of the parity-check matrix (the
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *2.15 Codes for Detecting and Correcting Errors 61
syndrome is 110, or 6). By complementing the bit in position 6 of the received
word, we determine that the correct word is 0001011.
DO NOT COPYA distance-3 Hamming code can easily be modified to increase its mini-
mum distance to 4. We simply add one more check bit, chosen so that the parity
of all the bits, including the new one, is even. As in the 1-bit even-parity code,
this bit ensures that all errors affecting an odd number of bits are detectable. In
particular, any 3-bit error is detectable. We already showed that 1- and 2-bit
DO NOT COPYerrors are detected by the other parity bits, so the minimum distance of the mod-
ified code must be 4.
Distance-3 and distance-4 Hamming codes are commonly used to detect
and correct errors in computer memory systems, especially in large mainframe
computers where memory circuits account for the bulk of the system’s failures.
DO NOT COPYThese codes are especially attractive for very wide memory words, since the
required number of parity bits grows slowly with the width of the memory word,
as shown in Table 2-15.
DO NOT COPYTable 2 -15 Word sizes of distance-3 and distance-4 Hamming codes.
Minimum-distance-3 Codes Minimum-distance-4 Codes
Information Bits
Total Bits Total Bits
DO NOT COPY1 3 4
Parity Bits Parity Bits
2 3
≤4 3 ≤7 4 ≤8
≤ 11 4 ≤ 15
DO NOT COPY≤26 5 ≤31
5 ≤ 16
6 ≤ 32
≤ 57 6 ≤ 63 7 ≤ 64
DO NOT COPY2.15.4 CRCCodes ≤ 127
≤ 120 7 8 ≤ 128
Beyond Hamming codes, many other error-detecting and -correcting codes have
been developed. The most important codes, which happen to include Hamming
codes, are the cyclic redundancy check (CRC) codes. A rich set of knowledge cyclic redundancy
DO NOT COPYhas been developed for these codes, focused both on their error detecting and check (CRC) code
correcting properties and on the design of inexpensive encoders and decoders
for them (see References).
Two important applications of CRC codes are in disk drives and in data
networks. In a disk drive, each block of data (typically 512 bytes) is protected
DO NOT COPYby a CRC code, so that errors within a block can be detected and, in some drives,
corrected. In a data network, each packet of data ends with check bits in a CRC
Copyright © 1999 by John F. Wakerly Copying Prohibited
62 Chapter 2 Number Systems and Codes
code. The CRC codes for both applications were selected because of their burst-
error detecting properties. In addition to single-bit errors, they can detect multi-
DO NOT COPYbit errors that are clustered together within the disk block or packet. Such errors
are more likely than errors of randomly distributed bits, because of the likely
physical causes of errors in the two applications—surface defects in disc drives
and noise bursts in communication links.
DO NOT COPY2.15.5 Two-Dimensional Codes
Another way to obtain a code with large minimum distance is to construct a two-
dimensional code, as illustrated in Figure 2-14(a). The information bits are con-
ceptually arranged in a two-dimensional array, and parity bits are provided to
check both the rows and the columns. A code Crow with minimum distance drow is
used for the rows, and a possibly different code Ccol with minimum distance dcol
DO NOT COPYtwo-dimensionalcode
is used for the columns. That is, the row-parity bits are selected so that each row
is a code word in Crow and the column-parity bits are selected so that each column
is a code word in Ccol. (The “corner” parity bits can be chosen according to either
code.) The minimum distance of the two-dimensional code is the product of drow
and dcol; in fact, two-dimensional codes are sometimes called product codes.
DO NOT COPYproductcode
DOFigure 2-14 NOT(a) COPY
checks Rows are
Two-dimensional codes: NOT COPYinformation bits
(a) general structure; on rows code words
(b) using even parity for in Crow
both the row and column
NOT COPYchecksoncolumns checks
DOcodes to obtain on checks
minimum distance 4; Columns are code words in Ccol
(c) typical pattern of an
DOundetectable error.
(b) (c)
DO NOTinformation bits COPY
Rows are No effect on
code words
in 1-bit COPYrow parity
even-parity
DO NOTcode
Columns are code words No effect on column parity
in 1-bit even-parity code
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *2.15 Codes for Detecting and Correcting Errors 63
As shown in Figure 2-14(b), the simplest two-dimensional code uses 1-bit
even-parity codes for the rows and columns, and has a minimum distance of
DO NOT COPY2 ⋅ 2, or 4. You can easily prove that the minimum distance is 4 by convincing
yourself that any pattern of one, two, or three bits in error causes incorrect parity
of a row or a column or both. In order to obtain an undetectable error, at least
four bits must be changed in a rectangular pattern as in (c).
The error detecting and correcting procedures for this code are straightfor-
DO NOT COPYward. Assume we are reading information one row at a time. As we read each
row, we check its row code. If an error is detected in a row, we can’t tell which bit
is wrong from the row check alone. However, assuming only one row is bad, we
can reconstruct it by forming the bit-by-bit Exclusive OR of the columns, omit-
ting the bad row, but including the column-check row.
DO NOT COPYTo obtain an even larger minimum distance, a distance-3 or -4 Hamming
code can be used for the row or column code or both. It is also possible to con-
struct a code in three or more dimensions, with minimum distance equal to the
product of the minimum distances in each dimension.
DO NOT COPYAn important application of two-dimensional codes is in RAID storage
systems. RAID stands for “redundant array of inexpensive disks.” In this RAID
scheme, n+1 identical disk drives are used to store n disks worth of data. For
example, eight 8-Gigabyte drives could be use to store 64 Gigabytes of non-
redundant data, and a ninth 8-gigabyte drive would be used to store checking
DO NOT COPYinformation.
Figure 2-15 shows the general scheme of a two-dimensional code for a
RAID system; each disk drive is considered to be a row in the code. Each drive
stores m blocks of data, where a block typically contains 512 bytes. For example,
an 8-gigabyte drive would store about 16 million blocks. As shown in the figure,
DO NOT COPYeach block includes its own check bits in a CRC code, to detect errors within that
block. The first n drives store the nonredundant data. Each block in drive n+1
DO NOT COPYFigure 2-15
Block number Structure of error-
1 2 3 4 5 6 7 8 9 10 11 12 . . . m correcting code for
a RAID system.
Disk 1
Disk 2
DO NOT COPYDisk3
Data bytes
Disk 4 information blocks ... 1234567 . . . 512 CRC
Disk 5 ...
Disk 6
... ... One block
DO NOT COPYDiskn ...
Disk n+1
check blocks
Copyright © 1999 by John F. Wakerly Copying Prohibited
64 Chapter 2 Number Systems and Codes
stores parity bits for the corresponding blocks in the first n drives. That is, each
bit i in drive n+1 block b is chosen so that there are an even number of 1s in block
DO NOT COPYb bit position i across all the drives.
In operation, errors in the information blocks are detected by the CRC
code. Whenever an error is detected in a block on one of the drives, the correct
contents of that block can be constructed simply by computing the parity of the
corresponding blocks in all the other drives, including drive n+1. Although this
DO NOT COPYrequires n extra disk read operations, it’s better than losing your data! Write
operations require extra disk accesses as well, to update the corresponding check
block when an information block is written (see Exercise 2.46). Since disk
writes are much less frequent than reads in typical applications, this overhead
DO NOT COPYusuallyisnota problem.
2.15.6 Checksum Codes
The parity-checking operation that we’ve used in the previous subsections is
essentially modulo-2 addition of bits—the sum modulo 2 of a group of bits is 0
if the number of 1s in the group is even, and 1 if it is odd. The technique of mod-
DO NOT COPYular addition can be extended to other bases besides 2 to form check digits.
For example, a computer stores information as a set of 8-bit bytes. Each
DO NOT COPYchecksum
byte may be considered to have a decimal value from 0 to 255. Therefore, we can
use modulo-256 addition to check the bytes. We form a single check byte, called
a checksum, that is the sum modulo 256 of all the information bytes. The result-
checksum code ing checksum code can detect any single byte error, since such an error will cause
a recomputed sum of bytes to disagree with the checksum.
ones’-complement
DO NOT COPYchecksumcode
Checksum codes can also use a different modulus of addition. In particular,
checksum codes using modulo-255, ones’-complement addition are important
because of their special computational and error detecting properties, and
because they are used to check packet headers in the ubiquitous Internet Protocol
(IP) (see References).
2.15.7 m-out-of-n Codes
DO NOT COPYThe 1-out-of-n and m-out-of-n codes that we introduced in Section 2.13 have a
minimum distance of 2, since changing only one bit changes the total number of
1s in a code word and therefore produces a noncode word.
These codes have another useful error-detecting property—they detect uni-
directional multiple errors. In a unidirectional error, all of the erroneous bits
change in the same direction (0s change to 1s, or vice versa). This property is
DO NOT COPYunidirectionalerror
very useful in systems where the predominant error mechanism tends to change
DO NOT COPYall bits in the same direction.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 2.16 Codes for Serial Data Transmission and Storage 65
time
DO NOT COPYCLOCK
bit time
DO NOT COPYSERDATA
bit cell bit cell bit cell bit cell bit cell bit cell bit cell bit cell bit cell bit cell
SYNC
bit number 1 2 3 4 5 6 7 8 1 2
DO NOT COPYFigure 2-16 Basic concepts for serial data transmission.
DO NOT COPY2.16 Codes for Serial Data Transmission and Storage
2.16.1 Parallel and Serial Data
Most computers and other digital systems transmit and store data in a parallel
format. In parallel data transmission, a separate signal line is provided for each
DO NOT COPYbit of a data word. In parallel data storage, all of the bits of a data word can be
parallel data
written or read simultaneously.
Parallel formats are not cost-effective for some applications. For example,
parallel transmission of data bytes over the telephone network would require
eight phone lines, and parallel storage of data bytes on a magnetic disk would
DO NOT COPYrequire a disk drive with eight separate read/write heads. Serial formats allow
serial data
data to be transmitted or stored one bit at a time, reducing system cost in many
applications.
Figure 2-16 illustrates some of the basic ideas in serial data transmission.
DO NOT COPYA repetitive clock signal, named CLOCK in the figure, defines the rate at which
bits are transmitted, one bit per clock cycle. Thus, the bit rate in bits per second bit rate, bps
(bps) numerically equals the clock frequency in cycles per second (hertz, or Hz).
The reciprocal of the bit rate is called the bit time and numerically equals bit time
the clock period in seconds (s). This amount of time is reserved on the serial data
DO NOT COPYline (named SERDATA in the figure) for each bit that is transmitted. The time
occupied by each bit is sometimes called a bit cell. The format of the actual sig- bit cell
nal that appears on the line during each bit cell depends on the line code. In the
simplest line code, called Non-Return-to-Zero (NRZ), a 1 is transmitted by plac-
ing a 1 on the line for the entire bit cell, and a 0 is transmitted as a 0. However,
DO NOT COPYmore complex line codes have other rules, as discussed in the next subsection.
line code
Non-Return-to-Zero
(NRZ)
Copyright © 1999 by John F. Wakerly Copying Prohibited
66 Chapter 2 Number Systems and Codes
Regardless of the line code, a serial data transmission or storage system
needs some way of identifying the significance of each bit in the serial stream. For
DO NOT COPYexample, suppose that 8-bit bytes are transmitted serially. How can we tell which
synchronization signal is the first bit of each byte? A synchronization signal, named SYNC in
Figure 2-16, provides the necessary information; it is 1 for the first bit of each byte.
Evidently, we need a minimum of three signals to recover a serial data
stream: a clock to define the bit cells, a synchronization signal to define the word
DO NOT COPYboundaries, and the serial data itself. In some applications, like the interconnec-
tion of modules in a computer or telecommunications system, a separate wire is
used for each of these signals, since reducing the number of wires per connec-
tion from n to three is savings enough. We’ll give an example of a 3-wire serial
data system in Section 8.5.4.
DO NOT COPYIn many applications, the cost of having three separate signals is still too
high (e.g., three phone lines, three read/write heads). Such systems typically
combine all three signals into a single serial data stream and use sophisticated
analog and digital circuits to recover the clock and synchronization information
DO NOT COPYfromthedatastream.
*2.16.2 Serial Line Codes
The most commonly used line codes for serial data are illustrated in Figure 2-17.
In the NRZ code, each bit value is sent on the line for the entire bit cell. This is
DO NOT COPYthe simplest and most reliable coding scheme for short distance transmission.
However, it generally requires a clock signal to be sent along with the data to
define the bit cells. Otherwise, it is not possible for the receiver to determine how
many 0s or 1s are represented by a continuous 0 or 1 level. For example, without
a clock to define the bit cells, the NRZ waveform in Figure 2-17 might be erro-
DO NOT COPYneously interpreted as 01010.
Figure 2-17 time
DOCommonly used line NOT COPYbitvalue 0 1 1 1 0 0 1 0
codes for serial data. NRZ
DO NOT COPYNRZI
RZ
DO NOTBPRZ COPY
Manchester
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 2.16 Codes for Serial Data Transmission and Storage 67
A digital phase-locked loop (DPLL) is an analog/digital circuit that can be digital phase-locked
used to recover a clock signal from a serial data stream. The DPLL works only if loop (DPLL)
DO NOT COPYthe serial data stream contains enough 0-to-1 and 1-to-0 transitions to give the
DPLL “hints” about when the original clock transitions took place. With NRZ-
coded data, the DPLL works only if the data does not contain any long, continu-
ous streams of 1s or 0s.
Some serial transmission and storage media are transition sensitive; they
DO NOT COPYcannot transmit or store absolute 0 or 1 levels, only transitions between two dis-
transition-sensitive
media
crete levels. For example, a magnetic disk or tape stores information by
changing the polarity of the medium’s magnetization in regions corresponding
to the stored bits. When the information is recovered, it is not feasible to deter-
mine the absolute magnetization polarity of a region, only that the polarity
DO NOT COPYchanges between one region and the next.
Data stored in NRZ format on transition-sensitive media cannot be recov-
ered unambiguously; the data in Figure 2-17 might be interpreted as 01110010
or 10001101. The Non-Return-to-Zero Invert-on-1s (NRZI) code overcomes this Non-Return-to-Zero
DO NOT COPYlimitation by sending a 1 as the opposite of the level that was sent during the pre- Invert-on-1s (NRZI)
vious bit cell, and a 0 as the same level. A DPLL can recover the clock from
NRZI-coded data as long as the data does not contain any long, continuous
streams of 0s.
The Return-to-Zero (RZ) code is similar to NRZ except that, for a 1 bit, the Return-to-Zero (RZ)
DO NOT COPY1 level is transmitted only for a fraction of the bit time, usually 1/2. With this code,
data patterns that contain a lot of 1s create lots of transitions for a DPLL to use to
recover the clock. However, as in the other line codes, a string of 0s has no transi-
tions, and a long string of 0s makes clock recovery impossible.
Another requirement of some transmission media, such as high-speed
DO NOT COPYfiber-optic links, is that the serial data stream be DC balanced. That is, it must DC balance
have an equal number of 1s and 0s; any long-term DC component in the stream
(created by have a lot more 1s than 0s or vice versa) creates a bias at the receiver
that reduces its ability to distinguish reliably between 1s and 0s.
Ordinarily, NRZ, NRZI or RZ data has no guarantee of DC balance; there’s
DO NOT COPYnothing to prevent a user data stream from having a long string of words with
more than 1s than 0s or vice versa. However, DC balance can still be achieved
using a few extra bits to code the user data in a balanced code, in which each balanced code
code word has an equal number of 1s and 0s, and then sending these code words
in NRZ format.
DO NOT COPYFor example, in Section 2.13 we introduced the 8B10B code, which codes
8 bits of user data into 10 bits in a mostly 5-out-of-10 code. Recall that there are
obfut6t-hoeurte-oafr-e10ancootdheerwo14r0ds.=O2f10co4u-rosuet,-othf-e1s0e
DO NOT COPYcode words aren’t quite DC balanced. The 8B10B code solves this problem by
only 252 5-out-of-10 code words,
code words and an equal number
associating with each 8-bit value to be encoded a pair of unbalanced code words,
one 4-out-of-10 (“light”) and the other 6-out-of-10 (“heavy”). The coder also
Copyright © 1999 by John F. Wakerly Copying Prohibited
68 Chapter 2 Number Systems and Codes
KILO-, MEGA-, The prefixes K (kilo-), M (mega-), G (giga-), and T (tera-) mean 103, 106, 109, and
DO NOT COPYGIGA-, TERA- 1012, respectively, when referring to bps, hertz, ohms, watts, and most other engi-
neering quantities. However, when referring to memory sizes, the prefixes mean 210,
220, 230, and 240. Historically, the prefixes were co-opted for this purpose because
memory sizes are normally powers of 2, and 210 (1024) is very close to 1000,
Now, when somebody offers you 50 kilobucks a year for your first engineering
DO NOT COPYjob, it’s up to you to negotiate what the prefix means!
DO NOT COPYrunningdisparity
keeps track of the running disparity, a single bit of information indicating
whether the last unbalanced code word that it transmitted was heavy or light.
When it comes time to transmit another unbalanced code word, the coder selects
the one of the pair with the opposite weight. This simple trick makes available
252 + 210 = 462 code words for the 8B10B to encode 8 bits of user data. Some
of the “extra” code words are used to conveniently encode non-data conditions
DO NOT COPYon the serial line, such as IDLE, SYNC, and ERROR. Not all the unbalanced code
words are used. Also, some of the balanced code words, such as 0000011111,
are not used either, in favor of unbalanced pairs that contain more transitions.
All of the preceding codes transmit or store only two signal levels. The
Bipolar Return-to-Zero (BPRZ) code transmits three signal levels: +1, 0, and −1.
The code is like RZ except that 1s are alternately transmitted as +1 and −1; for
Bipolar Return-to-Zero
DO NOT COPY(BPRZ)
Alternate Mark this reason, the code is also known as Alternate Mark Inversion (AMI).
DO NOT COPYInversion(AMI)
The big advantage of BPRZ over RZ is that it’s DC balanced. This makes it
possible to send BPRZ streams over transmission media that cannot tolerate a
DC component, such as transformer-coupled phone lines. In fact, the BPRZ
code has been used in T1 digital telephone links for decades, where analog
speech signals are carried as streams of 8000 8-bit digital samples per second
that are transmitted in BPRZ format on 64 Kbps serial channels.
As with RZ, it is possible to recover a clock signal from a BPRZ stream as
DO NOT COPYlong as there aren’t too many 0s in a row. Although TPC (The Phone Company)
has no control over what you say (at least, not yet), they still have a simple way
of limiting runs of 0s. If one of the 8-bit bytes that results from sampling your
DO NOT COPYzero-codesuppression
analog speech pattern is all 0s, they simply change second-least significant bit
to 1! This is called zero-code suppression and I’ll bet you never noticed it. And
this is also why, in many data applications of T1 links, you get only 56 Kbps of
usable data per 64 Kbps channel; the LSB of each byte is always set to 1 to pre-
vent zero-code suppression from changing the other bits.
The last code in Figure 2-17 is called Manchester or diphase code. The
major strength of this code is that, regardless of the transmitted data pattern, it
provides at least one transition per bit cell, making it very easy to recover the
Manchester
DO NOT COPYdiphase
clock. As shown in the figure, a 0 is encoded as a 0-to-1 transition in the middle
Copyright © 1999 by John F. Wakerly Copying Prohibited
References 69
ABOUT TPC Watch the 1967 James Coburn movie, The President’s Analyst, for an amusing view
DO NOT COPYof TPC. With the growing pervasiveness of digital technology and cheap wireless
communications, the concept of universal, personal connectivity to the phone net-
DO NOT COPYwork presented in the movie’s conclusion has become much less far-fetched.
of the bit cell, and a 1 is encoded as a 1-to-0 transition. The Manchester code’s
major strength is also its major weakness. Since it has more transitions per bit
cell than other codes, it also requires more media bandwidth to transmit a given
bit rate. Bandwidth is not a problem in coaxial cable, however, which was used
DO NOT COPYin the original Ethernet local area networks to carry Manchester-coded serial
data at the rate of 10 Mbps (megabits per second).
References
DO NOT COPYThe presentation in the first nine sections of this chapter is based on Chapter 4
of Microcomputer Architecture and Programming, by John F. Wakerly (Wiley,
1981). Precise, thorough, and entertaining discussions of these topics can also
be found in Donald E. Knuth’s Seminumerical Algorithms, 3rd edition (Addi-
DO NOT COPYson-Wesley, 1997). Mathematically inclined readers will find Knuth’s analysis
of the properties of number systems and arithmetic to be excellent, and all read-
ers should enjoy the insights and history sprinkled throughout the text.
Descriptions of digital logic circuits for arithmetic operations, as well as an
introduction to properties of various number systems, appear in Computer Arith-
DO NOT COPYmetic by Kai Hwang (Wiley, 1979). Decimal Computation by Hermann Schmid
(Wiley, 1974) contains a thorough description of techniques for BCD arithmetic.
An introduction to algorithms for binary multiplication and division and to
floating-point arithmetic appears in Microcomputer Architecture and Program-
ming: The 68000 Family by John F. Wakerly (Wiley, 1989). A more thorough
DO NOT COPYdiscussion of arithmetic techniques and floating-point number systems can be
found in Introduction to Arithmetic for Digital Systems Designers by Shlomo
Waser and Michael J. Flynn (Holt, Rinehart and Winston, 1982). finite fields
CRC codes are based on the theory of finite fields, which was developed by
French mathematician Évariste Galois (1811–1832) shortly before he was killed
DO NOT COPYin a duel with a political opponent. The classic book on error-detecting and
error-correcting codes is Error-Correcting Codes by W. W. Peterson and E. J.
Weldon, Jr. (MIT Press, 1972, 2nd ed.); however, this book is recommended
only for mathematically sophisticated readers. A more accessible introduction
can be found in Error Control Coding: Fundamentals and Applications by S.
DO NOT COPYLin and D. J. Costello, Jr. (Prentice Hall, 1983). Another recent, communica-
tion-oriented introduction to coding theory can be found in Error-Control
Copyright © 1999 by John F. Wakerly Copying Prohibited
70 Chapter 2 Number Systems and Codes
Techniques for Digital Communication by A. M. Michelson and A. H. Levesque
(Wiley-Interscience, 1985). Hardware applications of codes in computer sys-
DO NOT COPYtems are discussed in Error-Detecting Codes, Self-Checking Circuits, and
Applications by John F. Wakerly (Elsevier/North-Holland, 1978).
As shown in the above reference by Wakerly, ones’-complement checksum
codes have the ability to detect long bursts of unidirectional errors; this is useful
in communication channels where errors all tend to be in the same direction. The
DO NOT COPYspecial computational properties of these codes also make them quite amenable
to efficient checksum calculation by software programs, important for their use
in the Internet Protocol; see RFC-1071 and RFC-1141.
An introduction to coding techniques for serial data transmission, includ-
ing mathematical analysis of the performance and bandwidth requirements of
DO NOT COPYseveral codes, appears in Introduction to Communications Engineering by R. M.
Gagliardi (Wiley-Interscience, 1988, 2nd ed.). A nice introduction to the serial
codes used in magnetic disks and tapes is given in Computer Storage Systems
and Technology by Richard Matick (Wiley-Interscience, 1977).
DO NOT COPYThe structure of the 8B10B code and the rationale behind it is explained
nicely in the original IBM patent by Peter Franaszek and Albert Widmer, U.S.
patent number 4,486,739 (1984). This and almost all U.S. patents issued after
1971 can be found on the web at www.patents.ibm.com. When you’re done
DO NOT COPYreading Franaszek, for a good time do a boolean search for inventor “wakerly”.
Drill Problems
(a) 11010112 = ?16
DO NOT COPY(c) 101101112=?16
2.1 Perform the following number system conversions:
(b) 1740038 = ?2
(d) 67.248 = ?2
(e) 10100.11012 = ?16 (f) F3A516 = ?2
(g) 110110012 = ?8
DO NOT COPY(i) 101111.01112= ?8
(h) AB3D16 = ?2
(j) 15C.3816 = ?2
2.2 Convert the following octal numbers into binary and hexadecimal:
DO NOT(a) 10238 = ?2 = ?16 COPY(b) 7613028 = ?2 = ?16
(c) 1634178 = ?2 = ?16 (d) 5522738 = ?2 = ?16
(e) 5436.158 = ?2 = ?16 (f) 13705.2078 = ?2 = ?16
2.3 Convert the following hexadecimal numbers into binary and octal:
DO NOT(a) 102316 = ?2 = ?8 COPY(b) 7E6A16 = ?2 = ?8
(c) ABCD16 = ?2 = ?8 (d) C35016 = ?2 = ?8
(e) 9E36.7A16 = ?2 = ?8 (f) DEAD.BEEF16 = ?2 = ?8
Copyright © 1999 by John F. Wakerly Copying Prohibited
Drill Problems 71
2.4 What are the octal values of the four 8-bit bytes in the 32-bit number with octal
representation 123456701238?
DO NOT COPY2.5 Convert the following numbers into decimal:
(a) 11010112 = ?10 (b) 1740038 = ?10
(c) 101101112 = ?10 COPY
(e) 10100.11012 = ?10
DO NOT(g) 120103 = ?10
(d) 67.248 = ?10
(f) F3A516 = ?10
(h) AB3D16 = ?10
(i) 71568 = ?10 (j) 15C.3816 = ?10
DO NOT(a) 12510=?2 COPY
2.6 Perform the following number system conversions:
(b) 348910 = ?8
(c) 20910 = ?2 (d) 971410 = ?8
DO(e) 13210 = ?2 NOT(f) 2385110 = ?16 COPY
(g) 72710 = ?5 (h) 5719010 = ?16
(i) 143510 = ?8 (j) 6511310 = ?16
2.7 Add the following pairs of binary numbers, showing all carries:
DO NOT COPY2.8 Repeat Drill 2.7 using subtraction instead of addition, and showing borrows
(a) 110101 (b) 101110 (c) 11011101 (d) 1110010
+ 11001 + 100101 + 1100011 + 1101101
instead of carries.
DO NOT COPY+ 4631
2.9 Add the following pairs of octal numbers:
(a) 1372 (b) 47135 (c) 175214 (d) 110321
+ 56573
+ 5125 + 152405
2.10 Add the following pairs of hexadecimal numbers:
DO NOT COPY+ 4631
(a) 1372 (b) 4F1A5 (c) F35B (d) 1B90F
+ B8D5 + 27E6 + C44E
2.11 Write the 8-bit signed-magnitude, two’s-complement, and ones’-complement
representations for each of these decimal numbers: +18, +115, +79, −49, −3, −100.
2.12 Indicate whether or not overflow occurs when adding the following 8-bit two’s-
DO NOT COPYcomplementnumbers:
(a) 11010100 (b) 10111001 (c) 01011101 (d) 00100110
+ 10101011 + 11010110 + 00100001 + 01011010
2.13 How many errors can be detected by a code with minimum distance d?
DO NOT COPY2.14 What is the minimum number of parity bits required to obtain a distance-4, two-
dimensional code with n information bits?
Copyright © 1999 by John F. Wakerly Copying Prohibited
72 Chapter 2 Number Systems and Codes
Exercises
2.15 Here’s a problem to whet your appetite. What is the hexadecimal equivalent of
DO NOT COPY6145310?
2.16 Each of the following arithmetic operations is correct in at least one number sys-
DO (a) 1234 + 5432 = 6666
NOT COPY(c) 33/3=11
tem. Determine possible radices of the numbers in each operation.
(b) 41 / 3 = 13
(d) 23+44+14+32 = 223
(e) 302/20 = 12.1 (f) 14 = 5
2.17 The first expedition to Mars found only the ruins of a civilization. From the arti-
facts and pictures, the explorers deduced that the creatures who produced this
DO NOT COPYcivilization were four-legged beings with a tentacle that branched out at the end
with a number of grasping “fingers.” After much study, the explorers were able
DO to translate Martian mathematics. They found the following equation:
NOT COPY5x2−50x+125=0
with the indicated solutions x = 5 and x = 8. The value x = 5 seemed legitimate
enough, but x = 8 required some explanation. Then the explorers reflected on the way
in which Earth’s number system developed, and found evidence that the Martian sys-
tem had a similar history. How many fingers would you say the Martians had? (From
The Bent of Tau Beta Pi, February, 1956.)
DO NOT COPY2.18 Suppose a 4n-bit number B is represented by an n-digit hexadecimal number H.
Prove that the two’s complement of B is represented by the 16’s complement of
H. Make and prove true a similar statement for octal representation.
2.19 Repeat Exercise 2.18 using the ones’ complement of B and the 15s’ complement
of H.
DO NOT COPY2.20 Given an integer x in the range −2n−1 ≤ x ≤ 2n−1 − 1, we define [x] to be the two’s-
complement representation of x, expressed as a positive number: [x] = x if x ≥ 0
and [x] = 2n − |x| if x < 0, where | x| is the absolute value of x. Let y be another
DO
NOT COPYinteger in the same range as x. Prove that the two’s-complement addition rules
given in Section 2.6 are correct by proving that the following equation is always
true:
[ x + y] = ( [x] + [y] ) modulo 2n
(Hints: Consider four cases based on the signs of x and y. Without loss of generality,
you may assume that | x| ≥ | y|.)
DO NOT COPY2.21 Repeat Exercise 2.20 using appropriate expressions and rules for ones’-comple-
ment addition.
2.22 State an overflow rule for addition of two’s-complement numbers in terms of
counting operations in the modular representation of Figure 2-3.
2.23 Show that a two’s-complement number can be converted to a representation with
DO NOT COPYmore bits by sign extension. That is, given an n-bit two’s-complement number X,
show that the m-bit two’s-complement representation of X, where m > n, can be
Copyright © 1999 by John F. Wakerly Copying Prohibited
Exercises 73
obtained by appending m − n copies of X’s sign bit to the left of the n-bit repre-
sentation of X.
DO NOT COPY2.24 Show that a two’s-complement number can be converted to a representation with
fewer bits by removing higher-order bits. That is, given an n-bit two’s-comple-
ment number X, show that the m-bit two’s-complement number Y obtained by
discarding the d leftmost bits of X represents the same number as X if and only if
the discarded bits all equal the sign bit of Y.
DO NOT COPY2.25 Why is the punctuation of “two’s complement” and “ones’ complement” incon-
sistent? (See the first two citations in the References.)
2.26 A n-bit binary adder can be used to perform an n-bit unsigned subtraction opera-
tion X − Y, by performing the operation X + Y + 1, where X and Y are n-bit
unsigned numbers and Y represents the bit-by-bit complement of Y. Demonstrate
DO NOT COPYthis fact as follows. First, prove that (X − Y) = (X + Y + 1) − 2n. Second, prove that
the carry out of the n-bit adder is the opposite of the borrow from the n-bit sub-
traction. That is, show that the operation X − Y produces a borrow out of the MSB
position if and only if the operation X + Y + 1 does not produce a carry out of the
MSB position.
DO NOT COPY2.27 In most cases, the product of two n-bit two’s-complement numbers requires fewer
than 2n bits to represent it. In fact, there is only one case in which 2n bits are
needed—find it.
2.28 Prove that a two’s-complement number can be multiplied by 2 by shifting it one
bit position to the left, with a carry of 0 into the least significant bit position and
DO NOT COPYdisregarding any carry out of the most significant bit position, assuming no over-
flow. State the rule for detecting overflow.
2.29 State and prove correct a technique similar to the one described in Exercise 2.28,
for multiplying a ones’-complement number by 2.
2.30 Show how to subtract BCD numbers, by stating the rules for generating borrows
DO NOT COPYand applying a correction factor. Show how your rules apply to each of the fol-
lowing subtractions: 9 − 3, 5 − 7, 4 − 9, 1 − 8.
2.31 How many different 3-bit binary state encodings are possible for the traffic-light
controller of Table 2-12?
2.32 List all of the “bad” boundaries in the mechanical encoding disc of Figure 2-5,
DO NOT COPYwhere an incorrect position may be sensed.
2.33 As a function of n, how many “bad” boundaries are there in a mechanical encod-
ing disc that uses an n-bit binary code?
2.34 On-board altitude transponders on commercial and private aircraft use Gray code
to encode the altitude readings that are transmitted to air traffic controllers. Why?
DO NOT COPY2.35 An incandescent light bulb is stressed every time it is turned on, so in some appli-
cations the lifetime of the bulb is limited by the number of on/off cycles rather
than the total time it is illuminated. Use your knowledge of codes to suggest a way
to double the lifetime of 3-way bulbs in such applications.
DO NOT COPY2.36 As a function of n, how many different distinct subcubes of an n-cube are there?
2.37 Find a way to draw a 3-cube on a sheet of paper (or other two-dimensional object)
so that none of the lines cross, or prove that it’s impossible.
Copyright © 1999 by John F. Wakerly Copying Prohibited
74 Chapter 2 Number Systems and Codes
2.38 Repeat Exercise 2.37 for a 4-cube.
2.39 Write a formula that gives the number of m-subcubes of an n-cube for a specific
DO NOT COPYvalue of m. (Your answer should be a function of n and m.)
2.40 Define parity groups for a distance-3 Hamming code with 11 information bits.
2.41 Write the code words of a Hamming code with one information bit.
2.42 Exhibit the pattern for a 3-bit error that is not detected if the “corner” parity bits
are not included in the two-dimensional codes of Figure 2-14.
DO NOT COPY2.43 The rate of a code is the ratio of the number of information bits to the total num-
ber of bits in a code word. High rates, approaching 1, are desirable for efficient
transmission of information. Construct a graph comparing the rates of distance-2
parity codes and distance-3 and -4 Hamming codes for up to 100 information bits.
2.44 Which type of distance-4 code has a higher rate—a two-dimensional code or a
DO NOT COPYHamming code? Support your answer with a table in the style of Table 2-15,
including the rate as well as the number of parity and information bits of each
code for up to 100 information bits.
2.45 Show how to construct a distance-6 code with four information bits. Write a list
of its code words.
DO NOT COPY2.46 Describe the operations that must be performed in a RAID system to write new
data into information block b in drive d, so the data can be recovered in the event
of an error in block b in any drive. Minimize the number of disk accesses
required.
2.47 In the style of Figure 2-17, draw the waveforms for the bit pattern 10101110
DO NOT COPYwhen sent serially using the NRZ, NRZI, RZ, BPRZ, and Manchester codes,
assuming that the bits are transmitted in order from left to right.
DO NOT COPY
DO NOT COPY
DO NOT COPY
DO NOT COPY
Copyright © 1999 by John F. Wakerly Copying Prohibited
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••DO NOT 3c h a p t e r
COPY
DO NOT
COPYDigital Circuits
MDO NOTarketing hype notwithstanding, we live in an analog world, not
a digital one. Voltages, currents, and other physical quantities
in real circuits take on values that are infinitely variable,
COPYdepending on properties of the real devices that comprise the
circuits. Because real values are continuously variable, we
could use a physical quantity such as a signal voltage in a circuit to represent
a real number (e.g., 3.14159265358979 volts represents the mathematical
constant pi to 14 decimal digits of precision).
DO NOTUnfortunately, stability and accuracy in physical quantities are diffi-
cult to obtain in real circuits. They are affected by manufacturing tolerances,
temperature, power-supply voltage, cosmic rays, and noise created by other
circuits, among other things. If we used an analog voltage to represent pi, we
might find that instead of being an absolute mathematical constant, pi varied
COPYover a range of 10% or more.
Also, many mathematical and logical operations are difficult or impos-
sible to perform with analog quantities. While it is possible with some
cleverness to build an analog circuit whose output voltage is the square root
of its input voltage, no one has ever built a 100-input, 100-output analog cir-
DO NOTcuit whose outputs are a set of voltages identical to the set of input voltages,
but sorted arithmetically.
The purpose of this chapter is to give you a solid working knowledge
of the electrical aspects of digital circuits, enough for you to understand and
Copyright © 1999 by John F. Wakerly Copying Prohibited 75
76 Chapter 3 Digital Circuits
build real circuits and systems. We’ll see in later chapters that with modern soft-
ware tools, it’s possible to “build” circuits in the abstract, using hardware design
DO NOT COPYlanguages to specify their design and simulators to test their operation. Still, to
build real, production-quality circuits, either at the board level or the chip level,
you need to understand most of the material in this chapter. However, if you’re
anxious to start designing and simulating abstract circuits, you can just read the
DO NOT COPYfirst section of this chapter and come back to the rest of it later.
3.1 Logic Signals and Gates
digital logic
DO NOT COPYlogicvalues
Digital logic hides the pitfalls of the analog world by mapping the infinite set of
real values for a physical quantity into two subsets corresponding to just two
possible numbers or logic values—0 and 1. As a result, digital logic circuits can
be analyzed and designed functionally, using switching algebra, tables, and
other abstract means to describe the operation of well-behaved 0s and 1s in a
circuit.
A logic value, 0 or 1, is often called a binary digit, or bit. If an application
requires more than two discrete values, additional bits may be used, with a set of
binary digit
DO NOT COPYbit
n bits representing 2n different values.
Examples of the physical phenomena used to represent bits in some mod-
ern (and not-so-modern) digital technologies are given in Table 3-1. With
DO NOT COPYmost phenomena, there is an undefined region between the 0 and 1 states (e.g.,
voltage = 1.8 V, dim light, capacitor slightly charged, etc.). This undefined
region is needed so that the 0 and 1 states can be unambiguously defined and
reliably detected. Noise can more easily corrupt results if the boundaries sepa-
rating the 0 and 1 states are too close.
DO NOT COPYWhen discussing electronic logic circuits such as CMOS and TTL, digital
LOW designers often use the words “LOW” and “HIGH” in place of “0” and “1” to
HIGH remind them that they are dealing with real circuits, not abstract quantities:
LOW A signal in the range of algebraically lower voltages, which is interpret-
DO NOT COPYedasalogic0.
HIGH A signal in the range of algebraically higher voltages, which is interpret-
ed as a logic 1.
DO NOT COPYpositivelogic
Note that the assignments of 0 and 1 to LOW and HIGH are somewhat arbitrary.
Assigning 0 to LOW and 1 to HIGH seems most natural, and is called positive
logic. The opposite assignment, 1 to LOW and 0 to HIGH, is not often used, and
negative logic is called negative logic.
DO NOT COPYbufferamplifier
Because a wide range of physical values represent the same binary value,
digital logic is highly immune to component and power supply variations and
noise. Furthermore, buffer amplifier circuits can be used to regenerate “weak”
values into “strong” ones, so that digital signals can be transmitted over arbitrary
distances without loss of information. For example, a buffer amplifier for CMOS
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.1 Logic Signals and Gates 77
Ta b l e 3 - 1 Physical states representing bits in different computer logic and
DO NOT COPYmemory technologies.
State Representing Bit
Technology
Pneumatic logic
DO NOT COPYRelaylogic
0 1
Fluid at low pressure Fluid at high pressure
Circuit open Circuit closed
Complementary metal-oxide semi 0–1.5 V 3.5–5.0 V
conductor (CMOS) logic
Transistor-transistor logic (TTL) 0–0.8 V COPY2.0–5.0 V
Light off Light on
DO NOTFiberoptics
Dynamic memory Capacitor discharged Capacitor charged
Nonvolatile, erasable memory
DO NOT COPYBipolarread-only memory
Electrons trapped Electrons released
Fuse blown Fuse intact
Bubble memory No magnetic bubble Bubble present
Flux direction “south”
Molecule in state B
Pit
Magnetic tape or disk NOT COPYFlux direction “north”
Polymer memory Molecule in state A
No pit
DORead-only compact disc Dye in crystalline state
Rewriteable compact disc Dye in non-crystalline state
logic converts any HIGH input voltage into an output very close to 5.0 V, and any
DO NOT COPYLOW input voltage into an output very close to 0.0 V.
A logic circuit can be represented with a minimum amount of detail simply
as a “black box” with a certain number of inputs and outputs. For example,
Figure 3-1 shows a logic circuit with three inputs and one output. However, this
representation does not describe how the circuit responds to input signals.
DO NOT COPYFrom the point of view of electronic circuit design, it takes a lot of informa-
tion to describe the precise electrical behavior of a circuit. However, since the
inputs of a digital logic circuit can be viewed as taking on only discrete 0 and 1
values, the circuit’s “logical” operation can be described with a table that ignores
DO NOT COPYelectrical behavior and lists only discrete 0 and 1 values.
Inputs Output
F
X
Y
DO NOT COPYZ
logic circuit Figure 3-1
“Black box” representation
of a three-input, one-output
logic circuit.
Copyright © 1999 by John F. Wakerly Copying Prohibited
78 Chapter 3 Digital Circuits
combinational circuit
DO NOT COPYtruthtable
A logic circuit whose outputs depend only on its current inputs is called a
combinational circuit. Its operation is fully described by a truth table that lists
all combinations of input values and the output value(s) produced by each one.
Table 3-2 is the truth table for a logic circuit with three inputs X, Y, and Z and a
DO NOTsingle output F. COPYX Y Z F
Table 3-2 0000
Truth table for a
combinational logic COPY0 0 1 1
0100
DO NOTcircuit. 0110
1000
DO NOT COPY1 0 1 0
1101
1111
A circuit with memory, whose outputs depend on the current input and the
sequential circuit
DO NOT COPYstatetable
sequence of past inputs, is called a sequential circuit. The behavior of such a cir-
cuit may be described by a state table that specifies its output and next state as
functions of its current state and input. Sequential circuits will be introduced in
\chapref{SeqPrinc}.
As we’ll show in Section 4.1, just three basic logic functions, AND, OR,
and NOT, can be used to build any combinational digital logic circuit. Figure 3-2
shows the truth tables and symbols for logic “gates” that perform these func-
DO NOT COPYtions. The symbols and truth tables for AND and OR may be extended to gates
with any number of inputs. The gates’ functions are easily defined in words:
AND gate NOT COPY• An AND gate produces a 1 output if and only if all of its inputs are 1.
OR gate
• An OR gate produces a 1 if and only if one or more of its inputs are 1.
DONOT gate • A NOT gate, usually called an inverter, produces an output value that is the
inverter opposite of its input value.
X X X OR Y
(b) Y
DO NOT COPY(a) Y
X AND Y (c) X NOT X
X•Y X+Y X′
Figure 3-2
Basic logic elements: 00
(a) AND; (b) OR;
NOT COPY0 1
DO(c) NOT(inverter). X Y X AND Y X Y X OR Y X NOT X
0 00 0 01
0 01 1 10
10 0 10 1
11 1 11 1
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.1 Logic Signals and Gates 79
X X NAND Y X X NOR Y
(X • Y)′ (b) Y (X + Y)′
DO NOT COPY(a) Y
X Y X NAND Y X Y X NOR Y Figure 3-3
Inverting gates:
DO0 (a) NAND; (b) NOR.
0 NOT COPY0 1 00 1
1 01 0
1 11 10 0
01
10 11 0
The circle on the inverter symbol’s output is called an inversion bubble, and is inversion bubble
used in this and other gate symbols to denote “inverting” behavior.
DO NOT COPYNotice that in the definitions of AND and OR functions, we only had to
state the input conditions for which the output is 1, because there is only one pos-
sibility when the output is not 1—it must be 0.
Two more logic functions are obtained by combining NOT with an AND or
OR function in a single gate. Figure 3-3 shows the truth tables and symbols for
DO NOT COPYthese gates; Their functions are also easily described in words:
• A NAND gate produces the opposite of an AND gate’s output, a 0 if and NAND gate
only if all of its inputs are 1.
• A NOR gate produces the opposite of an OR gate’s output, a 0 if and only NOR gate
DO NOT COPYif one or more of its inputs are 1.
As with AND and OR gates, the symbols and truth tables for NAND and NOR
may be extended to gates with any number of inputs.
Figure 3-4 is a logic circuit using AND, OR, and NOT gates that functions
DO NOT COPYaccording to the truth table of Table 3-2. In Chapter 4 you’ll learn how to go
from a truth table to a logic circuit, and vice versa, and you’ll also learn about the
switching-algebra notation used in Figures 3-2 through 3-4.
Real logic circuits also function in another analog dimension—time. For
example, Figure 3-5 is a timing diagram that shows how the circuit of Figure 3-4
DO NOT COPYmight respond to a time-varying pattern of input signals. The timing diagram
timing diagram
shows that the logic signals do not change between 0 and 1 instantaneously, and
also that there is a lag between an input change and the corresponding output
DO NOT COPYX X•Y
Y
Figure 3-4
Logic circuit with the
DO NOT COPYX′
F truth table of
Table 3-2.
X • Y + X′ • Y′ • Z
Y′ X′ • Y • Z
Z
Copyright © 1999 by John F. Wakerly Copying Prohibited
80 Chapter 3 Digital Circuits
DO XNOT COPY
Y
Figure 3-5 Z
Timing diagram for aF
DO NOT COPYlogiccircuit.
TIME
change. Later in this chapter, you’ll learn some of the reasons for this timing
DO NOT COPYbehavior, and how it is specified and handled in real circuits. And once again,
you’ll learn in a later chapter how this analog timing behavior can be generally
ignored in most sequential circuits, and instead the circuit can be viewed as mov-
ing between discrete states at precise intervals defined by a clock signal.
DO NOT COPYThus, even if you know nothing about analog electronics, you should be
able to understand the logical behavior of digital circuits. However, there comes
a time in design and debugging when every digital logic designer must tempo-
rarily throw out “the digital abstraction” and consider the analog phenomena
that limit or disrupt digital performance. The rest of this chapter prepares you for
DO NOT COPYthat day by discussing the electrical characteristics of digital logic circuits.
THERE’S HOPE If all of this electrical “stuff” bothers you, don’t worry, at least for now. The rest of
FOR NON-EE’S this book is written to be as independent of this stuff as possible. But you’ll need it
DO NOT COPYlater, if you ever have to design and build digital systems in the real world.
DO NOT COPY3.2 Logic Families
There are many, many ways to design an electronic logic circuit. The first elec-
trically controlled logic circuits, developed at Bell Laboratories in 1930s, were
based on relays. In the mid-1940s, the first electronic digital computer, the Eni-
ac, used logic circuits based on vacuum tubes. The Eniac had about 18,000 tubes
DO NOT COPYand a similar number of logic gates, not a lot by today’s standards of micropro-
cessor chips with tens of millions of transistors. However, the Eniac could hurt
you a lot more than a chip could if it fell on you—it was 100 feet long, 10 feet
high, 3 feet deep, and consumed 140,000 watts of power!
The inventions of the semiconductor diode and the bipolar junction tran-
sistor allowed the development of smaller, faster, and more capable computers
semiconductor diode
DO NOT COPYbipolarjunction
transistor in the late 1950s. In the 1960s, the invention of the integrated circuit (IC)
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.2 Logic Families 81
allowed multiple diodes, transistors, and other components to be fabricated on a integrated circuit (IC)
single chip, and computers got still better.
DO NOT COPYThe 1960s also saw the introduction of the first integrated-circuit logic
families. A logic family is a collection of different integrated-circuit chips that logic family
have similar input, output, and internal circuit characteristics, but that perform
different logic functions. Chips from the same family can be interconnected to
perform any desired logic function. On the other hand, chips from differing fam-
DO NOT COPYilies may not be compatible; they may use different power-supply voltages or
may use different input and output conditions to represent logic values.
The most successful bipolar logic family (one based on bipolar junction
transistors) is transistor-transistor logic (TTL). First introduced in the 1960s,
TTL now is actually a family of logic families that are compatible with each
DO NOT COPYother but differ in speed, power consumption, and cost. Digital systems can mix
bipolar logic family
transistor-transistor
logic (TTL)
components from several different TTL families, according to design goals and
constraints in different parts of the system. Although TTL was largely replaced
by CMOS in the 1990s, you’re still likely to encounter TTL components in aca-
DO NOT COPYdemic labs; therefore, we introduce TTL families in Section 3.10.
Ten years before the bipolar junction transistor was invented, the principles
of operation were patented for another type of transistor, called the metal-oxide metal-oxide
semiconductor field effect transistor (MOSFET), or simply MOS transistor.
However, MOS transistors were difficult to fabricate in the early days, and it
DO NOT COPYwasn’t until the 1960s that a wave of developments made MOS-based logic and
semiconductor field
effect transistor
(MOSFET)
memory circuits practical. Even then, MOS circuits lagged bipolar circuits con- MOS transistor
siderably in speed, and were attractive only in selected applications because of
their lower power consumption and higher levels of integration.
Beginning in the mid-1980s, advances in the design of MOS circuits, in
DO NOT COPYparticular complementary MOS (CMOS) circuits, vastly increased their perfor- complementary MOS
mance and popularity. By far the majority of new large-scale integrated circuits, (CMOS)
such as microprocessors and memories, use CMOS. Likewise, small- to medi-
um-scale applications, for which TTL was once the logic family of choice, are
now likely to use CMOS devices with equivalent functionality but higher speed
DO NOT COPYand lower power consumption. CMOS circuits now account for the vast majority
of the worldwide IC market.
CMOS logic is both the most capable and the easiest to understand com-
mercial digital logic technology. Beginning in the next section, we describe the
basic structure of CMOS logic circuits and introduce the most commonly used
DO NOT COPYcommercial CMOS logic families.
GREEN STUFF Nowadays, the acronym “MOS” is usually spoken as “moss,” rather than spelled out.
DO NOT COPYAnd “CMOS” has always been spoken as “sea moss.”
Copyright © 1999 by John F. Wakerly Copying Prohibited
82 Chapter 3 Digital Circuits
As a consequence of the industry’s transition from TTL to CMOS over a
long period of time, many CMOS families were designed to be somewhat com-
DO NOT COPYpatible with TTL. In Section 3.12, we show how TTL and CMOS families can
be mixed within a single system.
3.3 CMOS Logic
DO NOT COPYThe functional behavior of a CMOS logic circuit is fairly easy to understand,
even if your knowledge of analog electronics is not particularly deep. The basic
(and typically only) building blocks in CMOS logic circuits are MOS transis-
tors, described shortly. Before introducing MOS transistors and CMOS logic
DO NOT COPYcircuits, we must talk about logic levels.
3.3.1 CMOS Logic Levels
Abstract logic elements process binary digits, 0 and 1. However, real logic cir-
cuits process electrical signals such as voltage levels. In any logic circuit, there
is a range of voltages (or other circuit conditions) that is interpreted as a logic 0,
DO NOT COPYand another, nonoverlapping range that is interpreted as a logic 1.
A typical CMOS logic circuit operates from a 5-volt power supply. Such a
circuit may interpret any voltage in the range 0–1.5 V as a logic 0, and in the
range 3.5–5.0 V as a logic 1. Thus, the definitions of LOW and HIGH for 5-volt
DO NOT COPYCMOS logic are as shown in Figure 3-6. Voltages in the intermediate range
(1.5–3.5 V)are not expected to occur except during signal transitions, and yield
undefined logic values (i.e., a circuit may interpret them as either 0 or 1). CMOS
circuits using other power supply voltages, such as 3.3 or 2.7 volts, partition the
DO NOT COPYvoltagerangesimilarly.
3.3.2 MOS Transistors
A MOS transistor can be modeled as a 3-terminal device that acts like a voltage-
controlled resistance. As suggested by Figure 3-7, an input voltage applied to
one terminal controls the resistance between the remaining two terminals. In
DO NOT COPYdigital logic applications, a MOS transistor is operated so its resistance is always
either very high (and the transistor is “off”) or very low (and the transistor is
DO NOT COPY“on”). 5.0 V
Figure 3-6 Logic 1 (HIGH)
DO NOTLogic levels for typical COPY3.5V undefined
logic level
CMOS logic circuits. 1.5 V
Logic 0 (LOW)
0.0 V
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.3 CMOS Logic 83
DO NOT COPYVIN
Figure 3-7
The MOS transistor as
a voltage-controlled
resistance.
There are two types of MOS transistors, n-channel and p-channel; the
DO NOT COPYnames refer to the type of semiconductor material used for the resistance-con-
trolled terminals. The circuit symbol for an n-channel MOS (NMOS) transistor n-channel MOS
is shown in Figure 3-8. The terminals are called gate, source, and drain. (Note (NMOS) transistor
DO NOT COPYhigher voltage than the source.
that the “gate” of a MOS transistor has nothing to do with a “logic gate.”) As you gate
might guess from the orientation of the circuit symbol, the drain is normally at a source
drain
Voltage-controlled resistance: Figure 3-8
increase Vgs ==> decrease Rds Circuit symbol for an
n-channel MOS (NMOS)
transistor.
gate drain
+
DO NOT COPYVgs
source
Note: normally, Vgs ≥0
−
The voltage from gate to source (Vgs) in an NMOS transistor is normally
zero or positive. If Vgs = 0, then the resistance from drain to source (Rds) is very
DO NOT COPYhigh, on the order of a megohm (106 ohms) or more. As we increase Vgs (i.e.,
increase the voltage on the gate), Rds decreases to a very low value, 10 ohms or
less in some devices.
The circuit symbol for a p-channel MOS (PMOS) transistor is shown in
Figure 3-9. Operation is analogous to that of an NMOS transistor, except that the
DO NOT COPYsource is normally at a higher voltage than the drain, and Vgs is normally zero or
p-channel MOS
(PMOS) transistor
negative. If Vgs is zero, then the resistance from source to drain (Rds) is very high.
As we algebraically decrease Vgs (i.e., decrease the voltage on the gate), Rds
decreases to a very low value.
DO NOT COPYThe gate of a MOS transistor has a very high impedance. That is, the gate
is separated from the source and the drain by an insulating material with a very
high resistance. However, the gate voltage creates an electric field that enhances
or retards the flow of current between source and drain. This is the “field effect”
in the “MOSFET” name.
DO NOT COPYRegardless of gate voltage, almost no current flows from the gate to source,
or from the gate to drain for that matter. The resistance between the gate and the
Vgs
DO NOT COPY+
− Figure 3-9
Voltage-controlled resistance: Circuit symbol for a
source decrease Vgs ==> decrease Rds
gate drain p-channel MOS (PMOS)
transistor.
Note: normally, Vgs ≤0
Copyright © 1999 by John F. Wakerly Copying Prohibited
84 Chapter 3 Digital Circuits
IMPEDANCE VS. Technically, there’s a difference between “impedance” and “resistance,” but electri-
DO NOT COPYRESISTANCE cal engineers often use the terms interchangeably. So do we in this text.
other terminals of the device is extremely high, well over a megohm. The small
DO NOT COPYamount of current that flows across this resistance is very small, typically less
leakage current than one microampere (µA, 10−6 A), and is called a leakage current.
The MOS transistor symbol itself reminds us that there is no connection
between the gate and the other two terminals of the device. However, the gate of
a MOS transistor is capacitively coupled to the source and drain, as the symbol
DO NOT COPYmight suggest. In high-speed circuits, the power needed to charge and discharge
this capacitance on each input-signal transition accounts for a nontrivial portion
of a circuit’s power consumption.
3.3.3 Basic CMOS Inverter Circuit
DO NOT COPYNMOS and PMOS transistors are used together in a complementary way to form
CMOS logic CMOS logic. The simplest CMOS circuit, a logic inverter, requires only one of
each type of transistor, connected as shown in Figure 3-10(a). The power supply
voltage, VDD, typically may be in the range 2–6 V, and is most often set at 5.0 V
for compatibility with TTL circuits.
DO NOT COPYIdeally, the functional behavior of the CMOS inverter circuit can be char-
acterized by just two cases tabulated in Figure 3-10(b):
DO 1. VIN is 0.0 V. In this case, the bottom, n-channel transistor Q1 is off, since
its Vgs is 0, but the top, p-channel transistor Q2 is on, since its Vgs is a large
NOT COPYnegative value (−5.0 V). Therefore, Q2 presents only a small resistance
between the power supply terminal (VDD, +5.0 V) and the output terminal
DO
NOT COPY(VOUT), and the output voltage is 5.0 V.
Figure 3-10
(a) VDD = +5.0 V
CMOS inverter: NOT COPYQ2 VOUT
(a) circuit diagram; (p-channel)
(b) functional behavior; (b) VIN Q1 Q2
DO(c) logic symbol. 0.0 (L) off on 5.0 (H)
VOUT 5.0 (H) on off 0.0 (L)
Q1 OUT
VIN (n-channel)
DO NOT COPY(c) IN
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.3 CMOS Logic 85
2. VIN is 5.0 V. Here, Q1 is on, since its Vgs is a large positive value (+5.0 V),
but Q2 is off, since its Vgs is 0. Thus, Q1 presents a small resistance
DO NOT COPYbetween the output terminal and ground, and the output voltage is 0 V.
With the foregoing functional behavior, the circuit clearly behaves as a logical
inverter, since a 0-volt input produces a 5-volt output, and vice versa
Another way to visualize CMOS operation uses switches. As shown in
Figure 3-11(a), the n-channel (bottom) transistor is modeled by a normally-open
DO NOT COPYswitch, and the p-channel (top) transistor by a normally-closed switch. Applying
a HIGH voltage changes each switch to the opposite of its normal state, as shown
in (b).
DO NOT COPY(a)
VDD = +5.0 V (b) VDD = +5.0 V Figure 3-11
Switch model for
CMOS inverter: (a)
DOVIN = L NOTVOUT = H COPYVOUT = L
LOW input; (b) HIGH
input.
VIN = H
DO NOT COPY
The switch model gives rise to a way of drawing CMOS circuits that makes
their logical behavior more readily apparent. As shown in Figure 3-12, different
DO NOT COPYsymbols are used for the p- and n-channel transistors to reflect their logical
behavior. The n-channel transistor (Q1) is switched “on,” and current flows
between source and drain, when a HIGH voltage is applied to its gate; this seems
DO NOT COPYVDD=+5.0V
natural enough. The p-channel transistor (Q2) has the opposite behavior. It is
Figure 3-12
CMOS inverter logical
Q2
operation.
DO NOT COPY(p-channel)
on when
VIN is low
VOUT
Q1
(n-channel)
DO NOT COPYVIN on when
VIN is high
Copyright © 1999 by John F. Wakerly Copying Prohibited
86 Chapter 3 Digital Circuits
WHAT’S IN A The “DD” in the name “VDD” refers to the drain terminal of an MOS transistor. This
DO NOT COPYNAME? may seem strange, since in the CMOS inverter VDD is actually connected to the
source terminal of a PMOS transistor. However, CMOS logic circuits evolved from
NMOS logic circuits, where the supply was connected to the drain of an NMOS tran-
sistor through a load resistor, and the name “VDD” stuck. Also note that ground is
sometimes referred to as “VSS” in CMOS and NMOS circuits. Some authors and
DO NOT COPYmost circuit manufacturers use “VCC” as the symbol for the CMOS supply voltage,
since this name is used in TTL circuits, which historically preceded CMOS. To get
you used to both, we’ll start using “VCC” in Section 3.4.
DO NOT COPY“on” when a LOW voltage is applied; the inversion bubble on its gate indicates
this inverting behavior.
3.3.4 CMOS NAND and NOR Gates
Both NAND and NOR gates can be constructed using CMOS. A k-input
DO NOT COPYgate uses k p-channel and k n-channel transistors. Figure 3-13 shows a 2-input
CMOS NAND gate. If either input is LOW, the output Z has a low-impedance
connection to VDD through the corresponding “on” p-channel transistor, and the
path to ground is blocked by the corresponding “off” n-channel transistor. If both
inputs are HIGH, the path to VDD is blocked, and Z has a low-impedance connec-
DO NOT COPYtion to ground. Figure 3-14 shows the switch model for the NAND gate’s
operation.
Figure 3-15 shows a CMOS NOR gate. If both inputs are LOW, the output
Z has a low-impedance connection to VDD through the “on” p-channel transis-
DO NOT COPYtors, and the path to ground is blocked by the “off” n-channel transistors. If
either input is HIGH, the path to VDD is blocked, and Z has a low-impedance con-
nection to ground.
Figure 3-13
(a) VDD
DO NOT COPYCMOS2-input
NAND gate: (b) A B Q1 Q2 Q3 Q4 Z
(a) circuit diagram; NOTQ2 Q4 COPYL L off on off on H
(b) function table; A Q1 L H off on on off H
Z H L on off off on H
DO(c) logic symbol.
H H on off on off L
DO NOT COPYB Q3
A Z
(c)
B
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.3 CMOS Logic 87
NAND VS. NOR CMOS NAND and NOR gates do not have identical performance. For a given silicon
DO NOT COPYarea, an n-channel transistor has lower “on” resistance than a p-channel transistor.
Therefore, when transistors are put in series, k n-channel transistors have lower “on”
resistance than do k p-channel ones. As a result, a k-input NAND gate is generally
DO NOT COPYfaster than and preferred over a k-input NOR gate.
(b) VDD
DO NOT COPY(a) VDD
(c) VDD
DO NOT COPYZ=H Z=H Z=L
A=L A=H A=H
DO NOT COPYB=LB=L B=H
Figure 3-14 Switch model for CMOS 2-input NAND gate: (a) both inputs LOW;
DO NOT COPY(b) one input HIGH; (c) both inputs HIGH.
DO NOT COPY(a) VDD
A Q2 (b) A B Q1 Q2 Q3 Q4 Z Figure 3-15
CMOS 2-input
DO NOT COPYB Q4
LL off on off on H NOR gate:
LH off on on off L (a) circuit diagram;
(b) function table;
HL on off off on L (c) logic symbol.
HH on off on off L
Z
DO NOT COPYQ1 Q3 A Z
(c) B
Copyright © 1999 by John F. Wakerly Copying Prohibited
88 Chapter 3 Digital Circuits
DO NOT COPY(a) VDD
(b)
A B C Q1 Q2 Q3 Q4 Q5 Q6 Z
Q2 Q4 Q6 L L L off on off on off on H
COPYL L H H
LHL H
L HH H
HL L H
HLH H
DO NOTZ off on off on on off
off on on off off on
off on on off on off
on off off on off on
on off off on on off
A Q1 H H L on off on off off on H
DOB Q3 NOT COPYH H H on off on off on off L
(c) A
BZ
DOC Q5 NOT CCOPY
Figure 3-16 CMOS 3-input NAND gate: (a) circuit diagram;
(b) function table; (c) logic symbol.
3.3.5 Fan-In
DO NOT COPYThe number of inputs that a gate can have in a particular logic family is called
fan-in the logic family’s fan-in. CMOS gates with more than two inputs can be
obtained by extending series-parallel designs on Figures 3-13 and 3-15 in the
obvious manner. For example, Figure 3-16 shows a 3-input CMOS NAND gate.
In principle, you could design a CMOS NAND or NOR gate with a very
DO NOT COPYlarge number of inputs. In practice, however, the additive “on” resistance of
series transistors limits the fan-in of CMOS gates, typically to 4 for NOR gates
and 6 for NAND gates.
As the number of inputs is increased, CMOS gate designers may compen-
sate by increasing the size of the series transistors to reduce their resistance and
DO NOT COPYthe corresponding switching delay. However, at some point this becomes ineffi-
cient or impractical. Gates with a large number of inputs can be made faster and
DO NOT COPYFigure 3-17
smaller by cascading gates with fewer inputs. For example, Figure 3-17 shows
I1
I1
I2
Logic diagram I3 I2
equivalent to theI4 I3
internal structure of COPYOUT
an 8-input CMOSI5 I4 OUT
I6 I5
DO NOTNAND gate. I6
I7 I7
I8 I8
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.3 CMOS Logic 89
DO NOT COPY(a) VDD=+5.0V
(b) A Q1 Q2 Q3 Q4 Z
Q2 Q4
DO NOT COPYQ1 Q3
L off on on off L Figure 3-18
A Z H on off off on H CMOS noninverting
buffer:
(a) circuit diagram;
(c) A Z (b) function table;
DO NOT COPY(c)logicsymbol.
the logical structure of an 8-input CMOS NAND gate. The total delay through a
4-input NAND, a 2-input NOR, and an inverter is typically less than the delay of
a one-level 8-input NAND circuit.
DO NOT COPY3.3.6 Noninverting Gates
In CMOS, and in most other logic families, the simplest gates are inverters, and
the next simplest are NAND gates and NOR gates. A logical inversion comes “for
free,” and it typically is not possible to design a noninverting gate with a smaller
number of transistors than an inverting one.
DO NOT COPYCMOS noninverting buffers and AND and OR gates are obtained by con-
necting an inverter to the output of the corresponding inverting gate. Combining
Figure 3-15(a) with an inverter yields an OR gate. Thus, Figure 3-18 shows a
noninverting buffer and Figure 3-19 shows an AND gate.
DO NOT COPYFigure 3-19 CMOS 2-input AND gate: (a) circuit diagram; (b) function table;
(c) logic symbol.
DO(a) VDD NOT COPY
Q2 (b) A B Q1 Q2 Q3 Q4 Q5 Q6 Z
DO Q4 Q6
A Q1
NOT COPYL L off on off on on off L
L H off on on off on off L
H L on off off on on off L
Z H H on off on off off on H
DO NOT COPYB Q3
A Z
Q5 (c) B
Copyright © 1999 by John F. Wakerly Copying Prohibited
90 Chapter 3 Digital Circuits
VDD
DO NOT COPY(a)
(b) A B C D Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Z
A Q2 Q4 L L L L off on off on off on off on H
B
DO NOT COPYQ6 Q8
L L LH off on off on off on on off H
L LHL off on off on on off off on H
L LHH off on off on on off on off L
LHL L off on on off off on off on H
LHLH off on on off off on on off H
L H H L off on on off on off off on H
Z L H H H off on on off on off on off L
DO NOT COPYC Q5 Q3
H L L L on off off on off on off on H
H L L H on off off on off on on off H
H L H L on off off on on off off on H
H L H H on off off on on off on off L
H H L L on off on off off on off on L
HH L H on off on off off on on off L
HHH L on off on off on off off on L
HHHH on off on off on off on off L
DO NOT COPYD Q7 Q1
Figure 3 -2 0 CMOS AND-OR-INVERT gate: (a) circuit diagram; (b) function tab
3.3.7 CMOS AND-OR-INVERT and OR-AND-INVERT Gates
DO NOT COPYCMOS circuits can perform two levels of logic with just a single “level” of tran-
sistors. For example, the circuit in Figure 3-20(a) is a two-wide, two-input
AND-OR-INVERT
DO NOT COPY(AOI)gate
CMOS AND-OR-INVERT (AOI) gate. The function table for this circuit is shown
in (b) and a logic diagram for this function using AND and NOR gates is shown
in Figure 3-21. Transistors can be added to or removed from this circuit to obtain
an AOI function with a different number of ANDs or a different number of inputs
per AND.
The contents of each of the Q1–Q8 columns in Figure 3-20(b) depends
only on the input signal connected to the corresponding transistor’s gate. The
DO NOT COPYlast column is constructed by examining each input combination and determin-
ing whether Z is connected to VDD or ground by “on” transistors for that input
combination. Note that Z is never connected to both VDD and ground for any
DO NOT COPYinput combination; in such a case the output would be a non-logic value some-
Figure 3-21 A
DO D
NOTLogic diagram for CMOS COPYB
AND-OR-INVERT gate. Z
C
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.3 CMOS Logic 91
VDD NOT COPY(b) A B C D Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Z
Q6 L L L L off on off on off on off on H
DO(a)
A Q2 NOT COPYL L L H off on off on off on on off H
DOB Q4 L L H L off on off on on off off on H
DOC Q5
D Q8 L L H H off on off on on off on off H
L H L L off on on off off on off on H
DOQ1
Z L H L H off on on off off on on off L
L H H L off on on off on off off on L
NOT COPYL H H H off on on off on off on off L
Q7 H L L L on off off on off on off on H
H L L H on off off on off on on off L
H L H L on off off on on off off on L
H L H H on off off on on off on off L
H H L L on off on off off on off on H
H H L H on off on off off on on off L
H H H L on off on off on off off on L
NOT COPYQ3
H H H H on off on off on off on off L
Figure 3 -2 2 CMOS OR-AND-INVERT gate: (a) circuit diagram; (b) function table.
DO NOT COPYwhere between LOW and HIGH, and the output structure would consume
excessive power due to the low-impedance connection between VDD and ground.
A circuit can also be designed to perform an OR-AND-INVERT function.
For example, Figure 3-22(a) is a two-wide, two-input CMOS OR-AND-INVERT OR-AND-INVERT
(OAI ) gate. The function table for this circuit is shown in (b); the values in each (AOI) gate
DO NOT COPYcolumn are determined just as we did for the CMOS AOI gate. A logic diagram
for the OAI function using OR and NAND gates is shown in Figure 3-23.
The speed and other electrical characteristics of a CMOS AOI or OAI gate
are quite comparable to those of a single CMOS NAND or NOR gate. As a result,
these gates are very appealing because they can perform two levels of logic
DO NOT COPY(AND-OR or OR-AND) with just one level of delay. Most digital designers don’t
bother to use AOI gates in their discrete designs. However, CMOS VLSI devices
often use these gates internally, since many HDL synthesis tools can automati-
DO NOT COPYcally convert AND/OR logic into AOI gates when appropriate.
A Figure 3-23
B Logic diagram for CMOS
OR-AND-INVERT gate.
Z
DO NOT COPYC
D
Copyright © 1999 by John F. Wakerly Copying Prohibited
92 Chapter 3 Digital Circuits
3.4 Electrical Behavior of CMOS Circuits
DO NOT COPYThe next three sections discuss electrical, not logical, aspects of CMOS circuit
operation. It’s important to understand this material when you design real cir-
cuits using CMOS or other logic families. Most of this material is aimed at
DO NOT COPYengineeringdesign
providing a framework for ensuring that the “digital abstraction” is really valid
for a given circuit. In particular, a circuit or system designer must provide in a
number of areas adequate engineering design margins—insurance that the cir-
margins cuit will work properly even under the worst of conditions.
3.4.1 Overview
The topics that we discuss in Sections 3.5–3.7 include the following:
DO NOT COPY• Logic voltage levels. CMOS devices operating under normal conditions are
guaranteed to produce output voltage levels within well-defined LOW and
DO
DO NOT COPYHIGH ranges. And they recognize LOW and HIGH input voltage levels over
DO somewhat wider ranges. CMOS manufacturers specify these ranges and
DO operating conditions very carefully to ensure compatibility among
different devices in the same family, and to provide a degree of
interoperability (if you’re careful) among devices in different families.
NOT COPY• DC noise margins. Nonnegative DC noise margins ensure that the highest
LOW voltage produced by an output is always lower than the highest volt-
age that an input can reliably interpret as LOW, and that the lowest HIGH
voltage produced by an output is always higher than the lowest voltage that
NOT COPYan input can reliably interpret as HIGH. A good understanding of noise
margins is especially important in circuits that use devices from a number
of different families.
• Fanout. This refers to the number and type of inputs that are connected to
a given output. If too many inputs are connected to an output, the DC noise
NOT COPYmargins of the circuit may be inadequate. Fanout may also affect the speed
at which the output changes from one state to another.
• Speed. The time that it takes a CMOS output to change from the LOW state
to the HIGH state, or vice versa, depends on both the internal structure of
DO NOT COPYthe device and the characteristics of the other devices that it drives, even to
the extent of being affected by the wire or printed-circuit-board traces con-
nected to the output. We’ll look at two separate components of “speed”—
transition time and propagation delay.
• Power consumption. The power consumed by a CMOS device depends on
DO
NOT COPYa number of factors, including not only its internal structure, but also the
input signals that it receives, the other devices that it drives, and how often
its output changes between LOW and HIGH.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 3.4 Electrical Behavior of CMOS Circuits 93
• Noise. The main reason for providing engineering design margins is to
ensure proper circuit operation in the presence of noise. Noise can be gen-
DO NOT COPYerated by a number of sources; several of them are listed below, from the
least likely to the (perhaps surprisingly) most likely:
– Cosmic rays.
– Magnetic fields from nearby machinery.
DO NOT COPY– Power-supply disturbances.
– The switching action of the logic circuits themselves.
• Electrostatic discharge. Would you believe that you can destroy a CMOS
device just by touching it?
DO NOT COPY• Open-drain outputs. Some CMOS outputs omit the usual p-channel pull-
up transistors. In the HIGH state, such outputs are effectively a “no-connec-
tion,” which is useful in some applications.
• Three-state outputs. Some CMOS devices have an extra “output enable”
control input that can be used to disable both the p-channel pull-up transis-
DO NOT COPYtors and the n-channel pull-down transistors. Many such device outputs
can be tied together to create a multisource bus, as long as the control logic
is arranged so that at most one output is enabled at a time.
3.4.2 Data Sheets and Specifications
DO NOT COPYThe manufacturers of real-world devices provide data sheets that specify the data sheet
devices’ logical and electrical characteristics. The electrical specifications por-
tion of a minimal data sheet for a simple CMOS device, the 54/74HC00
quadruple NAND gate, is shown in Table 3-3. Different manufacturers typically
specify additional parameters, and they may vary in how they specify even the
DO NOT COPY“standard” parameters shown in the table. Thus, they usually also show the test
circuits and waveforms that they use to define various parameters, for example
as shown in Figure 3-24. Note that this figure contains information for some
parameters in addition to those used with the 54/74HC00.
DO NOT COPYMost of the terms in the data sheet and the waveforms in the figure are
probably meaningless to you at this point. However, after reading the next three
sections you should know enough about the electrical characteristics of CMOS
circuits that you’ll be able to understand the salient points of this or any other
data sheet. As a logic designer, you’ll need this knowledge to create reliable and
DO NOT COPYrobust real-world circuits and systems.
DON’T BE AFRAID Computer science students and other non-EE readers should not have undue fear of
the material in the next three sections. Only a basic understanding of electronics, at
DO NOT COPYabout the level of Ohm’s law, is required.
Copyright © 1999 by John F. Wakerly Copying Prohibited
94 Chapter 3 Digital Circuits
Ta b l e 3 - 3 Manufacturer’s data sheet for a typical CMOS device,
the 54/74HC00 quad NAND gate.
DO NOT COPYDC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
The following conditions apply unless otherwise specified:
Commercial: TA = −40°C to +85°C, VCC = 5.0V±5%; Military: TA = −55°C to +125°C, VCC = 5.0V±10%
DO NOT COPYSym.
Parameter Test Conditions(1) Min. Typ.(2) Max. Unit
VIH Input HIGH level Guaranteed logic HIGH level 3.15 — — V
VIL Input LOW level Guaranteed logic LOW level COPY— — 1.35 V
DO NOTIIL Input LOW current VCC = Max., VI = 0 V
IIH Input HIGH current VCC = Max., VI = VCC —— 1 µA
— — −1 µA
VIK Clamp diode voltage VCC = Min., IN = −18 mA — −0.7 −1.2 V
DO NOT COPYVOH
IIOS Short-circuit current VCC = Max.,(3) VO = GND — — −35 mA
V
Output HIGH voltage VCC = Min., IOH = −20 µA 4.4 4.499 — V
VIN = VIL IOH = −4 mA
3.84 4.3 —
VCC = Min. IOL = 20 µA — .001 0.1 V
VIN = VIH IOL = 4 mA
DO NOT COPYICC Quiescent power VCC = Max.
VOL Output LOW voltage
0.17 0.33
— 2 10 µA
supply current VIN = GND or VCC, IO = 0
DO NOT COPYSym.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE, CL = 50 pF
Parameter (4) Test Conditions Min. Typ. Max. Unit
tPD Propagation delay A or B to Y — 9 19 ns
CI Input capacitance VIN = 0 V No load COPY— 3 10 pF
Cpd Power dissipation capacitance per gate — 22 — pF
DO NOTNOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics.
2. Typical values are at VCC = 5.0 V, +25°C ambient.
3. Not more than one output should be shorted at a time. Duration of short-circuit test should not exceed one second.
DO NOT COPY4. This parameter is guaranteed but not tested.
WHAT’S IN A Two different prefixes, “74” and “54,” are used in the part numbers of CMOS and
NUMBER? TTL devices. These prefixes simply distinguish between commercial and military
DO NOT COPYversions. A 74HC00 is the commercial part and the 54HC00 is the military version.
Copyright © 1999 by John F. Wakerly Copying Prohibited
The words you are searching are inside this book. To get more targeted content, please make full-text search by clicking here.
digital design digital design digital design principles & practices ( PDFDrive ) (1)
Discover the best professional documents and content resources in AnyFlip Document Base.
Search
digital design digital design digital design principles & practices ( PDFDrive ) (1)
- 1 - 50
- 51 - 100
- 101 - 150
- 151 - 200
- 201 - 250
- 251 - 300
- 301 - 350
- 351 - 400
- 401 - 450
- 451 - 500
- 501 - 550
- 551 - 600
- 601 - 650
- 651 - 700
- 701 - 750
- 751 - 796
Pages: