Section *5.10 Adders, Subtractors, and ALUs 395
x i hsi
DO NOT COPYyi ci si
x i−1
x0 NOT COPYFigure 5-88
Carry Structure of one
DOyi–1 Lookahead
Logic
y0 stage of a carry
c0 lookahead adder.
DO NOT COPYCorresponding to these definitions, we can write logic equations for a carry-
generate signal, gi, and a carry-propagate signal, pi, for each stage of a carry loo-
kahead adder:
gi = xi ⋅ yi
DO NOT COPYpi = xi+yi
That is, a stage unconditionally generates a carry if both of its addend bits are 1,
and it propagates carries if at least one of its addend bits is 1. The carry output
of a stage can now be written in terms of the generate and propagate signals:
DO NOT COPYci+1 = gi+pi⋅ci
To eliminate carry ripple, we recursively expand the ci term for each stage, and
multiply out to obtain a 2-level AND-OR expression. Using this technique, we
can obtain the following carry equations for the first four adder stages:
DO NOT COPYc1 = g0+p0⋅c0
c2 = g1 + p1 ⋅ c1
= g1 + p1 ⋅ (g0 + p0 ⋅ c0)
= g1 + p1 ⋅ g0 + p1 ⋅ p0 ⋅ c0
DO NOT COPYc3 = g2+p2⋅c2
= g2 + p2 ⋅ (g1 + p1 ⋅ g0 + p1 ⋅ p0 ⋅ c0)
= g2 + p2 ⋅ g1 + p2 ⋅ p1 ⋅ g0 + p2 ⋅ p1 ⋅ p0 ⋅ c0
c4 = g3 + p3 ⋅ c3
DO NOT COPY= g3 + p3 ⋅ (g2 + p2 ⋅ g1 + p2 ⋅ p1 ⋅ g0 + p2 ⋅ p1 ⋅ p0 ⋅ c0)
= g3 + p3 ⋅ g2 + p3 ⋅ p2 ⋅ g1 + p3 ⋅ p2 ⋅ p1 ⋅ g0 + p3 ⋅ p2 ⋅ p1 ⋅ p0 ⋅ c0
Each equation corresponds to a circuit with just three levels of delay—one for
the generate and propagate signals, and two for the sum-of-products shown. A
DO NOT COPYcarry lookahead adder uses three-level equations such as these in each adder
carry lookahead adder
stage for the block labeled “carry lookahead” in Figure 5-88. The sum output for
Copyright © 1999 by John F. Wakerly Copying Prohibited
396 Chapter 5 Combinational Logic Design Practices
a stage is produced by combining the carry bit with the two addend bits for the
stage as we showed in the figure. In the next subsection, we’ll study some
DO NOT COPYcommercial MSI adders and ALUs that use carry lookahead.
*5.10.5 MSI Adders
74x283
DO NOT COPY74x83
The 74x283 is a 4-bit binary adder that forms its sum and carry outputs with just
a few levels of logic, using the carry lookahead technique. Figure 5-89 is a logic
symbol for the 74x283. The older 74x83 is identical except for its pinout, which
has nonstandard locations for power and ground.
The logic diagram for the ’283, shown in Figure 5-90, has just a few differ-
ences from the general carry-lookahead design that we described in the
preceding subsection. First of all, its addends are named A and B instead of X and
Y; no big deal. Second, it produces active-low versions of the carry-generate (gi ′)
7 C074x283
DO NOT COPY5 A0S0 4
6 B0 and carry-propagate (pi ′) signals, since inverting gates are generally faster than
noninverting ones. Third, it takes advantage of the fact that we can algebraically
manipulate the half-sum equation as follows:
hsi = xi ⊕ yi
3 A1 S1 1
2 B1 S2 13
14 A2
DO NOT COPY15 B2
12 A3 S3 10 = xi ⋅ yi′ + xi′ ⋅ yi
11 B3 NOT COPY= xi ⋅ yi′ + xi ⋅ xi′ + xi′ ⋅ yi + yi ⋅ yi′
DOFigure 5-89C4 9 = (xi + yi) ⋅ (xi′ + yi′)
= (xi + yi) ⋅ (xi ⋅ yi)′
Traditional logic
symbol for the
74x283 4-bit
DO NOT COPYbinaryadder.
= pi ⋅ gi′
Thus, an AND gate with an inverted input can be used instead of an XOR gate to
create each half-sum bit.
Finally, the ’283 creates the carry signals using an INVERT-OR-AND
structure (the DeMorgan equivalent of an AND-OR-INVERT), which has about
the same delay as a single CMOS or TTL inverting gate. This requires some
explaining, since the carry equations that we derived in the preceding subsection
are used in a slightly modified form. In particular, the ci+1 equation uses the term
DO NOT COPYpi ⋅ gi instead of gi. This has no effect on the output, since pi is always 1 when gi
is 1. However, it allows the equation to be factored as follows:
DO NOT COPYci+1 = pi⋅gi+pi⋅ci
= pi ⋅ (gi + ci)
This leads to the following carry equations, which are used by the circuit :
c1 = p0 ⋅ (g0 + c0)
c2 = p1 ⋅ (g1 + c1)
DO NOT COPY= p1⋅ (g1+ p0⋅ (g0+ c0))
= p1 ⋅ (g1 + p0) ⋅ (g1 + g0 + c0)
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 397
DO NOT COPY
(9)
DO NOT COPYC4
(11) g3′
p3′
B3
(12)
DO NOT COPYA3
hs3
(10)
S3
DO NOT COc3 PY
(15) g2′ hs2
B2
DO NOT COPY(14)
A2 (13) S2
p2′
DO NOT COc2 PY
(2) g1′ NOT COPYhs1
NOT (1)
B1 p1′ NOT S1
(3)
DOA1
DO COc1 PY
(6) g0′ COPYhs0
B0
(5)
A0 (4)
p0′ c0
DO(7) c0′ S0
Figure 5-90
C0 Logic diagram for the
74x283 4-bit binary adder.
Copyright © 1999 by John F. Wakerly Copying Prohibited
398 Chapter 5 Combinational Logic Design Practices
c3 = p2 ⋅ (g2 + c2)
= p2 ⋅ (g2 + p1 ⋅ (g1 + p0) ⋅ (g1 + g0 + c0))
DO NOT COPY= p2 ⋅ (g2 + p1) ⋅ (g2 + g1 + p0) ⋅ (g2 + g1 + g0 + c0)
c4 = p3 ⋅ (g3 + c3)
= p3 ⋅ (g3 + p2 ⋅ (g2 + p1) ⋅ (g2 + g1 + p0) ⋅ (g2 + g1 + g0 + c0))
DO NOT COPY= p3 ⋅ (g3 + p2) ⋅ (g3 + g2 + p1) ⋅ (g3 + g2 + g1 + p0) ⋅ (g3 + g2 + g1 + g0 + c0)
If you’ve followed the derivation of these equations and can obtain the same
ones by reading the ’283 logic diagram, then congratulations, you’re up to speed
DO NOT COPYgroup-rippleadder
on switching algebra! If not, you may want to review Sections 4.1 and 4.2.
The propagation delay from the C0 input to the C4 output of the ’283 is
very short, about the same as two inverting gates. As a result, fairly fast group-
ripple adders with more than four bits can be made simply by cascading the
carry outputs and inputs of ’283s, as shown in Figure 5-91 for a 16-bit adder.
The total propagation delay from C0 to C16 in this circuit is about the same as
DO NOT COPYthat of eight inverting gates.
X[15:0]
NOT74x283 COPY74x283
DOY[15:0] 7 C0 S0 4 S0 7 C0 S0 4 S8
C0 X0 5 A0 X8 5 A0
Y0 6 B0 Y8 6 B0
Figure 5-91 S1 S9
A 16-bit group-ripple NOTX1 3 A1 S1 1 COPYX9 3 A1 S1 1
Y1 2 B1 Y9 2 B1
DOadder. X2 14 A2 X10 14 A2
DO Y2 15 B2 Y10 15 B2
DO S2 13 S2 S2 13 S10
DO
X3 12 A3 S3 10 S3 X11 12 A3 S3 10 S11
NOTY3 11 B3 COPYY11 11 B3
C4C4 9 C12C4 9
U1 U3
74x283 74x283
NOT7 C0 S0 4 S4 COPY7 C0 S0 4 S12
X4 5 A0 S1 1 S5 X12 5 A0 S1 1 S13
Y4 6 B0 Y12 6 B0
X5 3 A1 X13 3 A1
Y5 2 B1 Y13 2 B1 S2 13 S14
NOTX6 14 A2 S2 13 S6 COPYX14 14 A2
Y6 15 B2 Y14 15 B2 S3 10 S15
X7 12 A3S3 10 S7 X15 12 A3 C4 9
Y7 11 B3C4 9 C8 Y15 11 B3 C16
U2 U4
S[15:0]
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 399
*5.10.6 MSI Arithmetic and Logic Units
An arithmetic and logic unit (ALU) is a combinational circuit that can perform arithmetic and logic
DO NOT COPYany of a number of different arithmetic and logical operations on a pair of b-bit unit (ALU)
operands. The operation to be performed is specified by a set of function-select
inputs. Typical MSI ALUs have 4-bit operands and three to five function select 74x181
inputs, allowing up to 32 different functions to be performed.
Figure 5-92 is a logic symbol for the 74x181 4-bit ALU. The operation
DO NOT COPYperformed by the ’181 is selected by the M and S3–S0 inputs, as detailed in
Table 5-51. Note that the identifiers A, B, and F in the table refer to the 4-bit
words A3–A0, B3–B0, and F3–F0; and the symbols ⋅ and + refer to logical AND
and OR operations.
The 181’s M input selects between arithmetic and logical operations. When
DO NOT COPYM = 1, logical operations are selected, and each output Fi is a function only of the
corresponding data inputs, Ai and Bi. No carries propagate between stages, and
the CIN input is ignored. The S3–S0 inputs select a particular logical operation;
any of the 16 different combinational logic functions on two variables may be
DO NOT COPYselected.
Ta b l e 5 - 5 1 Functions performed by the 74x181 4-bit ALU. Figure 5-92
Logic symbol for the
74x181 4-bit ALU.
DO NOT COPYInputs Function
S3 S2 S1 S0 M = 0 (arithmetic) M = 1 (logic) 74x181
DO0 0 0 0 NOTF = A minus 1 plus CIN COPYF = A′ 6 S0 G 17
F = A ⋅ B minus 1 plus CIN F = A′ + B′ 5 S1 P 15
0001 F = A ⋅ B′ minus 1 plus CIN F = A′ + B 4 S2
0010 3 S3
0011
F = 1111 plus CIN F = 1111 8M A=B 14
DO0 1 0 0
F = A′ ⋅ B′ 7 CIN
0101 F = B′ 2 A0
0110 F = A ⊕ B′ 1 B0
0111 NOT COPYF = A plus (A + B′) plus CIN 23 A1 F0 9
F = A ⋅ B plus (A + B′) plus CIN F1 10
DO1 0 0 0 F = A minus B minus 1 plus CIN
22 B1
1001 NOT COPYF=A+B′plusCIN F = A + B′
1010 F = A plus (A + B) plus CIN F = A′ ⋅ B 21 A2 F2 11
1011 F = A plus B plus CIN F=A⊕B
F = A ⋅ B′ plus (A + B) plus CIN F=B 20 B2
DO1 1 0 0
19 A3 F3 13
1101
1110 18 B3 COUT 16
F = A + B plus CIN F=A+B
NOTF = A plus A plus CIN COPYF = 0000
F = A ⋅ B plus A plus CIN F = A ⋅ B′
F = A ⋅ B′ plus A plus CIN F=A⋅B
1111 F = A plus CIN F=A
Copyright © 1999 by John F. Wakerly Copying Prohibited
400 Chapter 5 Combinational Logic Design Practices
When M = 0, arithmetic operations are selected, carries propagate between
the stages, and CIN is used as a carry input to the least significant stage. For
DO NOT COPYoperations larger than four bits, multiple ’181 ALUs may be cascaded like the
group-ripple adder in the Figure 5-91, with the carry-out (COUT) of each ALU
connected to the carry-in (CIN) of the next most significant stage. The same
function-select signals (M, S3–S0) are applied to all the ’181s in the cascade.
To perform two’s-complement addition, we use S3–S0 to select the
DO NOT COPYoperation “A plus B plus CIN.” The CIN input of the least-significant ALU is
normally set to 0 during addition operations. To perform two’s-complement
subtraction, we use S3–S0 to select the operation A minus B minus plus CIN. In
this case, the CIN input of the least significant ALU is normally set to 1, since
CIN acts as the complement of the borrow during subtraction.
DO NOT COPYThe ’181 provides other arithmetic operations, such as “A minus 1 plus
CIN,” that are useful in some applications (e.g., decrement by 1). It also provides
a bunch of weird arithmetic operations, such as “A ⋅ B′ plus (A + B) plus CIN,”
that are almost never used in practice, but that “fall out” of the circuit for free.
DO NOT COPYNotice that the operand inputs A3_L–A0_L and B3_L–B0_L and the
function outputs F3_L–F0_L of the ’181 are active low. The ’181 can also be
used with active-high operand inputs and function outputs. In this case, a differ-
ent version of the function table must be constructed. When M = 1, logical
operations are still performed, but for a given input combination on S3–S0, the
DO NOT COPYfunction obtained is precisely the dual of the one listed in Table 5-51. When
M = 0, arithmetic operations are performed, but the function table is once again
different. Refer to a ’181 data sheet for more details.
74x381
DO NOT COPY74x382
Two other MSI ALUs, the 74x381 and 74x382 shown in Figure 5-93,
encode their select inputs more compactly, and provide only eight different but
useful functions, as detailed in Table 5-52. The only difference between the ’381
and ’382 is that one provides group-carry lookahead outputs (which we explain
next), while the other provides ripple carry and overflow outputs.
DO NOT COPYLogicsymbolsfor4-bit
Figure 5-93 (a) 74x381 (b) 74x382
5 S0
5 S0
ALUs: (a) 74x381; NOT6 S1 G 13 6 S1
7 S2P 14
DO(b) 74x382. 15 CIN COPY7 S2 OVR 13
3 A0F0 8 15 CIN COUT 14
4 B0
3 A0 F0 8
4 B0
1 A1 F1 9 1 A1 F1 9
2 B1F2 112 B1 F2 11
19 A2F3 1219 A2 F3 12
18 B218 B2
17 A3
DO NOT COPY17 A3
16 B3 16 B3
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 401
Inputs
DO NOT COPYS2 S1 S0
Function Table 5-52
Functions performed
by the 74x381 and
000 F = 0000 74x382 4-bit ALUs.
F = B minus A minus 1 plus CIN
F = A minus B minus 1 plus CIN
F = A plus B plus CIN
F=A⊕B
001 COPY
010
011
DO NOT1 0 0
101 F=A+B
F=A⋅B
F = 1111
110
DO NOT COPY1 1 1
*5.10.7 Group-Carry Lookahead
The ’181 and ’381 provide group-carry lookahead outputs that allow multiple group-carry lookahead
ALUs to be cascaded without rippling carries between 4-bit groups. Like the
74x283, the ALUs use carry lookahead to produce carries internally. However,
DO NOT COPYthey also provide G_L and P_L outputs that are carry lookahead signals for the
entire 4-bit group. The G_L output is asserted if the ALU generates a carry, that
is, if it will produce a carry-out (COUT = 1) whether or not there is a carry-in
(CIN = 1):
G_L = (g3 + p3 ⋅ g2 + p3 ⋅ p2 ⋅ g1 + p3 ⋅ p2 ⋅ p1 ⋅ g0)′
DO NOT COPYThe P_L output is asserted if the ALU propagates a carry, that is, if it will
produce a carry-out if there is a carry-in:
P_L = (p3 ⋅ p2 ⋅ p1 ⋅ p0)′
When ALUs are cascaded, the group-carry lookahead outputs may be
DO NOT COPYcombined in just two levels of logic to produce the carry input to each ALU. A
lookahead carry circuit
lookahead carry circuit, the 74x182 shown in Figure 5-94, performs this opera- 74x182
tion. The ’182 inputs are C0, the carry input to the least significant ALU 74x182
(“ALU 0”), and G0–G3 and P0–P3, the generate and propagate outputs of ALUs
0–3. Using these inputs, the ’182 produces carry inputs C1–C3 for ALUs 1–3. 13 C0
3 G0
DO NOT COPYFigure 5-95 shows the connections for a 16-bit ALU using four ’381s and a4 P0
’182.
C1 12
The 182’s carry equations are obtained by “adding out” the basic carry 1 G1 C2 11
lookahead equation of Section 5.10.4: 2 P1 C3 9
14 G2
DO NOT COPYci+1 = gi+pi⋅ci 15 P2
5 G3 G 10
6 P3 P7
= (gi + pi) ⋅ (gi + ci)
Expanding for the first three values of i, we obtain the following equations:
C1 = (G0+ P0) ⋅ (G0+C0)
DO NOT COPYC2 = (G1+P1) ⋅ (G1+G0+P0) ⋅ (G1+G0+C0)
Figure 5-94
Logic symbol for the
74x182 lookahead
C3 = (G2+P2) ⋅ (G2+G1+P1) ⋅ (G2+G1+G0+P0) ⋅ (G2+G1+G0+C0) carry circuit.
Copyright © 1999 by John F. Wakerly Copying Prohibited
402 Chapter 5 Combinational Logic Design Practices COPY74x182
13 C0
DO NOTFigure 5-95 3 G0
A 16-bit ALU using 4 P0 C1 12 C4
group-carry lookahead.
COPY1 G1 C2 11 C8
DO NOT 2 P1 C3 9 C12
14 G2
15 P2
5 G3 G 10 GALL_L
6 P3 P7 PALL_L
DOC0 NOT COUP5 Y
S[2:0]
A[15:0] NOT74x381
DOB[15:0] COPY74x381
S0 5 S0 S0 5 S0
S1 6 S1 S1 6 S1
S2 7 S2 G 13 G0_L S2 7 S2 G 13 G2_L
P 14 P0_L P 14 P2_L
DOA0 NOT15 CIN COPY15 CIN
B0 F0 8 F0 A8 3 A0 F0 8 F8
A1 3 A0 B8 4 B0
B1 4 B0
1 A1 F1 9 F1 A9 1 A1 F1 9 F9
2 B1 B9 2 B1
A2 NOT19 A2 F2 11 F2 COPYA10 19 A2 F2 11 F10
F3 B10 18 B2
DOB2 18 B2 F3 12 A11 17 A3 F3 12 F11
A3 17 A3 U1 B11 16 B3 U3
B3 16 B3
ALU0 ALU2
DOS0 NOT74x381 COPY74x381
S1 5 S0 S0 5 S0
S2 6 S1
7 S2 13 G1_L S1 6 S1 G 13 G3_L
DOA4
B4 G S2 7 S2
A5
B5 15 CIN P 14 P1_L 15 CIN P 14 P3_L
A6
B6 NOT3 A0 F0 8 F4 COPYA12 3 A0 F0 8 F12
F1 9 F5 B12 4 B0
DOA7 4 B0
B7 1 A1 A13 1 A1 F1 9 F13
2 B1 B13 2 B1
19 A2 F2 11 F6 A14 19 A2 F2 11 F14
18 B2 B14 18 B2
NOT17 A3 F3 12 F7 COPYA15 17 A3 F3 12 F15
B15 16 B3
16 B3 U2 U4
ALU1 ALU3 F[15:0]
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 403
The ’182 realizes each of these equations with just one level of delay—an
INVERT-OR-AND gate.
DO NOT COPYWhen more than four ALUs are cascaded, they may be partitioned into
“supergroups,” each with its own ’182. For example, a 64-bit adder would have
four supergroups, each containing four ALUs and a ’182. The G_L and P_L
outputs of each ’182 can be combined in a next-level ’182, since they indicate
whether the supergroup generates or propagates carries:
DO NOT COPYG_L = ((G3+P3) ⋅ (G3+G2+P2) ⋅ (G3+G2+ G1+P1) ⋅ (G3+G2+G1+G0))′
P_L = (P0 ⋅ P1 ⋅ P2 ⋅ P3)′
*5.10.8 Adders in ABEL and PLDs
DO NOT COPYABEL supports addition (+) and subtraction (-) operators which can be applied
to sets. Sets are interpreted as unsigned integers; for example, a set with n bits
represents an integer in the range of 0 to 2n−1. Subtraction is performed by
negating the subtrahend and adding. Negation is performed in two’s comple-
ment; that is, the operand is complemented bit-by-bit and then 1 is added.
DO NOT COPYTable 5-53 shows an example of addition in ABEL. The set definition for
SUM was made one bit wider than the addends to accommodate the carry out of
the MSB; otherwise this carry would be discarded. The set definitions for the
addends were extended on the left with a 0 bit to match the size of SUM.
DO NOT COPYEven though the adder program is extremely small, it takes a long time to
compile and it generates a huge number of terms in the minimal two level sum of
products. While SUM0 has only two product terms, subsequent terms SUMi have
5 ⋅2i−4 terms, or 636 terms for SUM7! And the carry out (SUM8) has 28−1=255
product terms. Obviously, adders with more than a few bits cannot be practically
DO NOT COPYrealized using two levels of logic.
Ta ble 5-5 3
ABEL program for
an 8-bit adder.
module add
title 'Adder Exercise'
DO NOT COPY" Input and output pins
A7..A0, B7..B0 pin;
SUM8..SUM0 pin istype 'com';
" Set definitions
A = [0, A7..A0];
DO NOT COPYB = [0, B7..B0];
SUM = [SUM8..SUM0];
equations
DO NOT COPYSUM = A + B;
end add
Copyright © 1999 by John F. Wakerly Copying Prohibited
404 Chapter 5 Combinational Logic Design Practices
CARRYING ON The carry out (SUM8) in our adder example has the exactly same number of product
DO NOT COPYterms (255) as the “less-than” or “greater-than” output of an 8-bit comparator. This
is less surprising once you realize that the carry out from the addition A+B is
functionally equivalent to the expression A>B.
DO NOT COPYRecognizing that larger adders and comparators are still needed in PLDs
@CARRY directive from time to time, ABEL provides an @CARRY directive which tells the compiler
to synthesize group-ripple adder with n bits per group. For example, if the
statement “@CARRY 1;” were included in Table 5-53, the compiler would create
eight new signals for the carries out of bit positions 0 through 7. The equations
DO NOT COPYfor SUM1 through SUM8 would use these internal carries, essentially creating an
8-stage ripple adder with a worst-case delay of eight passes through the PLD.
If the statement “@CARRY 2;” were used, the compiler would compute car-
ries two bits at a time, creating four new signals for carries out of bit positions 1,
DO NOT COPY3, 5, and 7. In this case, the maximum number of product terms needed for any
output is still reasonable, only 7, and the worst-case delay path has just four
passes through the PLD. With three bits per group (@CARRY 3;), the maximum
number of product terms balloons to 28, which is impractical.
A special case that is often used in ABEL and PLDs is adding or subtract-
DO NOT COPYing a constant 1. This operation is used in the definition of counters, where the
next state of the counter is just the current state plus 1 for an “up” counter or
minus 1 for a “down” counter. The equation for bit i of an “up” counter can be
stated very simply in words: “Complement bit i if counting is enabled and all of
the bits lower than i are 1.” This requires just i+2 product terms for any value of
DO NOT COPYi, and can be further reduced to just one product term and an XOR gate in some
PLDs, as shown in Sections 10.5.1 and 10.5.3.
*5.10.9 Adders in VHDL
Although VHDL has addition (+) and subtraction (-) operators built in, they
DO NOT COPYonly work with the integer, real, and physical types. They specifically do not
work with BIT_VECTOR types or the IEEE standard type STD_LOGIC_VECTOR.
Instead, standard packages define these operators.
As we explained in Section 5.9.6, the IEEE_std_logic_arith package
defines two new array types, SIGNED and UNSIGNED, and a set of comparison
DO NOT COPYfunctions for operands of type INTEGER, SIGNED, or UNSIGNED. The package
also defines addition and subtraction operations for the same kinds of operands
as well as STD_LOGIC and STD_ULOGIC for 1-bit operands.
The large number of overlaid addition and subtraction functions may make
DO NOT COPYit less than obvious what type an addition or subtraction result will have.
Normally, if any of the operands is type SIGNED, the result is SIGNED, else the
result is UNSIGNED. However, if the result is assigned to a signal or variable of
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 405
library IEEE;
use IEEE.std_logic_1164.all;
DO NOT COPYuse IEEE.std_logic_arith.all;
Table 5-54
VHDL program for
adding and subtracting
8-bit integers of
entity vadd is various types.
port ( COPY
A, B: in UNSIGNED (7 downto 0);
C: in SIGNED (7 downto 0);
DO NOTD: in STD_LOGIC_VECTOR (7 downto 0);
S: out UNSIGNED (8 downto 0);
T: out SIGNED (8 downto 0); COPY
U: out SIGNED (7 downto 0);
V: out STD_LOGIC_VECTOR (8 downto 0)
DO NOT);
end vadd;
architecture vadd_arch of vadd is
begin
S <= ('0' & A) + ('0' & B);
DO NOT COPYT <= A + C;
U <= C + SIGNED(D);
V <= C - UNSIGNED(D);
end vadd_arch;
DO NOT COPYtype STD_LOGIC_VECTOR, then the SIGNED or UNSIGNED result is converted to
that type. The length of any result is normally the length of the longest operand.
However, when an UNSIGNED operand is combined with a SIGNED or INTEGER
operand, its length is increased by 1 to accommodate a sign bit of 0, and then the
result’s length is determined.
DO NOT COPYIncorporating these considerations, the VHDL program in Table 5-54
shows 8-bit additions for various operand and result types. The first result, S, is
declared to be 9 bits long assuming the designer is interested in the carry from
the 8-bit addition of UNSIGNED operands A and B. The concatenation operator &
is used to extend A and B so that the addition function will return the carry bit in
DO NOT COPYtheMSBoftheresult.
The next result, T, is also 9 bits long, since the addition function extends the
UNSIGNED operand A when combining it with the SIGNED operand C. In the third
addition, an 8-bit STD_LOGIC_VECTOR D is type-converted to SIGNED and
DO NOT COPYcombined with C to obtain an 8-bit SIGNED result U. In the last statement, D is
converted to UNSIGNED, automatically extended by one bit, and subtracted from
C to produce a 9-bit result V.
Since addition and subtraction are fairly expensive in terms of the number
of gates required, many VHDL synthesis engines will attempt to reuse adder
DO NOT COPYblocks whenever possible. For example, Table 5-55 is a VHDL program that
includes two different additions. Rather than building two adders and selecting
Copyright © 1999 by John F. Wakerly Copying Prohibited
406 Chapter 5 Combinational Logic Design Practices
Table 5-55
VHDL program that
DO NOT COPYallows adder sharing.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
DO ); entity vaddshr is
NOT COPYport (
A, B, C, D: in SIGNED (7 downto 0);
SEL: in STD_LOGIC;
S: out SIGNED (7 downto 0)
DO NOT COPYend vaddshr;
architecture vaddshr_arch of vaddshr is
begin
S <= A + B when SEL = '1' else C + D;
end vaddshr_arch;
one’s output with a multiplexer, the synthesis engine can build just one adder and
DO NOT COPYselect its inputs using multiplexers, potentially creating a smaller overall circuit.
*5.11 Combinational Multipliers
*5.11.1 Combinational Multiplier Structures
DO NOT COPYIn Section 2.8, we outlined an algorithm that uses n shifts and adds to multiply
n-bit binary numbers. Although the shift-and-add algorithm emulates the way
that we do paper-and-pencil multiplication of decimal numbers, there is nothing
inherently “sequential” or “time dependent” about multiplication. That is, given
two n-bit input words X and Y, it is possible to write a truth table that expresses
the 2n-bit product P = X ⋅Y as a combinational function of X and Y. A combina-
DO NOT COPYcombinational
multiplier tional multiplier is a logic circuit with such a truth table.
Most approaches to combinational multiplication are based on the paper-
and-pencil shift-and-add algorithm. Figure 5-96 illustrates the basic idea for an
DO NOT COPY8×8 multiplier for two unsigned integers, multiplicand X = x7x6x5x4x3x2x1x0 and
product component multiplier Y = y7y6y5y4y3y2y1y0. We call each row a product component, a shifted
DOFigure 5-96 NOT COPYy0x7 y0x6 y0x5 y0x4 y0x3 y0x2 y0x1 y0x0
y1x7 y1x6 y1x5 y1x4 y1x3 y1x2 y1x1 y1x0
Partial products in an y2x7 y2x6 y2x5 y2x4 y2x3 y2x2 y2x1 y2x0
8 × 8 multiplier. y3x7 y3x6 y3x5 y3x4 y3x3 y3x2 y3x1 y3x0
y4x7 y4x6 y4x5 y4x4 y4x3 y4x2 y4x1 y4x0
DO y5x7 y5x6 y5x5 y5x4 y5x3 y5x2 y5x1 y5x0
NOT COPYy6x7 y6x6 y6x5 y6x4 y6x3 y6x2 y6x1 y6x0
y7x7 y7x6 y7x5 y7x4 y7x3 y7x2 y7x1 y7x0
p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 407
Figure 5-97 NOTy0x7 COPYy0x6 y0x5 y0x4 y0x3 y0x2 y0x1 y0x0
Interconnections y1x7 y1x6
y1x5 y1x4 y1x3 y1x2 y1x1 y1x0
DOfor an 8 × 8 0
combinational NOT COPYy2x7 y2x6 y2x5 y2x4 y2x3 y2x2 y2x1 y2x0
0
DOmultiplier. y3x7 y3x6 y3x5 y3x4 y3x3 y3x2 y3x1 y3x0
DO NOTy4x7 y4x6 y4x5 y4x4 y4x3 COPYy4x2 y4x1 y4x0 0
0
DO NOT COPYy5x7 y5x6 y5x5 y5x4 y5x3 y5x2 y5x1 y5x0
0
DOy6x7 y6x6 NOTy6x5 y6x4 y6x3 y6x2 y6x1 COPYy6x0
y7x7 y7x6 y7x5 0
y7x4 y7x3 y7x2 y7x1 y7x0
DOp15 p14 p13 p12 COPY0
NOTp11 p10p9 p8 p7
p6 p5 p4 p3 p2 p1 p0
multiplicand that is multiplied by 0 or 1 depending on the corresponding multi-
plier bit. Each small box represents one product-component bit yixj, the logical
AND of multiplier bit yi and multiplicand bit xj. The product P = p15p14 . ..p2p1p0
DO NOT COPYhas 16 bits and is obtained by adding together all the product components.
Figure 5-97 shows one way to add up the product components. Here, the
product-component bits have been spread out to make space, and each “+” box
is a full adder equivalent to Figure 5-85(c) on page 391. The carries in each row
of full adders are connected to make an 8-bit ripple adder. Thus, the first ripple
DO NOT COPYadder combines the first two product components to product the first partial
product, as defined in Section 2.8. Subsequent adders combine each partial
product with the next product component.
It is interesting to study the propagation delay of the circuit in Figure 5-97.
DO NOT COPYIn the worst case, the inputs to the least significant adder (y0x1 and y1x0) can
affect the MSB of the product (p15). If we assume for simplicity that the delays
from any input to any output of a full adder are equal, say tpd, then the worst case
Copyright © 1999 by John F. Wakerly Copying Prohibited
408 Chapter 5 Combinational Logic Design Practices
Figure 5-98 NOTy0x7 COPYy0x6 y0x5 y0x4 y0x3 y0x2 y0x1 y0x0
Interconnections y1x7 y1x6
y1x5 y1x4 y1x3 y1x2 y1x1 y1x0
DOfor a faster 8 × 8 0000000
combinational NOT COPYy2x7 y2x6 y2x5 y2x4 y2x3 y2x2 y2x1 y2x0
y3x7 y3x6 y3x5 y3x4 y3x3 y3x2 y3x1 y3x0
DOmultiplier.
NOTy4x7 y4x6 y4x5 y4x4 y4x3 COPYy4x2 y4x1 y4x0
DO
DO NOT COPYy5x7 y5x6 y5x5 y5x4 y5x3 y5x2 y5x1 y5x0
DOy6x7 y6x6 NOTy6x5 y6x4 y6x3 y6x2 y6x1 COPYy6x0
y7x7 y7x6 y7x5 COPY
y7x4 y7x3 y7x2 y7x1 y7x0 p5
DO
NOT0
p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p4 p3 p2 p1 p0
path goes through 20 adders and its delay is 20tpd. If the delays are different, then
DO NOT COPYthe answer depends on the relative delays; see Exercise \exref{xxxx}.
sequential multiplier Sequential multipliers use a single adder and a register to accumulate the
partial products. The partial-product register is initialized to the first product
component, and for an n ×n-bit multiplication, n−1 steps are taken and the adder
is used n−1 times, once for each of the remaining n−1 product components to be
DO NOT COPYadded to the partial-product register.
carry-save addition Some sequential multipliers use a trick called carry-save addition to speed
up multiplication. The idea is to break the carry chain of the ripple adder to
shorten the delay of each addition. This is done by applying the carry output
DO NOT COPYfrom bit i during step j to the carry input for bit i+1 during the next step, j+1.
After the last product component is added, one more step is needed in which the
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 409
carries are hooked up in the usual way and allowed to ripple from the least to the
most significant bit.
DO NOT COPYThe combinational equivalent of an 8×8 multiplier using carry-save addi-
tion is shown in Figure 5-98. Notice that the carry out of each full adder in the
first seven rows is connected to an input of an adder below it. Carries in the
eighth row of full adders are connected to create a conventional ripple adder.
Although this adder uses exactly the same amount of logic as the previous one
DO NOT COPY(64 2-input AND gates and 56 full adders), its propagation delay is substantially
shorter. Its worst-case delay path goes through only 14 full adders. The delay can
be further improved by using a carry lookahead adder for the last row.
The regular structure of combinational multipliers make them ideal for
VLSI and ASIC realization. The importance of fast multiplication in micro-
DO NOT COPYprocessors, digital video, and many other applications has led to much study and
development of even better structures and circuits for combinational multipliers;
see the References.
*5.11.2 Multiplication in ABEL and PLDs
DO NOT COPYABEL provides a multiplication operator *, but it can be used only with individ-
ual signals, numbers, or special constants, not with sets. Thus, ABEL cannot
synthesize a multiplier circuit from a single equation like “P = X*Y.”
Still, you can use ABEL to specify a combinational multiplier if you break
DO NOT COPYit down into smaller pieces. For example, Table 5-56 shows the design of a 4×4
unsigned multiplier following the same general structure as Figure 5-96 on page
page 406. Expressions are used to define the four product components, PC1,
PC2, PC3, and PC4, which are then added in the equations section of the pro-
gram. This does not generate an array of full adders as in Figure 5-97 or 5-98.
DO NOT COPYRather, the ABEL compiler will dutifully crunch the addition equation to pro-
Table 5-56
ABEL program for a
4×4 combinational
multiplier.
module mul4x4
title '4x4 Combinational Multiplier'
DO NOT COPYX3..X0, Y3..Y0 pin; " multiplicand, multiplier
P7..P0 pin istype 'com'; " product
P = [P7..P0]; COPY
PC1 = Y0 & [0, 0, 0, 0,X3,X2,X1,X0]; COPY
DO NOTPC2 = Y1 & [0, 0, 0,X3,X2,X1,X0, 0];
PC3 = Y2 & [0, 0,X3,X2,X1,X0, 0, 0];
PC4 = Y3 & [0,X3,X2,X1,X0, 0, 0, 0];
equations
DO NOTP = PC1 + PC2 + PC3 + PC4;
end mul4x4
Copyright © 1999 by John F. Wakerly Copying Prohibited
410 Chapter 5 Combinational Logic Design Practices
duce a minimal sum for each of the eight product output bits. Surprisingly, the
worst-case output, P4, has only 36 product terms, a little high but certainly real-
DO NOT COPYizable in two passes through a PLD.
*5.11.3 Multiplication in VHDL
VHDL is rich enough to express multiplication in a number of different ways;
we’ll save the best for last.
DO NOT COPYTable 5-57 is a behavioral VHDL program that mimics the multiplier
structure of Figure 5-98. In order to represent the internal signals in the figure,
the program defines a new data type, array8x8, which is a two-dimensional
array of STD_LOGIC (recall that STD_LOGIC_VECTOR is a one-dimensional array
of STD_LOGIC). Variable PC is declared as a such an array to hold the product-
DO NOT COPYcomponent bits, and variables PCS and PCC are similar arrays to hold the sum and
carry outputs of the main array of full adders. One-dimensional arrays RAS and
RAC hold the sum and carry outputs of the ripple adder. Figure 5-99 shows the
variable naming and numbering scheme. Integer variables i and j are used as
loop indices for rows and columns, respectively.
DO NOT COPYThe program attempts to illustrate the logic gates that would be used in a
faithful realization of Figure 5-98, even though a synthesizer could legitimately
create quite a different structure from this behavioral program. If you want to
control the structure, then you must use structural VHDL, as we’ll show later.
DO NOT COPYIn the program, the first, nested for statement performs 64 AND operations
to obtain the product-component bits. The next for loop initializes boundary
conditions at the top of the multiplier, using the notion of row-0 “virtual” full
DO NOT COPYFigure 5-99
adders, not shown in the figure, whose sum outputs equal the first row of PC bits
PCS(0)(j) y0x7 y0x6 y0x5 y0x4 y0x3 y0x2 y0x1 y0x0
VHDL variable names y1x7 y1x6 y1x5 y1x4 y1x3 y1x2 y1x1 y1x0 0
COPY0 0 0 0 0 0
DOfor the 8 × 8 multiplier. NOTPCS(1)(7) y2x4 y2x3 y2x2 y2x1 y2x0 PCC
PCC(1)(6) (0)(0)
PCS(1)(6)
PCS
y2x7 y2x6 y2x5 (0)(0)
y6x7 PCS(2)(7)
DOPCS(6)(7) NOTy3x7 y3x6 y3x5 y3x4 COPYy3x2 y3x1 y3x0 PCC PCS
y7x7 y7x6 y7x5 (1)(0) (2)(0)
y7x4 y7x3 y7x2 y7x1 y7x0 y3x3
PCS(7)(7)
DO NOT COPY0 PCS PCS PCS
(7)(0) (3)(0) (2)(0)
p15 p14 p13 p12
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0
RAC(7) RAC(6) RAC(5) RAS(3) RAS(2) RAS(1) RAC(1) RAC(0)
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 411
library IEEE;
DO NOT COPYuse IEEE.std_logic_1164.all;
Ta ble 5- 57
Behavioral VHDL
program for an 8×8
entity vmul8x8p is combinational
port ( X: in STD_LOGIC_VECTOR (7 downto 0); multiplier.
Y: in STD_LOGIC_VECTOR (7 downto 0);
P: out STD_LOGIC_VECTOR (15 downto 0) );
DO NOT COPYend vmul8x8p;
architecture vmul8x8p_arch of vmul8x8p is
function MAJ (I1, I2, I3: STD_LOGIC) return STD_LOGIC is
begin
return ((I1 and I2) or (I1 and I3) or (I2 and I3));
DO NOT COPYend MAJ;
begin
process (X, Y)
type array8x8 is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0);
DO NOT COPYvariable PCC: array8x8; -- full-adder carry output bits
variable PC: array8x8; -- product component bits
variable PCS: array8x8; -- full-adder sum bits
variable RAS, RAC: STD_LOGIC_VECTOR (7 downto 0); -- ripple adder sum
begin -- and carry bits
for i in 0 to 7 loop for j in 0 to 7 loop
PC(i)(j) := Y(i) and X(j); -- compute product component bits
end loop; end loop;
DO NOT COPYfor j in 0 to 7 loop
PCS(0)(j) := PC(0)(j); -- initialize first-row "virtual"
PCC(0)(j) := '0';
end loop;
for i in 1 to 7 loop
DO NOT COPYfor j in 0 to 6 loop
-- adders (not shown in figure)
-- do all full adders except last row
PCS(i)(j) := PC(i)(j) xor PCS(i-1)(j+1) xor PCC(i-1)(j);
PCC(i)(j) := MAJ(PC(i)(j), PCS(i-1)(j+1), PCC(i-1)(j));
PCS(i)(7) := PC(i)(7); -- leftmost "virtual" adder sum output
end loop;
end loop;
DO NOT COPYRAC(0) := '0';
for i in 0 to 6 loop -- final ripple adder
RAS(i) := PCS(7)(i+1) xor PCC(7)(i) xor RAC(i);
RAC(i+1) := MAJ(PCS(7)(i+1), PCC(7)(i), RAC(i));
end loop;
for i in 0 to 7 loop
DO NOT COPYP(i) <= PCS(i)(0); -- first 8 product bits from full-adder sums
end loop;
for i in 8 to 14 loop
DO NOT COPYP(15) <= RAC(7);
P(i) <= RAS(i-8); -- next 7 bits from ripple-adder sums
end loop;
-- last bit from ripple-adder carry
end process;
end vmul8x8p_arch;
Copyright © 1999 by John F. Wakerly Copying Prohibited
412 Chapter 5 Combinational Logic Design Practices
SIGNALS VS. Variables are used rather than signals in the process in Table 5-57 to make simula-
DO NOT COPYVARIABLES tion run faster. Variables are faster because the simulator keeps track of their values
only when the process is running. Because variable values are assigned sequentially,
the process in Table 5-57 is carefully written to compute values in the proper order.
That is, a variable cannot be used until a value has been assigned to it.
Signals, on the other hand, have a value at all times. When a signal value is
DO NOT COPYchanged in a process, the simulator schedules a future event in its event list for the
value change. If the signal appears on the right-hand side of an assignment statement
in the process, then the signal must also be included in the process’ sensitivity list. If
a signal value changes, the process will then execute again, and keep repeating until
all of the signals in the sensitivity list are stable.
DO NOT COPYIn Table 5-57, if you wanted to observe internal values or timing during
simulation, you could change all the variables (except i and j) to signals and include
them in the sensitivity list. To make the program syntactically correct, you would
also have to move the type and signal declarations to just after the architecture
statement, and change all of the “:=” assignments to “<=”.
DO NOT COPYSuppose that after making the changes above, you also reversed the order of
the indices in the for loops (e.g., “7 downto 0” instead of “0 to 7”). The program
would still work. However, dozens of repetitions of the process would be required
for each input change in X or Y, because the signal changes in this circuit propagate
from the lowest index to the highest.
DO NOT COPYWhile the choice of signals vs. variables affects the speed of simulation, with
most VHDL synthesis engines it does not affect the results of synthesis.
and whose carry outputs are 0. The third, nested for loop corresponds to the
DO NOT COPYmain array of adders in Figure 5-98, all except the last row, which is handled by
the fourth for loop. The last two for loops assign the appropriate adder outputs
to the multiplier output signals.
DO NOT COPYON THE A three-input “majority function,” MAJ, is defined at the beginning of Table 5-57 and
THRESHOLD OF A is subsequently used to compute carry outputs. An n-input majority function
DO NOT COPYDREAM
produces a 1 output if the majority of its inputs are 1, two out of three in the case of
a 3-input majority function. (If n is even, n/2+1 inputs must be 1.)
Over thirty years ago, there was substantial academic interest in a more general
class of n-input threshold functions which produce a 1 output if k or more of their
inputs are 1. Besides providing full employment for logic theoreticians, threshold
functions could realize many logic functions with a smaller number of elements than
could a conventional AND/OR realization. For example, an adder’s carry function
requires three AND gates and one OR gate, but just one three-input threshold gate.
DO NOT COPY(Un)fortunately, an economical technology never emerged for threshold gates,
and they remain, for now, an academic curiosity.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section *5.10 Adders, Subtractors, and ALUs 413
architecture vmul8x8s_arch of vmul8x8s is COPYTable 5-58
component AND2 Structural VHDL
DO NOTport( I0, I1: in STD_LOGIC; architecture for an
O: out STD_LOGIC ); 8×8 combinational
end component; multiplier.
component XOR3
COPY
port( I0, I1, I2: in STD_LOGIC;
O: out STD_LOGIC );
DO NOTend component;
component MAJ -- Majority function, O = I0*I1 + I0*I2 + I1*I2
port( I0, I1, I2: in STD_LOGIC;
O: out STD_LOGIC );
DO NOT COPYend component;
type array8x8 is array (0 to 7) of STD_LOGIC_VECTOR (7 downto 0);
signal PC: array8x8; -- product-component bits
signal PCS: array8x8; -- full-adder sum bits
signal PCC: array8x8; -- full-adder carry output bits
signal RAS, RAC: STD_LOGIC_VECTOR (7 downto 0); -- sum, carry
DO NOT COPYbegin
g1: for i in 0 to 7 generate -- product-component bits
g2: for j in 0 to 7 generate COPY
U1: AND2 port map (Y(i), X(j), PC(i)(j));
end generate;
end generate;
DO NOTg3: for j in 0 to 7 generate
PCS(0)(j) <= PC(0)(j); -- initialize first-row "virtual" adders
PCC(0)(j) <= '0';
end generate;
g4: for i in 1 to 7 generate -- do full adders except the last row
DO NOT COPYg5: for j in 0 to 6 generate
U2: XOR3 port map (PC(i)(j),PCS(i-1)(j+1),PCC(i-1)(j),PCS(i)(j));
U3: MAJ port map (PC(i)(j),PCS(i-1)(j+1),PCC(i-1)(j),PCC(i)(j));
PCS(i)(7) <= PC(i)(7); -- leftmost "virtual" adder sum output
end generate;
end generate;
DO NOT COPYRAC(0) <= '0';
g6: for i in 0 to 6 generate -- final ripple adder
U7: XOR3 port map (PCS(7)(i+1), PCC(7)(i), RAC(i), RAS(i));
U3: MAJ port map (PCS(7)(i+1), PCC(7)(i), RAC(i), RAC(i+1));
end generate;
g7: for i in 0 to 7 generate
DO NOT COPYP(i) <= PCS(i)(0); -- get first 8 product bits from full-adder sums
end generate;
g8: for i in 8 to 14 generate
DO NOT COPYP(15) <= RAC(7);
P(i) <= RAS(i-8); -- get next 7 bits from ripple-adder sums
end generate;
-- get last bit from ripple-adder carry
end vmul8x8s_arch;
Copyright © 1999 by John F. Wakerly Copying Prohibited
414 Chapter 5 Combinational Logic Design Practices
The program in Table 5-57 can be modified to use structural VHDL as
shown in Table 5-58. This approach gives the designer complete control over the
DO NOT COPYcircuit structure that is synthesized, as might be desired in an ASIC realization.
The program assumes that the architectures for AND2, XOR3, and MAJ3 have been
defined elsewhere, for example, in an ASIC library.
This program makes good use of the generate statement to create the
arrays of components used in the multiplier. The generate statement must have
a label, and similar to a for-loop statement, it specifies an iteration scheme to
DO NOT COPYgenerate statement
control the repetition of the enclosed statements. Within for-generate, the
enclosed statements can include any concurrent statements, IF-THEN-ELSE
statements, and additional levels of looping constructs. Sometimes generate
statements are combined with IF-THEN-ELSE to produce a kind of conditional
DO NOT COPYcompilationcapability
Well, we said we’d save the best for last, and here it is. The IEEE
std_logic_arith library that we introduced in Section 5.9.6 defines multipli-
cation functions for SIGNED and UNSIGNED types, and overlays these functions
DO NOT COPYonto the “*” operator. Thus, the program in Table 5-59 can multiply unsigned
numbers with a simple one-line assignment statement. Within the IEEE library,
the multiplication function is defined behaviorally, using the shift-and-add algo-
rithm. We could have showed you this approach at the beginning of this
DO NOT COPYsubsection, but then you wouldn’t have read the rest of it, would you?
Table 5-59 library IEEE;
Truly behavioral VHDL use IEEE.std_logic_1164.all;
program for an 8×8
DO NOT COPYcombinationalmultiplier.
use IEEE.std_logic_arith.all;
entity vmul8x8i is
port (
X: in UNSIGNED (7 downto 0);
DO NOT COPYY: in UNSIGNED (7 downto 0);
P: out UNSIGNED (15 downto 0)
);
end vmul8x8i;
architecture vmul8x8i_arch of vmul8x8i is
DO
NOT COPYbegin
P <= X * Y;
end vmul8x8i_arch;
References
Digital designers who want to write better should start by reading the classic
DO NOT COPYElements of Style, 3rd ed., by William Strunk, Jr. and E. B. White (Allyn &
Bacon, 1979). Another book on writing style, especially for nerds, is Effective
Copyright © 1999 by John F. Wakerly Copying Prohibited
References 415
SYNTHESIS OF You’ve probably heard that compilers for high-level programming languages like C
DO NOT COPYBEHAVIORAL usually generate better code than people do writing in assembly language, even with
DESIGNS “hand-tweaking.” Most digital designers hope that compilers for behavioral HDLs
will also some day produce results superior to a typical hand-tweaked design, be it a
schematic or structural VHDL. Better compilers won’t put the designers out of work,
they will simply allow them to tackle bigger designs.
DO NOT COPYWe’re not quite there yet. However, the more advanced synthesis engines do
include some nice optimizations for commonly used behavioral structures. For
example, I have to admit that the FPGA synthesis engine that I used to test the VHDL
programs in this subsection produced just as fast a multiplier from Table 5-59 as it
DO NOT COPYdid from any of the more detailed architectures!
Writing for Engineers, Managers, and Scientists, 2nd ed., by H. J. Tichy (Wiley,
1988). Plus two new books from Amazon.
The ANSIIEEE standard for logic symbols is Std 91-1984, IEEE Standard
DO NOT COPYGraphic Symbols for Logic Functions. Another standard of interest to logic
designers is ANSI/IEEE 991-1986, Logic Circuit Diagrams. These two stan-
dards and ten others, including standard symbols for 10-inch gongs and maid’s-
signal plugs, can be found in one handy, five-pound reference, Electrical and
Electronics Graphic and Letter Symbols and Reference Designations Standards
DO NOT COPYCollection Electrical and Electronics Graphics Symbols and Reference Desig-
nations published by the IEEE in 1996 (www.ieee.org).
Real logic devices are described in data sheets and data books published by
the manufacturers. Updated editions of data books used to be published every
DO NOT COPYfew years, but in recent years the trend has been to minimize or eliminate the
hardcopy editions and instead to publish up-to-date information on the web. Two
of the largest suppliers with the most comprehensive sites are Texas Instruments
(www.ti.com) and Motorola (www.mot.com).
For a given logic family such as 74ALS, all manufacturers list generally
DO NOT COPYequivalent specifications, so you can get by with just one data book per family.
Some specifications, especially timing, may vary slightly between manufactur-
ers, so when timing is tight it’s best to check a couple of different sources and use
the worst case. That’s a lot easier than convincing your manufacturing depart-
ment to buy a component only from a single supplier.
DO NOT COPYThe first PAL devices were invented in 1978 by John Birkner at Monolithic
Memories, Inc. (MMI). Birkner earned U.S. patent number 4,124,899 for his
invention, and MMI rewarded him by buying him a brand new Porsche! Seeing
the value in this technology (PALs, not Porsches), Advanced Micro Devices
(AMD) acquired MMI in the early 1980s and remained a leading developer and
DO NOT COPYsupplier of new PLDs and CPLDs. In 1997, AMD spun off its PLD operations to
form Vantis Corporation.
Copyright © 1999 by John F. Wakerly Copying Prohibited
416 Chapter 5 Combinational Logic Design Practices
Some of the best resources for learning about PLD-based design are pro-
vided the PLD manufacturers. For example, Vantis publishes the 1999 Vantis
DO NOT COPYData Book (Sunnyvale, CA 94088, 1999), which contains information on their
PLDs, CPLDs, and FPGAs. Individual data sheets and application notes are
readily downloadable from their web site (www.vantis.com). Similarly, GAL
inventor Lattice Semiconductor has a comprehensive Lattice Data Book (Hills-
boro, OR 97124, 1999) and web site (www.latticesemi.com).
DO NOT COPYA much more detailed discussion of the internal operation of LSI and VLSI
devices, including PLDs, ROMs, and RAMs, can be found in electronics texts
such as Microelectronics, 2nd ed., by J.Millman and A.Grabel (McGraw-Hill,
1987) and VLSI Engineering by Thomas E. Dillinger (Prentice Hall, 1988).
Additional PLD references are cited at the end of \chapref{SeqPLDs}.
DO NOT COPYOn the technical side of digital design, lots of textbooks cover digital
design principles, but only a few cover practical aspects of design. A classic is
Digital Design with Standard MSI and LSI by Thomas R. Blakeslee, 2nd ed.
(Wiley, 1979), which includes chapters on everything from structured combina-
DO NOT COPYtional design with MSI and LSI to “the social consequences of engineering.” A
more recent, excellent short book focusing on digital design practices is The
Well-Tempered Digital Design by Robert B. Seidensticker (Addison-Wesley,
1986). It contains hundreds of readily accessible digital-design “proverbs” in
areas ranging from high-level design philosophy to manufacturability. Another
DO NOT COPYeasy-reading, practical, and “fun” book on analog and digital design is Clive
Maxfield’s Bebop to the Boolean Boogie (LLH Technology Publishing, 1997;
for a good time, also visit www.maxmon.com).
DO NOT COPYDrillProblems
5.1 Give three examples of combinational logic circuits that require billions and bil-
lions of rows to describe in a truth table. For each circuit, describe the circuit’s
DO NOT COPYinputs and output(s), and indicate exactly how many rows the truth table contains;
you need not write out the truth table. (Hint: You can find several such circuits
right in this chapter.)
5.2 Draw the DeMorgan equivalent symbol for a 74x30 8-input NAND gate.
5.3 Draw the DeMorgan equivalent symbol for a 74x27 3-input NOR gate.
5.4 What’s wrong with the signal name “READY′ ”?
5.5 You may find it annoying to have to keep track of the active levels of all the sig-
DO NOT COPYnals in a logic circuit. Why not use only noninverting gates, so all signals are
active high?
5.6 True or false: In bubble-to-bubble logic design, outputs with a bubble can be con-
nected only to inputs with a bubble.
5.7 A digital communication system is being designed with twelve identical network
DO NOT COPYports. Which type of schematic structure is probably most appropriate for the
design?
Copyright © 1999 by John F. Wakerly Copying Prohibited
Drill Problems 417
5.8 Determine the exact maximum propagation delay from IN to OUT of the circuit
in Figure X5.8 for both LOW-to-HIGH and HIGH-to-LOW transitions, using the
DO NOT COPYtiming information given in Table 5-2. Repeat, using a single worst-case delay
number for each gate and compare and comment on your results.
74LS00 74LS00
74LS00 1 4
1 12 5
2
8 13
DO NOT COPYIN 2 74LS00 74LS00 1 1 6 OUT
U2
4 19 11 3
1 74LS00 1 5 6 10 U2
1 3
U1 U1
U1 U1
Figure X5.8
5.9 Repeat Drill 5.8, substituting 74HCT00s for the 74LS00s.
5.10 Repeat Drill 5.8, substituting 74LS08s for the 74LS00s.
DO NOT COPY5.11 Repeat Drill 5.8, substituting 74AHCT02s for the 74LS00s, using constant 0
instead of constant 1 inputs, and using typical rather than maximum timing.
Estimate the minimum propagation delay from IN to OUT for the circuit shown in
DO NOT COPY5.12
Figure X5.12. Justify your answer.
74LS86 74LS86
74LS86 74LS86 09 1 12 11 OUT
U1
1 0 4 6 10 8 13
5
1 3
IN 2 U1 Figure X5.12
U1
DO NOT COPY5.13 Determine the exact maximum propagation delay from IN to OUT of the circuitU1
in Figure X5.12 for both LOW-to-HIGH and HIGH-to-LOW transitions, using the
timing information given in Table 5-2. Repeat, using a single worst-case delay
number for each gate and compare and comment on your results.
5.14 Repeat Drill 5.13, substituting 74HCT86s for the 74LS86s.
DO NOT COPY5.15 Which would expect to be faster, a decoder with active-high outputs or one with
active-low outputs?
5.16 Using the information in Table 5-3 for 74LS components, determine the maxi-
mum propagation delay from any input to any output in the 5-to-32 decoder
circuit of Figure 5-39. You may use the “worst-case” analysis method.
DO NOT COPY5.17 Repeat Drill 5.16, performing a detailed analysis for each transition direction,
and compare your results.
5.18 Show how to build each of the following single- or multiple-output logic func-
tions using one or more 74x138 or 74x139 binary decoders and NAND gates.
(Hint: Each realization should be equivalent to a sum of minterms.)
DO NOT COPY(a) F=ΣX,Y,Z(2,4,7)
(b) F =∏A,B,C(3,4,5,6,7)
(c) F = ΣA,B,C,D(2,4,6,14) (d) F = ΣW,X,Y,Z(0,1,2,3,5,7,11,13)
DO NOTG = ΣW,X,Y(2,3,4,7) COPY
(e) F = ΣW,X,Y(1,3,5,6) (f) F = ΣA,B,C(0,4,6)
G = ΣC,D,E(1,2)
5.19 Draw the digits created by a 74x49 seven-segment decoder for the nondecimal
inputs 1010 through 1111.
Copyright © 1999 by John F. Wakerly Copying Prohibited
418 Chapter 5 Combinational Logic Design Practices
5.20 Starting with the logic diagram for the 74x148 priority encoder, write logic equa-
tions for its A2_L, A1_L, and A0_L outputs. How do they differ from the “generic”
DO NOT COPYequations given in Section 5.5.1?
5.21 What’s terribly wrong with the circuit in Figure X5.21? Suggest a change that
DO eliminates the terrible problem.
DO NOT COPYEN_L
74x139 1-bit party-line
1 1G 1Y0 4 SELP_L
1Y1 5 SELQ_L
2 1A 1Y2 6 SELR_L P
ASRC0
3 1B 1Y3 7 SELS_L
ASRC1
NOT COPYBSRC0
15 2G 2Y0 12 SELT_L Q
14 2A 2Y1 11 SELU_L
2Y2 10 SELV_L R
13 2B 2Y3 9 SELW_L
BSRC1
DO NOT COSPY
T
DO NOT COPYFigureX5.21 U
V
DO NOT COPYW
SDATA
5.22 Using the information in Tables 5-2 and 5-3 for 74LS components, determine the
maximum propagation delay from any input to any output in the 32-to-1 multi-
plexer circuit of Figure 5-65. You may use the “worst-case” analysis method.
5.23 Repeat Exercise 5.22 using 74HCT components.
DO NOT COPY5.24 An n-input parity tree can be built with XOR gates in the style of Figure 5-73(a).
Under what circumstances does a similar n-input parity tree built using XNOR
gates perform exactly the same function?
5.25 Using the information in Tables 5-2 and 5-3 for 74LS components, determine the
maximum propagation delay from the DU bus to the DC bus in the error-correc-
DO NOT COPYtion circuit of Figure 5-76. You may use the “worst-case” analysis method.
5.26 Repeat Exercise 5.25 using 74HCT components.
5.27 Starting with the equations given in Section 5.9.4, write a complete logic expres-
sion for the ALTBOUT output of the 74x85.
DO NOT COPY5.28 Starting with the logic diagram for the 74x682, write a logic expression for the
PGTQ_L output in terms of the inputs.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Exercises 419
5.29 Write an algebraic expression for s2, the third sum bit of a binary adder, as a func-
tion of inputs x0, x1, x2, y0, y1, and y2. Assume that c0 = 0, and do not attempt to
DO NOT COPY“multiply out” or minimize the expression.
5.30 Using the information in Table 5-3 for 74LS components, determine the maxi-
mum propagation delay from any input to any output of the 16-bit group ripple
adder of Figure 5-91. You may use the “worst-case” analysis method.
DO NOT COPYExercises
5.31 A possible definition of a BUT gate (Exercise 4.45) is “Y1 is 1 if A1 and B1 are 1
but either A2 or B2 is 0; Y2 is defined symmetrically.” Write the truth table and
find minimal sum-of-products expressions for the BUT-gate outputs. Draw the
logic diagram for a NAND-NAND circuit for the expressions, assuming that only
DO NOT COPYuncomplemented inputs are available. You may use gates from 74HCT00, ’04,
’10, ’20, and ’30 packages.
5.32 Find a gate-level design for the BUT gate defined in Exercise 5.31 that uses a min-
imum number of transistors when realized in CMOS. You may use gates from
74HCT00, ’02, ’04, ’10, ’20, and ’30 packages. Write the output expressions
DO NOT COPY(which need not be two-level sums-of-products), and draw the logic diagram.
5.33 For each circuit in the two preceding exercises, compute the worst-case delay
from input to output, using the delay numbers for 74HCT components in
Table 5-2. Compare the cost (number of transistors), speed, and input loading of
the two designs. Which is better?
DO NOT COPY5.34 Butify the function F = ΣW,X,Y,Z(3,7,11,12,13,14). That is, show how to perform F
butification
with a single BUT gate as defined in Exercise 5.31 and a single 2-input OR gate.
5.35 Design a 1-out-of-4 checker with four inputs, A, B, C, D, and a single output ERR.
The output should be 1 if two or more of the inputs are 1, and 0 if no input or one
DO NOT COPYinput is 1. Use SSI parts from Figure 5-18, and try to minimize the number of
gates required. (Hint: It can be done with seven two-input inverting gates.)
5.36 Suppose that a 74LS138 decoder is connected so that all enable inputs are assert-
ed and C B A = 101. Using the information in Table 5-3 and the ’138 internal logic
diagram, determine the propagation delay from input to all relevant outputs for
each possible single-input change. (Hint: There are a total of nine delay numbers,
DO NOT COPYsince a change on A, B, or C affects two outputs, and a change on any of the three
enable inputs affects one output.)
5.37 Suppose that you are asked to design a new component, a decimal decoder that is
optimized for applications in which only decimal input combinations are expect-
ed to occur. How can the cost of such a decoder be minimized compared to one
DO NOT COPYthat is simply a 4-to-16 decoder with six outputs removed? Write the logic equa-
tions for all ten outputs of the minimized decoder, assuming active-high inputs
and outputs and no enable inputs.
5.38 How many Karnaugh maps would be required to work Exercise 5.37 using the
DO NOT COPYformal multiple-output minimization procedure described in Section 4.3.8?
5.39 Suppose that a system requires a 5-to-32 binary decoder with a single active-low
enable input, a design similar to Figure 5-39. With the EN1 input pulled HIGH,
Copyright © 1999 by John F. Wakerly Copying Prohibited
420 Chapter 5 Combinational Logic Design Practices
DO NOT COPYeither the EN2_L or the EN3_L input in the figure could be used as the enable,
with the other input grounded. Discuss the pros and cons of using EN2_L versus
EN3_L.
5.40 Determine whether the circuits driving the a, b, and c outputs of the 74x49 seven-
segment decoder correspond to minimal product-of-sums expressions for these
segments, assuming that the nondecimal input combinations are “don’t cares”
and BI = 1.
DO NOT COPY5.41 Redesign the MSI 74x49 seven-segment decoder so that the digits 6 and 9 have
tails as shown in Figure X5.41. Are any of the digit patterns for nondecimal
inputs 1010 through 1111 affected by your redesign?
DO NOT COPYFigureX5.41
5.42 Starting with the ABEL program in Table 5-21, write a program for a seven-seg-
ment decoder with the following enhancements:
• The outputs are all active low.
DO NOT COPY• Two new inputs, ENHEX and ERRDET, control the decoding of the segment outputs.
• If ENHEX = 0, the outputs match the behavior of a 74x49.
DO NOT COPY• If ENHEX = 1, then the outputs for digits 6 and 9 have tails, and the outputs for digits
A–F are controlled by ERRDET.
• If ENHEX = 1 and ERRDET = 0, then the outputs for digits A–F look like the letters
A–F, as in the original program.
• If ENHEX = 1 and ERRDET = 1, then the output for digits A–F looks like the letter S.
5.43 A famous logic designer decided to quit teaching and make a fortune by fabricat-
ing huge quantities of the MSI circuit shown in Figure X5.47.
5-44 (a)Label the inputs and outputs of the circuit with appropriate signal names, including
DO NOT COPYactive-levelindications.
5-45 (b)What does the circuit do? Be specific and account for all inputs and outputs.
5-46 (c)Draw the MSI logic symbol that would go on the data sheet of this wonderful
device.
5-47 (d)With what standard MSI parts does the new part compete? Do you think it would
DO NOT COPYbe successful in the MSI marketplace?
5.48 An FCT three-state buffer drives ten FCT inputs and a 4.7-KΩ pull-up resistor to
5.0 V. When the output changes from LOW to Hi-Z, estimate how long it takes for
the FCT inputs to see the output as HIGH. State any assumptions that you make.
5.49 On a three-state bus, ten FCT three-state buffers are driving ten FCT inputs and a
DO NOT COPY4.7-KΩ pull-up resistor to 5.0 V. Assuming that no other devices are driving the
bus, estimate how long the bus signal remains at a valid logic level when an active
output enters the Hi-Z state. State any assumptions that you make.
5.50 Design a 10-to-4 encoder with inputs in the 1-out-of-10 code and outputs in BCD.
DO NOT COPY5.51 Draw the logic diagram for a 16-to-4 encoder using just four 8-inputNAND gates.
What are the active levels of the inputs and outputs in your design?
Copyright © 1999 by John F. Wakerly Copying Prohibited
Exercises 421
DO NOT COPY
DO NOT COPY
DO NOT COPY
DO NOT COPY
DO NOT COPYFigureX5.47
5.52 Draw the logic diagram for a circuit that uses the 74x148 to resolve priority
among eight active-high inputs, I0–I7, where I7 has the highest priority. The cir-
cuit should produce active-high address outputs A2–A0 to indicate the number of
DO NOT COPYthe highest-priority asserted input. If no input is asserted, then A2–A0 should be
111 and an IDLE output should be asserted. You may use discrete gates in addition
to the ’148. Be sure to name all signals with the proper active levels.
5.53 Draw the logic diagram for a circuit that resolves priority among eight active-low
inputs, I0_L–I7_L, where I0_L has the highest priority. The circuit should produce
DO NOT COPYactive-high address outputs A2–A0 to indicate the number of the highest-priority
asserted input. If at least one input is asserted, then an AVALID output should be
asserted. Be sure to name all signals with the proper active levels. This circuit can
be built with a single 74x148 and no other gates.
5.54 A purpose of Exercise 5.53 was to demonstrate that it is not always possible to
DO NOT COPYmaintain consistency in active-level notation unless you are willing to define
alternate logic symbols for MSI parts that can be used in different ways. Define
an alternate symbol for the 74x148 that provides this consistency in
Exercise 5.53.
5.55 Design a combinational circuit with eight active-low request inputs, R0_L–R7_L,
DO NOT COPYand eight outputs, A2–A0, AVALID, B2–B0, and BVALID. The R0_L–R7_L inputs
and A2–A0 and AVALID outputs are defined as in Exercise 5.53. The B2–B0 and
BVALID outputs identify the second-highest priority request input that is asserted.
Copyright © 1999 by John F. Wakerly Copying Prohibited
422 Chapter 5 Combinational Logic Design Practices COPY
DO NOTA
DO NOT COPYFigureX5.59 Z
B
DO NOT COPYS
You should be able to design this circuit with no more than six SSI and MSI pack-
ages, but don’t use more than 10 in any case.
5.56 Repeat Exercise 5.55 using ABEL. Does the design fit into a single GAL20V8?
5.57 Repeat Exercise 5.55 using VHDL.
5.58 Design a 3-input, 5-bit multiplexer that fits in a 24-pin IC package. Write the truth
table and draw a logic diagram and logic symbol for your multiplexer.
DO NOT COPY5.59 Write the truth table and a logic diagram for the logic function performed by the
CMOS circuit in Figure X5.59. (The circuit contains transmission gates, which
were introduced in Section 3.7.1.)
5.60 A famous logic designer decided to quit teaching and make a fortune by fabricat-
DO NOT COPYing huge quantities of the MSI circuit shown in Figure X5.64.
5-61 (a)Label the inputs and outputs of the circuit with appropriate signal names, including
active-level indications.
5-62 (b)What does the circuit do? Be specific and account for all inputs and outputs.
5-63 (c)Draw the MSI logic symbol that would go on the data sheet of this wonderful
DO NOT COPYdevice.
5-64 (d)With what standard MSI parts does the new part compete? Do you think it would
be successful in the MSI marketplace?
DO NOT COPYbarrelshifter
5.65 A 16-bit barrel shifter is a combinational logic circuit with 16 data inputs, 16 data
outputs, and 4 control inputs. The output word equals the input word, rotated by
a number of bit positions specified by the control inputs. For example, if the input
word equals ABCDEFGHIJKLMNOP (each letter represents one bit), and the con-
trol inputs are 0101 (5), then the output word is FGHIJKLMNOPABCDE. Design
DO NOT COPYa 16-bit barrel shifter using combinational MSI parts discussed in this chapter.
Your design should contain 20 or fewer ICs. Do not draw a complete schematic,
but sketch and describe your design in general terms and indicate the types and
total number of ICs required.
5.66 Write an ABEL program for the barrel shifter in Exercise 5.65.
5.67 Write a VHDL program for the barrel shifter in Exercise 5.65.
5.68 Show how to realize the 4-input, 18-bit multiplexer with the functionality
DO NOT COPYdescribed in Table 5-39 using 18 74x151s.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Exercises 423
DO NOT COPY
DO NOT COPY
DO NOT COPYFigureX5.64
DO NOT COPY
DO NOT COPY5.69 Show how to realize the 4-input, 18-bit multiplexer with the functionality of
Table 5-39 using 9 74x153s and a “code converter” with inputs S2–S0 and
outputs C1,C0 such that [C1,C0] = 00–11 when S2–S0 selects A–D, respectively.
5.70 Design a 3-input, 2-output combinational circuit that performs the code conver-
sion specified in the previous exercise, using discrete gates.
DO NOT COPY5.71 Add a three-state-output control input OE to the VHDL multiplexer program in
Table 5-42. Your solution should have only one process.
5.72 A digital designer who built the circuit in Figure 5-75 accidentally used 74x00s
instead of ’08s in the circuit, and found that the circuit still worked, except for a
change in the active level of the ERROR signal. How was this possible?
DO NOT COPY5.73 What logic function is performed by the CMOS circuit shown in Figure X5.73?
DO NOT COPYA FigureX5.73
Z
DO NOT COPY
B
Copyright © 1999 by John F. Wakerly Copying Prohibited
424 Chapter 5 Combinational Logic Design Practices COPY
DO NA OT
DO NOT COPY
Figure X5.75
Z
DO NOT COPY
DO NOT COPY
B
C
DO NOT COPY5.74 An odd-parity circuit with 2n inputs can be built with 2n-1 XOR gates. Describe
two different structures for this circuit, one of which gives a minimum worst-case
input to output propagation delay and the other of which gives a maximum. For
each structure, state the worst-case number of XOR-gate delays, and describe a
situation where that structure might be preferred over the other.
DO NOT COPY5.75 Write the truth table and a logic diagram for the logic function performed by the
CMOS circuit in Figure X5.75.
5.76 Write a 4-step iterative algorithm corresponding to the iterative comparator cir-
cuit of Figure 5-79.
5.77 Design a 16-bit comparator using five 74x85s in a tree-like structure, such that
DO NOT COPYthe maximum delay for a comparison equals twice the delay of one 74x85.
5.78 Starting with a manufacturer’s logic diagram for the 74x85, write a logic expres-
sion for the ALTBOUT output, and prove that it algebraically equals the expression
derived in Drill 5.27.
DO NOT COPY5.79 Design a comparator similar to the 74x85 that uses the opposite cascading order.
That is, to perform a 12-bit comparison, the cascading outputs of the high-order
comparator would drive the cascading inputs of the mid-order comparator, and
DO NOT COPYthe mid-order outputs would drive the low-order inputs. You needn’t do a com-
plete logic design and schematic; a truth table and an application note showing
the interconnection for a 12-bit comparison are sufficient.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Exercises 425
5.80 Design a 24-bit comparator using three 74x682s and additional gates as required.
Your circuit should compare two 24-bit unsigned numbers P and Q and produce
DO NOT COPYtwo output bits that indicate whether P = Q or P > Q.
5.81 Draw a 6-variable Karnaugh map for the s2 function of Drill 5.29, and find all of
its prime implicants. Using the 6-variable map format of Exercise 4.66, label the
variables in the order x0, y0, x2, y2, x1, y1 instead of U, V, W, X, Y, Z. You need not
write out the algebraic product corresponding to each prime implicant; simply
DO NOT COPYidentify each one with a number (1, 2, 3, …) on the map. Then make a list that
shows for each prime implicant whether or not it is essential and how many inputs
are needed on the corresponding AND gate.
5.82 Starting with the logic diagram for the 74x283 in Figure 5-90, write a logic
expression for the S2 output in terms of the inputs, and prove that it does indeed
DO NOT COPYequal the third sum bit in a binary addition as advertised. You may assume that c0
= 0 (i.e., ignore c0).
5.83 Using the information in Table 5-3, determine the maximum propagation delay
from any A or B bus input to any F bus output of the 16-bit carry lookahead adder
of Figure 5-95. You may use the “worst-case” analysis method.
DO NOT COPY5.84 Referring to the data sheet of a 74S182 carry lookahead circuit, determine wheth-
er or not its outputs match the equations given in Section 5.10.7.
5.85 Estimate the number of product terms in a minimal sum-of-products expression
for the c32 output of a 32-bit binary adder. Be more specific than “billions and bil-
lions,” and justify your answer.
DO NOT COPY5.86 Draw the logic diagram for a 64-bit ALU using sixteen 74x181s and five 74S182s
for full carry lookahead (two levels of ’182s). For the ’181s, you need only show
the CIN inputs and G_L and P_L outputs.
5.87 Show how to build all four of the following functions using one SSI package and
one 74x138.
DO NOT COPYF1 = X′ ⋅ Y′ ⋅ Z′ +X ⋅ Y ⋅ Z F2= X′⋅ Y′ ⋅ Z+X ⋅Y ⋅Z′
F3 = X′ ⋅ Y ⋅ Z′ + X ⋅ Y′ ⋅ Z F4 = X ⋅ Y′ ⋅ Z′ + X′ ⋅ Y ⋅ Z
5.88 Design a customized decoder with the function table in Table X5.88 using MSI
DO NOT COPYand SSI parts. Minimize the number of IC packages in your design.
CS_L A2 A1 A0 Output to assert Ta b l e X 5 . 8 8
1 x xx none
0 0 0x BILL_L
MARY_L
DO NOT COPY0 0 x 0
0 0 1x JOAN_L
0 0 x1 PAUL_L
0 1 0x
0 1 x0 ANNA_L
FRED_L
DO NOT COPY0 1 1 x DAVE_L
0 1 x1 KATE_L
Copyright © 1999 by John F. Wakerly Copying Prohibited
426 Chapter 5 Combinational Logic Design Practices
5.89 Repeat Exercise 5.88 using ABEL and a single GAL16V8.
5.90 Repeat Exercise 5.88 using VHDL.
DO NOT COPY5.91 Using ABEL and a single GAL16V8, design a customized multiplexer with four
3-bit input buses P, Q, R, T, and three select inputs S2–S0 that choose one of the
buses to drive a 3-bit output bus Y according to Table X5.91.
DO NOT COPYTable X5.91
S2 S1 S0 Input to select
000 P
001 P
DO NOT COPY0 1 0 P
011Q
100P
101P
110 R
111 T
5.92 Design a customized multiplexer with four 8-bit input buses P, Q, R, and T, select-
DO NOT COPYing one of the buses to drive a 8-bit output bus Y according to Table X5.91. Use
two 74x153s and a code converter that maps the eight possible values on S2–S0
to four select codes for the ‘153. Choose a code that minimizes the size and prop-
agation delay of the code converter.
5.93 Design a customized multiplexer with five 4-bit input buses A, B, C, D, and E,
DO NOT COPYselecting one of the buses to drive a 4-bit output bus T according to Table X5.93.
You may use no more than three MSI and SSI ICs.
DO NOT COPYS2 S1 S0 Input to select Table X5.93 A
000
001 B
010 A
DO NOT COPY0 1 1 C
100A
101D
110A
111 E
5.94 Repeat Exercise 5.93 using ABEL and one or more PAL/GAL devices from this
DO NOT COPYchapter. Minimize the number and size of the GAL devices.
5.95 Design a 3-bit equality checker with six inputs, SLOT[2–0] and GRANT[2–0], and
DO one active-low output, MATCH_L. The SLOT inputs are connected to fixed values
NOT COPYwhen the circuit installed in the system, but the GRANT values are changed on a
cycle-by-cycle basis during normal operation of the system. Using only SSI and
MSI parts that appear in Tables 5-2 and 5-3, design a comparator with the shortest
possible maximum propagation delay from GRANT[2–0] to MATCH_L. (Note:
Copyright © 1999 by John F. Wakerly Copying Prohibited
Exercises 427
The author had to solve this problem “in real life” to shave 2 ns off the critical-
path delay in a 25-MHz system design.)
DO NOT COPY5.96 Design a combinational circuit whose inputs are two 8-bit unsigned binary inte-
gers, X and Y, and a control signal MIN/MAX. The output of the circuit is an 8-bit
unsigned binary integer Z such that Z = 0 if X = Y; otherwise, Z = min(X,Y) if MIN/
MAX = 1, and Z = max(X,Y) if MIN/MAX = 0.
5.97 Design a combinational circuit whose inputs are two 8-bit unsigned binary inte-
DO NOT COPYgers, X and Y, and whose output is an 8-bit unsigned binary integer Z = max(X,Y).
For this exercise, you may use any of the 74x SSI and MSI components intro-
duced in this chapter except the 74x682.
DO NOT COPY
DO NOT COPY
DO NOT COPY
DO NOT COPY
DO NOT COPY
DO NOT COPY
DO NOT COPY
Copyright © 1999 by John F. Wakerly Copying Prohibited
428 Chapter 5 Combinational Logic Design Practices
comparator DO NOT 6c h a p t e r
X >Y
max (X, Y) COPY
mux
mux
mux
DO NOTmin(X,Y)
COPYCombinational Design Examples
•••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• SDO NOTo far, we have looked at basic principles in several areas—number
systems, digital circuits, and combinational logic—and we have
described many of the basic building blocks of combinational
COPYdesign—decoders, multiplexers, and the like. All of that is a needed
foundation, but the ultimate goal of studying digital design is eventually to
be able to solve real problems by designing digital systems (well, duh…).
That usually requires experience beyond what you can get by reading a
textbook. We’ll try to get you started by presenting a number of larger
DO NOTcombinational design examples in this chapter.
The chapter is divided into three sections. The first section gives
design examples using combinational building blocks. While the examples
are written in terms of MSI functions, the same functions are widely used in
ASIC and schematic-based FPGA design. The idea of these examples is to
COPYshow that you can often express a combinational function using a collection
of smaller building blocks. This is important for a couple of reasons: a
hierarchical approach usually simplifies the overall design task, and the
smaller building blocks often have a more efficient, optimized realization in
FPGA and ASIC cells than what you’d get if you wrote a larger, monolithic
DO NOTdescription in an HDL and then just hit the “synthesize” button.
The second section gives design examples using ABEL. These designs
are all targeted to small PLDs such as 16V8s and 20V8s. Besides the general
use of the ABEL language, some of the examples illustrate the partitioning
Copyright © 1999 by John F. Wakerly Copying Prohibited 463
464 Chapter 6 Combinational Design Examples
decisions that a designer must make when an entire circuit does not fit into a
single component.
DO NOT COPYA VHDL-based approach is especially appropriate for larger designs that
will be realized in a single CPLD, FPGA or ASIC, as described in the third sec-
tion. You may notice that these examples do not target a specific CPLD or
FPGA. Indeed, this is one of the benefits of HDL-based design; most or all of the
design effort is “portable” and can be targeted to any of a variety of technologies.
DO NOT COPYThe only prerequisites for this chapter are the chapters that precede it. The
three sections are written to be pretty much independent of each other, so you
don’t have to read about ABEL if you’re only interested in VHDL, or vice versa.
Also, the rest of the book is written so that you can read this chapter now or skip
DO NOT COPYitandcomeback later.
6.1 Building-Block Design Examples
DO NOT COPYbarrelshifter
6.1.1 Barrel Shifter
A barrel shifter is a combinational logic circuit with n data inputs, n data
outputs, and a set of control inputs that specify how to shift the data between
input and output. A barrel shifter that is part of a microprocessor CPU can
typically specify the direction of shift (left or right), the type of shift (circular,
arithmetic, or logical), and the amount of shift (typically 0 to n–1 bits, but
DO NOT COPYsometimes 1 to n bits).
In this subsection, we’ll look at the design of a simple 16-bit barrel shifter
that does left circular shifts only, using a 4-bit control input S[3:0] to specify the
amount of shift. For example, if the input word is ABCDEFGHGIHKLMNOP
(where each letter represents one bit), and the control input is 0101 (5), then the
DO NOT COPYoutput word is FGHGIHKLMNOPABCDE.
From one point of view, this problem is deceptively simple. Each output bit
can be obtained from a 16-input multiplexer controlled by the shift-control
inputs, which each multiplexer data input connected to the appropriate On the
other hand, when you look at the details of the design, you’ll see that there are
DO NOT COPYtrade-offs in the speed and size of the circuit.
Let us first consider a design that uses off-the-shelf MSI multiplexers. A
16-input, one-bit multiplexer can be built using two 74x151s, by applying S3
and its complement to the EN_L inputs and combining the Y_L data outputs with
a NAND gate, as we showed in Figure 5-66 for a 32-input multiplexer. The low-
DO NOT COPYorder shift-control inputs, S2–S0. connect to the like-named select inputs of the
’151s.
We complete the design by replicating this 16-input multiplexer 16 times
and hooking up the data inputs appropriately, as shown in Figure 6-1. The top
DO NOT COPY’151 of each pair is enabled by S3_L, and the bottom one by S3; the remaining
select bits are connected to all 32 ’151s. Data inputs D0–D7 of each ’151 are
connected to the DIN inputs in the listed order from left to right.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 6.1 Building-Block Design Examples 465
DIN[15:8]74x151DOUT[15]
74x151
DO NOT COPYDIN[7:0]
DIN[14:7] 74x151
DOUT[14]
DIN[6:0,15]74x151
74x151
DO NOT COPYDIN[13:6]
DOUT[13]
DIN[5:0,15:14] 74x151
DIN[1:0,15:10]74x151DOUT[1]
74x151
DO NOT COPYDIN[9:2]
DIN[0,15:9]
DIN[8:1] 74x151 Figure 6-1
74x151 One approach to
building a 16-bit
barrel shifter.
DO NOT COPYDIN[15:0]
S3_L DOUT[0]
DOUT[15:0]
S3 S[2-0]
S[3:0]DO NOT COPYThe first row of Table 6-1 shows the characteristics of this first approach.
About 36 chips (32 74x151s, 4 74x00s, and 1/6 74x04) are used in the MSI/SSI
realization. We can reduce this to 32 chips by replacing the 74x151s with
74x251s and tying their three-state Y outputs together, as tabulated in the second
row. Both of these designs have very heavy loading on the control inputs; each of
DO NOT COPYthe control bits S[2:0] must be connected to the like-named select input of all 32
multiplexers. The data inputs are also fairly heavily loaded; each data bit must
connect to 16 different multiplexer data inputs, corresponding to the 16 possible
shift amounts. However, assuming that the heavy control and data loads don’t
slow things down too much, the 74x251-based approach yields the shortest data
DO NOT COPYdelay, with each data bit passing through just one multiplexer.
Alternatively, we could build the barrel shifter using 16 74x157 2-input,
4-bit multiplexers, as tabulated in the last row of the table. We start by using four
74x157s to make a 2-input, 16-bit multiplexer. Then, we can hook up a first set
DO NOT COPYMultiplexer
Data Data Control Total Ta ble 6-1
Component Loading Delay Loading ICs Properties of four
DO74x15116 NOT COPYdifferent barrel-shifter
74x251 16 2 32 36 design approaches.
74x153 4 1 32 32
2 8 16
74x157 2 4 4 16
Copyright © 1999 by John F. Wakerly Copying Prohibited
466 Chapter 6 Combinational Design Examples
DIN[15:12]74x157X[15:12] X[15:12] 74x157 Y[15:12] Y[15:12] 74x157 Z[15:12] Z[15:12] 74x157 DOUT[15:12]
X[13:10] Y[11:8] Z[7:4]
DO NOT COPYDIN[14:11]
DIN[11:8] X[11:8] Y[11:8] Z[11:8]
DIN[10:7] X[11:8] X[9:6] Y[11:8] Y[7:4] Z[11:8] Z[3:0] DOUT[11:8]
74x157 74x157 74x157 74x157
DIN[7:4] X[7:4] Y[7:4] COPYZ[7:4] Z[7:4]
X[5:2] Y[3:0] 74x157 Z[15:12]
DO NOTDIN[6:3]
X[7:4] Y[7:4] 74x157 DOUT[7:4]
74x157 74x157
DIN[3:0] X[3:0] Y[3:0] Z[3:0]
X[3:0] Y[3:0] Z[3:0] DOUT[3:0]
DIN[2:0,15] 74x157 X[1:0,15:14] 74x157 Y[15:12] 74x157 74x157
DIN[15:0] Z[11:8]
DO NOT COPYS[3:0]
S0 S1 S2 S3 DOUT[15:0]
Figure 6-2 A second approach to building a 16-bit barrel shifter.
of four ’157s controlled by S0 to shift the input word left by 0 or 1 bit. The data
DO NOT COPYoutputs of this set are connected to the inputs of a second set, controlled by S1,
which shifts its input word left by 0 or 2 bits. Continuing the cascade, a third and
fourth set are controlled by S2 and S3 to shift selectively by 4 and 8 bits, as
shown in Figure 6-2. Here, the 1A-4A and 1B-4B inputs and the 1Y-4Y outputs of
each ’157 are connected to the indicated signals in the listed order from left to
DO NOT COPYright.
The ’157-based approach requires only half as many MSI packages and
has far less loading on the control and data inputs. On the other hand, it has the
longest data-path delay, since each data bit must pass through four 74x157s.
Halfway between the two approaches, we can use eight 74x153 4-input,
DO NOT COPY2-bit multiplexers two build a 4-input, 16-bit multiplexer. Cascading two sets of
these, we can use S[3:2] to shift selectively by 0, 4, 8, or 12 bits, and S[1:0] to
shift by 0–3 bits. This approach has the performance characteristics shown in the
third row of Table 6-1, and would appear to be the best compromise if you don’t
need to have the absolutely shortest possible data delay.
DO NOT COPYThe same kind of considerations would apply if you were building the
barrel shifter out of ASIC cells instead of MSI parts, except you’d be counting
chip area instead of MSI/SSI packages.
Typical ASIC cell libraries have 1-bit-wide multiplexers, usually realized
with CMOS transmission gates, with 2 to 8 inputs. To build a larger multiplexer,
DO NOT COPYyou have to put together the appropriate combination of smaller cells. Besides
the kind of choices we encountered in the MSI example, you have the further
complication that CMOS delays are highly dependent on loading. Thus, depend-
ing on the approach, you must decide where to add buffers to the control lines,
DO NOT COPYthe data lines, or both to minimize loading-related delays. An approach that
looks good on paper, before analyzing these delays and adding buffers, may
actually turn out to have poorer delay or more chip area than another approach.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 6.1 Building-Block Design Examples 467
6.1.2 Simple Floating-Point Encoder
The previous example used multiple copies of a single building block, a multi-
DO NOT COPYplexer, and it was pretty obvious from the problem statement that a multiplexer
was the appropriate building block. The next example shows that you sometimes
have to look a little harder to see the solution in terms of known building blocks.
Now let’s look at a design problem whose MSI solution is not quite so
obvious, a “fixed-point to floating-point encoder.” An unsigned binary integer B
DO NOT COPYin the range 0 ≤ B < 211 can be represented by 11 bits in “fixed-point” format,
B = b10b9…b1b0. We can represent numbers in the same range with less preci-
sion using only 7 bits in a floating-point notation, F = M ⋅ 2E, where M is a 4-bit
mantissa m3m2m1m0 and E is a 3-bit exponent e2e1e0. The smallest integer in this
format is 0⋅20 and the largest is (24−1) ⋅ 27.
DO NOT COPYGiven an 11-bit fixed-point integer B, we can convert it to our 7-bit float-
ing-point notation by “picking off” four high-order bits beginning with the most
significant 1, for example,
11010110100 = 1101 ⋅ 27 + 0110100
DO NOT COPY00100101111 = 1001 ⋅ 25 + 01111
00000111110 = 1111 ⋅ 22 + 10
00000001011 = 1011 ⋅ 20 + 0
DO NOT COPY00000000010 = 0010 ⋅ 20 + 0
The last term in each equation is a truncation error that results from the loss of
precision in the conversion. Corresponding to this conversion operation, we can
write the specification for a fixed-point to floating-point encoder circuit:
DO NOT COPY• A combinational circuit is to convert an 11-bit unsigned binary integer B into
a 7-bit floating-point number M,E, where M and E have 4 and 3 bits, respec-
tively. The numbers have the relationship B = M ⋅2E + T, where T is the
truncation error, 0 ≤ T < 2E.
Starting with a problem statement like the one above, it takes some
DO NOT COPYcreativity to come up with an efficient circuit design—the specification gives no
clue. However, we can get some ideas by looking at how we converted numbers
by hand earlier. We basically scanned each input number from left to right to find
the first position containing a 1, stopping at the b3 position if no 1 was found. We
picked off four bits starting at that position to use as the mantissa, and the start-
DO NOT COPYing position number determined the exponent. These operations are beginning to
sound like MSI building blocks.
“Scanning for the first 1” is what a generic priority encoder does. The out-
put of the priority encoder is a number that tells us the position of the first 1. The
DO NOT COPYposition number determines the exponent; first-1 positions of b10 − b3 imply
exponents of 7–0, and positions of b2 − b0 or no-1-found imply an exponent of 0.
Therefore, we can scan for the first 1 with an 8-input priority encoder with inputs
Copyright © 1999 by John F. Wakerly Copying Prohibited
468 Chapter 6 Combinational Design Examples COPYE2_L
E1_L
DO NOT
E0_L
M3_L
74x151
DO NOT74x148 COPY7 EN
DO 5 EI 11 A
DO B10_L 4 I7 9 10 B
9C
B_L[10:0] A0 B9_L 4 D0
DO 3NOTB9_LI6 7 COPYB8_L 3 D1
2 I5 B7_L2 D2
1B8_LI4 A1 B6_L1 D3
13B7_LI3 B5_L15 D4
B6_L 6 B4_L14 D5
5
A2
Y M2_L
14 Y6
GS
B5_L 12 I2 15
EO
NOTB4_L 11
13 D6
B3_L 10 12 D7
74x151
I1 COPYB3_L
I0 B2_L
U1 U2
7 EN
NOT COPYB8_L 11 A
10 B
9C
4 D0
B7_L 3 D1
DO NOT COPYB6_L 2 D2
B5_L1 D3
B4_L15 D4
B3_L14 D5
5
Y M1_L
Y6
B2_L 13 D6
12 D7
DO NOT COPYB1_L U3
74x151
7 EN
11 A
DO NOT COPYB7_L 10 B
NOT B6_L9C
Figure 6-3 4 D0
A combinational 3 D1
fixed-point to floating-
B5_L 2 D2
DOpoint encoder.
COPYB4_L 1 D3 5
B3_L15 D4
B2_L14 D5 Y M0_L
B1_L13 D6 Y6
B0_L 12 D7
U4
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 6.1 Building-Block Design Examples 469
I7 (highest priority) through I0 connected to b10 − b3. We can use the priority
encoder’s A2 – A0 outputs directly as the exponent, as long as the no-1-found
DO NOT COPYcaseproducesA2 –A0 = 000.
“Picking off four bits” sounds like a “selecting” or multiplexing operation.
The 3-bit exponent determines which four bits of B we pick off, so we can use
the exponent bits to control an 8-input, 4-bit multiplexer that selects the appro-
priate four bits of B to form M.
DO NOT COPYAn MSI circuit that results from these ideas is shown in Figure 6-3. It con-
tains several optimizations:
• Since the available MSI priority encoder, the 74x148, has active-low
inputs, the input number B is assumed to be available on an active-low bus
DO NOT COPYB_L[10:0]. If only an active-high version of B is available, then eight
inverters can be used to obtain the active-low version.
• If you think about the conversion operation a while, you’ll realize that the
most significant bit of the mantissa, m3, is always 1, except in the no-1-
found case. The ’148 has a GS_L output that indicates this case, allowing
DO NOT COPYus to eliminate the multiplexer for m3.
• The ’148 has active-low outputs, so the exponent bits (E0_L–E2_L) are
produced in active-low form. Naturally, three inverters could be used to
produce an active-high version.
DO NOT COPY• Since everything else is active-low, active-low mantissa bits are used too.
Active-high bits are also readily available on the ’148 EO_L and the ’151
Y_L outputs.
Strictly speaking, the multiplexers in Figure 6-3 are drawn incorrectly. The
DO NOT COPY74x151 symbol can be drawn alternatively as shown in Figure 6-4. In words, if
the multiplexer’s data inputs are active low, then the data outputs have an active
level opposite that shown in the original symbol. The “active-low-data” symbol
74x151
DO NOT COPY7 EN
11 A Figure 6-4
Alternate logic symbol
for the 74x151 8-input
10 B multiplexer.
9C
4 D0Y5
Y6
DO NOT COPY3 D1
2 D2
1 D3
15 D4
14 D5
DO NOT COPY13 D6
12 D7
Copyright © 1999 by John F. Wakerly Copying Prohibited
470 Chapter 6 Combinational Design Examples
should be preferred in Figure 6-3, since the active levels of the ’151 inputs and
outputs would then match their signal names. However, in data transfer and
DO NOT COPYstorage applications, designers (and the book) don’t always “go by the book.” It
is usually clear from the context that a multiplexer (or a multibit register, in
Section 8.2.5) does not alter the active level of its data.
6.1.3 Dual-Priority Encoder
DO NOT COPYQuite often MSI building blocks need a little help from their friends—ordinary
gates— to get the job done. In this example, we’d like to build a priority encoder
that identifies not only the highest but also the second-highest priority asserted
signal among a set of eight request inputs.
We’ll assume for this example that the request inputs are active low and are
DO NOT COPYnamed R0_L–R7_L, where R0_L has the highest priority. We’ll use A2–A0 and
AVALID to identify the highest-priority request, where AVALID is asserted only
if at least one request input is asserted. We’ll use B2–B0 and BVALID to identify
the second-highest-priority request, where BVALID is asserted only if at least
two request inputs are asserted.
DO NOT COPYFinding the highest-priority request is easy enough, we can just use a
74x148. To find the second highest-priority request, we can use another ’148,
but only if we first “knock out” the highest-priority request before applying the
request inputs. This can be done using a decoder to select a signal to knock out,
DO NOT COPYbased on A2–A0 and AVALID from the first ’148. These ideas are combined in
the solution shown in Figure 6-6. A 74x138 decoder asserts at most one of its
eight outputs, corresponding to the highest-priority request input. The outputs
are fed to a rank of NAND gates to “turn off” the highest-priority request.
A trick is used in this solution is to get active-high outputs from the ’148s,
DO NOT COPYas shown in Figure 6-5. We can rename the address outputs A2_L–A0_L to be
active high if we also change the name of the request input that is associated with
each output combination. In particular, we complement the bits of the request
number. In the redrawn symbol, request input I0 has the highest priority.
DO NOT COPY74x148
74x148
Figure 6-5 5 EI 5 DI
Alternate logic symbols4 I7A2 64 I0 A2 6
for the 74x148 8-input A1 7 A1 7
3 I6 A0 9 3 I1 A0 9
DO NOT COPYpriority encoder. 2 I5 2 I2
1 I4 1 I3
13 I3 13 I4
NOT COPY12 I2 GS 14
11 I1 EO 15
10 I0
DO 12 I5 IDLE 14
11 I6 AVALID 15
10 I7
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 6.1 Building-Block Design Examples 471
DO NOT COPYR[7:0]_L
74LS148 74LS138
Y0 15 D0_L
Y1 14 D1_L
Y2 13 D2_L
Y3 12 D3_L
5EI A0 9 A0 6 G1
I7 A1 7 A1 4 G2A
R0_L 4 I6 A2 6 A2 5 G2B
R1_L 3 I5
R2_L 2 I4 A[2–0] A0 1 A Y4 11 D4_L
R3_L 1 I3 A1 2 B Y5 10 D5_L
I2 GS 14 AVALID A2 3 C Y6 9 D6_L
DO NOT COPYR4_L 13I1EO 15 Y7 7 D7_L
I0
R5_L 12
R6_L 11 U2
DO NOT COPYR7_L 10
U1 A[2:0]
DO NOTU4 D_L[0-7] COPYAVALID
74LS04 74LS00
R0_L 1 2 R0 1 3 RD0_L
D0_L
2
U6
R1_L 3DO NOTU4 D1_L 5 COPY74LS148
4 R1 4 6 RD1_L
U6
R2_L 5 6 R2 9 8 RD2_L 5 EI
U6
U4 D2_L 10 A0 9 B0
11 RD3_L A1 7 B1
A2 6 B2
DO NOTU4 D3_L 13 COPY4 I7
R3_L 9 8 R3 12 3 I6
2 I5
1 I4
U6 B[2:0]
R4_L 11 10 R4 1 3 RD4_L 13 I3 GS 14
D4_L 2 U7
DO NOTR5_L 13U4 EO 15
6 RD5_L COPY12 I2 BVALID
12 11 I1
R5 4 10 I0
U4 D5_L 5
U7 U3
R6_L 1 2 R6 9
DO NOTU5 D7_L 13 8 RD6_L COPY
U5 D6_L 10 U7
R7_L 3 4 R7 12 11 RD7_L
U7
DO NOT COPYFigure 6-6 First-and second-highest priority encoder circuit.
Copyright © 1999 by John F. Wakerly Copying Prohibited
472 Chapter 6 Combinational Design Examples
6.1.4 Cascading Comparators
In Section 5.9.4, we showed how 74x85 4-bit comparators can be cascaded to
DO NOT COPYcreate larger comparators. Since the 74x85 uses a serial cascading scheme, it can
be used to build arbitrarily large comparators. The 74x682 8-bit comparator, on
the other hand, doesn’t have any cascading inputs and outputs at all. Thus, at first
glance, you might think that it can’t be used to build larger comparators. But
that’s not true.
DO NOT COPYIf you think about the nature of a large comparison, it is clear that two wide
inputs, say 32 bits (four bytes) each, are equal only if their corresponding bytes
are equal. If we’re trying to do a greater-than or less-than comparison, then the
corresponding most-significant that are not equal determine the result of the
comparison.
DO NOT COPYUsing these ideas, Figure 6-7 uses three 74x682 8-bit comparators to do
equality and greater-than comparison on two 24-bit operands. The 24-bit results
are derived from the individual 8-bit results using combinational logic for the
following equations:
DO NOT COPYPEQQ = EQ2⋅EQ1⋅EQ0
PGTQ = GT2 + EQ2 ⋅ GT1 + EQ2 ⋅ EQ1 ⋅ GT0
This “parallel” expansion approach is actually faster than the 74x85’s
serial cascading scheme, because it does not suffer the delay of propagating the
DO NOT COPYcascading signals through a cascade of comparators. The parallel approach can
be used to build very wide comparators using two-level AND-OR logic to
combine the 8-bit results, limited only by the fan-in constraints of the AND-OR
logic. Arbitrary large comparators can be made if you use additional levels of
DO NOT COPYlogictodothecombining.
6.1.5 Mode-Dependent Comparator
Quite often, the requirements for a digital-circuit application are specified in a
way that makes an MSI or other building-block solution obvious. For example,
DO NOT COPYconsider the following problem:
• Design a combinational circuit whose inputs are two 8-bit unsigned binary
integers, X and Y, and a control signal MIN/MAX. The output of the circuit is
an 8-bit unsigned binary integer Z such that Z = min(X,Y) if MIN/MAX = 1,
and Z = max(X,Y) if MIN/MAX = 0.
DO NOT COPYThis circuit is fairly easy to visualize in terms of MSI functions. Clearly, we can
use a comparator to determine whether X > Y. We can use the comparator’s
output to control multiplexers that produce min(X,Y) and max(X,Y), and we can
use another multiplexer to select one of these results depending on MIN/MAX.
DO NOT COPYFigure 6-8(a) is the block diagram of a circuit corresponding to this approach.
Our first solution approach works, but it’s more expensive than it needs to
be. Although it has three two-input multiplexers, there are only two input words,
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 6.1 Building-Block Design Examples 473
P[23:0] 74x682 74x682
DO NOT COPYQ[23:0]
P0 2 P0 P16 2 P0
Q0 3 Q0 Q16 3 Q0
P1 4 P1 P17 4 P1
Q1 5 Q1 Q17 5 Q1
P18 6 P2
DO NOT COPYP2 6 P2
Q2 7 Q2 19 EQ0_L Q18 7 Q2 19 EQ2_L
P3 8 P3 P EQ Q P19 8 P3 P EQ Q 1 GT2_L
Q19 9 Q3
P20 11 P4
Q20 12 Q4
P21 13 P5 P GT Q
Q4 12 Q4Q3 9 Q3
DO NOT COPYP5 13 P5 PGTQ
P4 11 P4
1 GT0_L
DOQ5 14 Q5 NOT COPYQ21 14 Q5
P6 15 P6 P22 15 P6
Q6 16 Q6 Q22 16 Q6
P7 17 P7 P23 17 P7
Q7 18 Q7 U1 Q23 18 Q7 U3
74x682
DO NOT COPYP8 2 P0
Q8 3 Q0 1 74x27
P9 4 P1
2 12
13
U4
3 74x27
Q10Q9 5 Q1 PEQQ
DO NOT COPYP11
P10 6 P2
7 Q2 19 EQ1_L
8 P3 P EQ Q
46
Q11 9 Q3
5
U4
P12 11 P4
Q12 12 Q4
P13 13 P5 P GT Q
DO NOT COPYQ13 14 Q5
P14 15 P6
1 GT1_L 74x02 74x27 74x02
2 11 8
1 10 8 9 10 PGTQ
39
U5
U5 U4
Q14 16 Q6 74x02
P15 17 P7
5
DO NOT COPYQ15 18 Q7 4
U2 Figure 6-7
6 24-bit comparator
U5
circuit.
X and Y, that may ultimately be selected and produced at the output of the cir-
cuit. Therefore, we should be able to use just a single two-input mux, and use
DO NOT COPYsome other logic to figure out which input to tell it to select. This approach is
shown in Figure 6-8(b) and (c). The “other logic” is very simple indeed, just a
single XOR gate.
Copyright © 1999 by John F. Wakerly Copying Prohibited
474 Chapter 6 Combinational Design Examples
DOMIN/MAX NOT COPYcomparator
X MIN/MAX
Y
X >Y X comparator X > Y other
DO logic
NOTmax (X, Y)
mux COPYY
mux z SELECTmuxZ
(a) mux (b)
DO NOT COPYmin(X,Y)
74LS682 74x157
(c) X0 2 P0 15 G 1Y 4
Y0 3 Q0 1S
X1 4 P1 2 1A
3 1B
DO NOT COPYY1 5 Q1
DO NOTX2 6 P2 COPY5 2A
Y27 Q2 19 6 2B2Y 7
X38 P3 P EQ Q 11 3A3Y 9
Y39 Q3 10 3B
11 P4 14 4A
13 4B
X412 Q4 74x86 4Y 12
Y413 P5 P GT Q U2
11 3
X5 2
Y5
14 Q5 U4 74x157 Z[7:0]
X6
15 P6 15 G
DO NOT COPYY6 1S
X716 Q6U1 2 1A
Y717 P7 3 1B
5 2A 1Y 4
18 Q7 6 2B 2Y 7
DO NOT COPYMIN/MAX 11 3A 3Y 9
U1 10 3B
X[7:0] 14 4A 4Y 12
13 4B U3
DO NOT COPYY[7:0]
Figure 6-8 Mode-dependent comparator circuit: (a) block diagram of a
DO NOT COPY“first-cut” solution; (b) block diagram of a more cost-effective
solution; (c) logic diagram for the second solution.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 6.2 Design Examples Using ABEL and PLDs 475
DON’T BE A The wastefulness of our original design approach in Figure 6-8(a) may have been
DO NOT COPYBLOCKHEAD obvious to you from the beginning, but it demonstrates an important approach to
designing with building blocks:
• Use standard building blocks to handle data, and look for ways that a single
block can perform different functions at different times or in different modes.
Design control circuits to select the appropriate functions as needed, to reduce
DO NOT COPYthe total parts count of the design.
As Figure 6-8(c) dramatically shows, this approach can save a lot of chips. When
designing with IC chips, you should not heed the slogan, “Have all you want, we’ll
DO NOT COPYmakemore”!
6.2 Design Examples Using ABEL and PLDs
6.2.1 Barrel Shifter
A barrel shifter, defined on page 464, is good example of something not to
DO NOT COPYdesign using PLDs. However, we can put ABEL to good use to describe a barrel
shifter’s function, and we’ll also see why a typical barrel shifter is not a good fit
for a PLD.
Table 6-2 shows the equations for a 16-bit barrel shifter with the same
DO NOT COPYfunctionality as the example on page 464—it does left circular shifts only, using
a 4-bit control input S[3..0] to specify the amount of shift. ABEL makes it easy
to specify the functionality of the overall circuit without worrying about how the
circuit might be partitioned into multiple chips. Also, ABEL dutifully generates
a minimal sum-of-products expression for each output bit. In this case, each out-
DO NOT COPYput requires 16 product terms.
Partitioning the 16-bit barrel shifter into multiple PLDs is a difficult task in
two different ways. First, it should be obvious that the nature of the function is
such that every output bit depends on every input bit. A PLD that produces, say,
the DOUT0 output must have all 16 DIN inputs and all four S inputs available to
DO NOT COPYit. So, a GAL16V8 definitely cannot be used; it has only 16 inputs.
The GAL20V8 is similar to the GAL16V8, with the addition of four input-
only pins. If we use all 20 available inputs, we are left with two output-only pins
(corresponding to the top and bottom outputs in Figure 5-27 on page 341). Thus,
it seems possible that we could realize the barrel shifter using eight 20V8 chips,
DO NOT COPYproducing two output bits per chip.
No, we still have a problem. The second dimension of difficulty in a PLD-
based barrel shifter is the number of product terms per output. The barrel shifter
requires 16, and the 20V8 provides only 7. We’re stuck—any realization of the
DO NOT COPYbarrel shifter in 20V8s is going to require multiple-pass logic. At this point, we
would be best advised to look at partitioning options along the lines that we did
in Section 6.1.1.
Copyright © 1999 by John F. Wakerly Copying Prohibited
476 Chapter 6 Combinational Design Examples
Table 6-2 COPY
ABEL program for a pin;
DO NOT16-bit barrel shifter. COPYpin istype 'com';
module barrel16
title '16-bit Barrel Shifter'
" Inputs and Outputs
DIN15..DIN0, S3..S0
DO NOTDOUT15..DOUT0
S = [S3..S0];
equations
[DOUT15..DOUT0] = (S==0) & [DIN15..DIN0]...
# (S==1) & [DIN14..DIN0,DIN15]
# (S==2) & [DIN13..DIN0,DIN15..DIN14]
DO NOT COPY# (S==3) & [DIN12..DIN0,DIN15..DIN13]
# (S==12) & [DIN3..DIN0,DIN15..DIN4]
DO NOT COPY# (S==13) & [DIN2..DIN0,DIN15..DIN3]
# (S==14) & [DIN1..DIN0,DIN15..DIN2]
# (S==15) & [DIN0,DIN15..DIN1];
end barrel16
The 16-bit barrel shifter can be realized without much difficulty in a larger
DO NOT COPYprogrammable device, that is, in a CPLD or an FPGA with enough I/O pins.
However, imagine that we were trying to design a 32-bit or 64-bit barrel shifter.
Clearly, we would need to use a device with even more I/O pins, but that’s not
all. The number of product terms and the large amount of connectivity (all the
inputs connect to all the outputs) would still be challenging.
DO NOT COPYIndeed, a typical CPLD or FPGA fitter could have difficulty realizing a
large barrel shifter with small delay or even at all. There is a critical resource that
we took for granted in the partitioned, building-block barrel-shifter designs of
Section 6.1.1—wires! An FPGA is somewhat limited in its internal connectivity,
and a CPLD is even more so. Thus, even with modern FPGA and CPLD design
DO NOT COPYtools, you may still have to “use your head” to partition the design in a way that
helps the tools do their job.
Barrel shifters can be even more complex than what we’ve shown so far.
Just for fun, Table 6-3 shows the design for a barrel shifter that supports six
different kinds of shifting. This requires even more product terms, up to 40 per
DO NOT COPYoutput! Although you’d never build this device in a PLD, CPLD, or small FPGA,
the minimized ABEL equations are useful because they can help you understand
the effects of some of your design choices. For example, by changing the coding
of SLA and SRA to [1,.X.,0] and [1,.X.,1], you can reduce the total number
DO NOT COPYof product terms in the design from 624 to 608. You can save more product terms
by changing the coding of the shift amount for some shifts (see Exercise 6.3).
The savings from these changes may carry over to other design approaches.
Copyright © 1999 by John F. Wakerly Copying Prohibited
Section 6.2 Design Examples Using ABEL and PLDs 477
Ta b l e 6 - 3 ABEL program for a multi-mode 16-bit barrel shifter.
DO NOT COPYmodule barrl16f
Title 'Multi-mode 16-bit Barrel Shifter'
" Inputs and Outputs
DIN15..DIN0, S3..S0, C2..C0
DOUT15..DOUT0
DO NOT COPYS = [S3..S0]; C = [C2..C0]; " Shift amount and mode
pin;
pin istype 'com';
L = DIN15; R = DIN0; " MSB and LSB
ROL = (C == [0,0,0]); " Rotate (circular shift) left
ROR = (C == [0,0,1]); " Rotate (circular shift) right
SLL = (C == [0,1,0]); " Shift logical left (shift in 0s)
DO NOT COPYSRL = (C == [0,1,1]); " Shift logical right (shift in 0s)
SLA = (C == [1,0,0]); " Shift left arithmetic (replicate LSB)
SRA = (C == [1,0,1]); " Shift right arithmetic (replicate MSB)
equations
DO NOT COPY[DOUT15..DOUT0] = ROL & (S==0) & [DIN15..DIN0]
# ROL & (S==1) & [DIN14..DIN0,DIN15]
# ROL & (S==2) & [DIN13..DIN0,DIN15..DIN14]
...
# ROL & (S==15) & [DIN0,DIN15..DIN1]
# ROR & (S==0) & [DIN15..DIN0]
DO NOT COPY# ROR & (S==1) & [DIN0,DIN15..DIN1]
...
# ROR & (S==14) & [DIN13..DIN0,DIN15..DIN14]
# ROR & (S==15) & [DIN14..DIN0,DIN15]
# SLL & (S==0) & [DIN15..DIN0]
DO NOT COPY# SLL & (S==1) & [DIN14..DIN0,0]
...
# SLL & (S==14) & [DIN1..DIN0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
# SLL & (S==15) & [DIN0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0]
# SRL & (S==0) & [DIN15..DIN0]
# SRL & (S==1) & [0,DIN15..DIN1]
DO NOT COPY...
# SRL & (S==14) & [0,0,0,0,0,0,0,0,0,0,0,0,0,0,DIN15..DIN14]
# SRL & (S==15) & [0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,DIN15]
# SLA & (S==0) & [DIN15..DIN0]
# SLA & (S==1) & [DIN14..DIN0,R]
...
DO NOT COPY# SLA & (S==14) & [DIN1..DIN0,R,R,R,R,R,R,R,R,R,R,R,R,R,R]
# SLA & (S==15) & [DIN0,R,R,R,R,R,R,R,R,R,R,R,R,R,R,R]
# SRA & (S==0) & [DIN15..DIN0]
# SRA & (S==1) & [L,DIN15..DIN1]
...
# SRA & (S==14) & [L,L,L,L,L,L,L,L,L,L,L,L,L,L,DIN15..DIN14]
DO NOT COPY# SRA & (S==15) & [L,L,L,L,L,L,L,L,L,L,L,L,L,L,L,DIN15];
end barrl16f
Copyright © 1999 by John F. Wakerly Copying Prohibited
478 Chapter 6 Combinational Design Examples
6.2.2 Simple Floating-Point Encoder
We defined a simple floating-point number format on page 467, and posed the
DO NOT COPYdesign problem of converting a number from fixed-point to this floating point
format. The I/O-pin requirements of this design are limited—11 inputs and 7
outputs—so we can potentially use a single PLD to replace the four parts that
were used in the MSI solution.
An ABEL program for the fixed-to-floating-point converter is given in
DO NOT COPYTable 6-4. The WHEN statement expresses the operation of determining the expo-
nent value E in a very natural way. Then E is used to select the appropriate bits of
B to use as the mantissa M.
Despite the deep nesting of the WHEN statement, only four product terms are
needed in the minimal sum for each bit of E. The equations for the M bits are not
DO NOT COPYtoo bad either, requiring only eight product terms each. Unfortunately, the
Table 6-4
An ABEL program
DO NOT COPYfor the fixed-point to
module fpenc
title 'Fixed-point to Floating-point Encoder'
FPENC device 'P20L8';
floating-point PLD. " Input and output pins
NOT COPYB10..B0
E2..E0, M3..M0
DO pin 1..11;
pin 21..15 istype 'com';
" Constant expressions
B = [B10..B0];
E = [E2..E0];
DO NOT COPYM = [M3..M0];
equations
WHEN B < 16 THEN E = 0;
ELSE WHEN B < 32 THEN E = 1;
DO NOT COPYELSE WHEN B < 64 THEN E = 2;
ELSE WHEN B < 128 THEN E = 3;
ELSE WHEN B < 256 THEN E = 4;
ELSE WHEN B < 512 THEN E = 5;
ELSE WHEN B < 1024 THEN E = 6;
ELSE E = 7;
DO NOT COPYM = (E==0) & [B3..B0]
# (E==1) & [B4..B1]
# (E==2) & [B5..B2]
# (E==3) & [B6..B3]
DO NOT COPY# (E==4) & [B7..B4]
# (E==5) & [B8..B5]
# (E==6) & [B9..B6]
# (E==7) & [B10..B7];
end fpenc
Copyright © 1999 by John F. Wakerly Copying Prohibited
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