digital design digital design digital design principles & practices ( PDFDrive ) (1)

Section 5.2 Circuit Timing 295

in typical applications. A logic designer who combines ICs in a larger circuit
uses the individual device specifications to analyze the overall circuit timing.

DO NOT COPYThe delay of a path through the overall circuit is the sum of the delays through

subpaths in the individual devices.

5.2.3 Timing Specifications
The timing specification for a device may give minimum, typical, and maximum

DO NOT COPYvalues for each propagation-delay path and transition direction:
• Maximum. This specification is the one that is most often used by experi- maximum delay
enced designers, since a path “never” has a propagation delay longer than
the maximum. However, the definition of “never” varies among logic
DO NOT COPYfamilies and manufacturers. For example, “maximum” propagation delays
of 74LS and 74S TTL devices are specified with VCC = 5 V, TA = 25ºC, and
almost no capacitive load. If the voltage or temperature is different, or if
the capacitive load is more than 15 pF, the delay may be longer. On the
other hand, a “maximum” propagation delay is specified for 74AC and
DO NOT COPY74ACT devices over the full operating voltage and temperature range, and
with a heavier capacitive load of 50 pF.

• Typical. This specification is the one that is most often used by designers typical delay
who don’t expect to be around when their product leaves the friendly envi-
ronment of the engineering lab and is shipped to customers. The “typical”

DO NOT COPYdelay is what you see from a device that was manufactured on a good day
and is operating under near-ideal conditions.

• Minimum. This is the smallest propagation delay that a path will ever minimum delay
exhibit. Most well-designed circuits don’t depend on this number; that is,

DO NOT COPYthey will work properly even if the delay is zero. That’s good because
manufacturers don’t specify minimum delay in most moderate-speed logic
families, including 74LS and 74S TTL. However, in high-speed families,
including ECL and 74AC and 74ACT CMOS, a nonzero minimum delay
is specified to help the designer ensure that timing requirements of latches

DO NOT COPYand flip-flops discussed in \secref{llff}, are met.
Table 5-2 lists the typical and maximum delays of several 74-series CMOS
and TTL gates. Table 5-3 does the same thing for most of the CMOS and TTL

DO NOT COPYMSI parts that are introduced later in this chapter.

HOW TYPICAL IS

DO NOT COPYTYPICAL?
Most ICs, perhaps 99%, really are manufactured on “good” days and exhibit delays

near the “typical” specifications. However, if you design a system that works only if

all of its 100 ICs meet the “typical” timing specs, probability theory suggests that
63% (1 − .99100) of the systems won’t work.But see the next box....

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296 Chapter 5 Combinational Logic Design Practices

DO NOT COPY74HCT
Ta b l e 5 - 2 Propagation delay in nanoseconds of selected 5-V CMOS and TTL SSI parts.

74AHCT 74LS

Typical Maximum Typical Maximum Typical Maximum

DO NOT’00,’10 COPYtpLH tpHL
Part number tpLH, tpHL tpLH, tpHL
35 9.0 9.0
11 tpLH tpHL tpLH tpHL tpLH tpHL
5.5 5.5 9 10 15 15

’02 9 29 3.4 4.5 8.5 8.5 10 10 15 15

11 ‘04 COPY8.5 8.59 10 15 15
11 8 10 15 20
DO NOT’08,’11 9.0 9.0
35 5.5 5.5
35 5.5 5.5

’14 16 48 5.5 5.5 9.0 9.0 15 15 22 22

’20 11 35 COPY9.0 9.09 10 15 15
’21 11 35 8 10 15 20
10 10 15 15
DO NOT’27 9 29 5.6 5.6
’30 11 35 8 13 15 20
’32 COPY8.5 8.5

DO NOT’86 (2 levels) 10 10
9 30 5.3 5.3 14 14 22 22
13 40 5.5 5.5 12 10 23 17

’86 (3 levels) 13 40 5.5 5.5 10 10 20 13 30 22

DO NOT COPY
A COROLLARY OF Murphy’s law states, “If something can go wrong, it will.” A corollary to this is, “If
MURPHY’S LAW you want something to go wrong, it won’t.”

In the boxed example on the previous page, you might think that you have a

DO NOT COPY63% chance of detecting the potential timing problems in the engineering lab. The
problems aren’t spread out evenly, though, since all ICs from a given batch tend to
behave about the same. Murphy’s Corollary says that all of the engineering proto-
types will be built with ICs from the same, “good” batches. Therefore, everything
works fine for a while, just long enough for the system to get into volume production

DO NOT COPYand for everyone to become complacent and self-congratulatory.
Then, unbeknownst to the production department, a “slow” batch of some IC
type arrives from a supplier and gets used in every system that is built, so that nothing
works. The production engineers scurry around trying to analyze the problem (not
easy, because the designer is long gone and didn’t bother to write a circuit descrip-
tion), and in the meantime the company loses big bucks because it is unable to ship

DO NOT COPYitsproduct.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.2 Circuit Timing 297

DO NOT COPY74HCT
Ta b l e 5 - 3 Propagation delay in nanoseconds of selected CMOS and TTL MSI parts.

74AHCT / FCT 74LS

Typical Maximum Typical Maximum Typical Maximum

Part From To tpLH,tpHL tpLH, tpHL tpLH, tpHL tpLH, tpHL tpLH tpHL tpLH tpHL
DO NOT COPYG2A,G2B output 20 41
’138 any select output (2) 23 45 8.1 / 5 13 / 9 11 18 27 39
45 8.1 / 5 13 / 9 21 20 18 32
any select output (3) 23 42 7.5 / 4 12 / 8 12 20

22

G1 output 22 42 7.1 / 4 11.5 / 8 14 13 26 38

’139 any select output (2) 14 43 6.5 / 5 10.5 / 9 13 22 20 33
DO NOT COPY’151 anyselect Y 14
any select output (3) 11 43 6.5 / 5 10.5 / 9 18 25 29 38
17
enable output 43 5.9 / 5 9.5 / 9 16 21 24 32

51 - / 5 - / 9 27 18 43 30

any select Y 18 54 - / 5 - / 9 14 20 23 32

DOany data Y NOT COPY16 48 -/ 4 -/7 20 16 32 26
any dataY 15 45 - / 4 - / 7 13 12 21 20
enable Y 12 36 - / 4 - / 7 26 20 42 32
enable Y 15 45 - / 4 - / 7 15 18 24 30

’153 any select output 14 43 - / 5 - / 9 19 25 29 38

any data
enable
’157 select

DO NOT COPYanydata
output 12 43 - / 4 - / 7 10 17 15 26
output 11
output 15 34 - / 4 - / 7 16 21 24 32
output 12
46 6.8 / 7 11.5 / 10.5 15 18 23 27

38 5.6 / 4 9.5 / 6 9 9 14 14

enable output 12 38 7.1 / 7 12.0 / 10.5 13 14 21 23

’182 any Gi, Pi C1–3 13 41 COPY4.5 4.5 77
DO NOTC0 C1–3 13 41 57 7.5 10.5
any Gi, Pi G 11 35 4.5 6.5 6.5 10
17 50 6.5 7 10 10.5
any Pi P

’280 any input EVEN 18 53 -/6 - / 10 33 29 50 45

any input ODD 19 56 -/6 - / 10 23 31 35 50
DO NOT COPYC0 C4 22
’283 C0 any Si 21 66 16 15 24 24
19
any Ai, Bi any Si 61 15 15 24 24

58 11 11 17 22

any Ai, Bi C4 20 60 11 12 17 17

’381 CIN any Fi COPY18 14 27 21
DO NOTany Ai, Bi anyFi 20 21 30 33
any Ai, Bi G 21 33 23 33
20 15 30 23
any Ai, Bi P

any select any Fi 35 34 53 51

any select G, P 31 32 47 48
DO NOT COPYanyPi
’682 any Pi PEQQ 26 69 -/7 - / 11 13 15 25 25
26
any Qi PEQQ 26 69 -/7 - / 11 14 15 25 25

PGTQ 69 -/9 - / 14 20 15 30 30

any Qi PGTQ 26 69 -/9 - / 14 21 19 30 30

Copyright © 1999 by John F. Wakerly Copying Prohibited

298 Chapter 5 Combinational Logic Design Practices

ESTIMATING If the minimum delay of an IC is not specified, a conservative designer assumes that

DO NOT COPYMINIMUM DELAYS it has a minimum delay of zero.
Some circuits won’t work if the propagation delay actually goes to zero, but
the cost of modifying a circuit to handle the zero-delay case may be unreasonable,
especially since this case is expected never to occur. To obtain a design that always
works under “reasonable” conditions, logic designers often estimate that ICs have

DO NOT COPYminimum delays of one-fourth to one-third of their published typical delays.

All inputs of an SSI gate have the same propagation delay to the output.

DO NOT COPYNote that TTL gates usually have different delays for LOW-to-HIGH and HIGH-
to-LOW transitions (tpLH and tpHL), but CMOS gates usually do not. CMOS
gates have a more symmetrical output driving capability, so any difference
between the two cases is usually not worth noting.
The delay from an input transition to the corresponding output transition

DO NOT COPYdepends on the internal path taken by the changing signal, and in larger circuits
the path may be different for different input combinations. For example, the
74LS86 2-input XOR gate is constructed from four NAND gates as shown in
Figure 5-70 on page 372, and has two different-length paths from either input to
the output. If one input is LOW, and the other is changed, the change propagates

DO NOT COPYthrough two NAND gates, and we observe the first set of delays shown in
Table 5-2. If one input is HIGH, and the other is changed, the change propagates
through three NAND gates internally, and we observe the second set of delays.
Similar behavior is exhibited by the 74LS138 and 74LS139 in Table 5-3.
However, the corresponding CMOS parts do not show these differences; they are

DO NOT COPYsmallenoughtobeignored.

5.2.4 Timing Analysis
To accurately analyze the timing of a circuit containing multiple SSI and

MSI devices, a designer may have to study its logical behavior in excruciating

DO NOT COPYdetail. For example, when TTL inverting gates (NAND, NOR, etc.) are placed in
series, a LOW-to-HIGH change at one gate’s output causes a HIGH-to-LOW
change at the next one’s, and so the differences between tpLH and tpHL tend to
average out. On the other hand, when noninverting gates (AND, OR, etc.) are

DO NOT COPYplaced in series, a transition causes all outputs to change in the same direction,
and so the gap between tpLH and tpHL tends to widen. As a student, you’ll have
the privilege of carrying out this sort of analysis in Drills 5.8–5.13.
The analysis gets more complicated if there are MSI devices in the delay
path, or if there are multiple paths from a given input signal to a given output

DO NOT COPYsignal. Thus, in large circuits, analysis of all of the different delay paths and
transition directions can be very complex.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.3 Combinational PLDs 299

To permit a simplified “worst-case” analysis, designers often use a single
worst-case delay specification that is the maximum of tpLH and tpHL specifica- worst-case delay

DO NOT COPYtions. The worst-case delay through a circuit is then computed as the sum of the

worst-case delays through the individual components, independent of the transi-
tion direction and other circuit conditions. This may give an overly pessimistic
view of the overall circuit delay, but it saves design time and it’s guaranteed to

DO NOT COPYwork.

5.2.5 Timing Analysis Tools
Sophisticated CAD tools for logic design make timing analysis even easier.
Their component libraries typically contain not only the logic symbols and
functional models for various logic elements, but also their timing models. A

DO NOT COPYsimulator allows you to apply input sequences and observe how and when out-
puts are produced in response. You typically can control whether minimum,

typical, maximum, or some combination of delay values are used.
Even with a simulator, you’re not completely off the hook. It’s usually up

the designer to supply the input sequences for which the simulator should

DO NOT COPYproduce outputs. Thus, you’ll need to have a good feel for what to look for and
how to stimulate your circuit to produce and observe the worst-case delays.

Some timing analysis programs can automatically find all possible delay
paths in a circuit, and print out a sorted list of them, starting with the slowest.

DO NOT COPYThese results may be overly pessimistic, however, as some paths may actually

not be used in normal operations of the circuit; the designer must still use some
intelligence to interpret the results properly.
COPY
5.3 Combinational PLDs

DO NOT5.3.1 Programmable Logic Arrays
Historically, the first PLDs were programmable logic arrays (PLAs). A PLA is programmable logic

a combinational, two-level AND-OR device that can be programmed to realize array (PLA)
any sum-of-products logic expression, subject to the size limitations of the

DO NOT COPYdevice.Limitations are
• the number of inputs (n), inputs

• the number of outputs (m), and outputs
• the number of product terms (p). product terms

DO NOT COPYWe might describe such a device as “an n × m PLA with p product terms.” In
general, p is far less than the number of n-variable minterms (2n). Thus, a PLA

cannot perform arbitrary n-input, m-output logic functions; its usefulness is
limited to functions that can be expressed in sum-of-products form using p or

DO NOT COPYfewer productterms.
An n × m PLA with p product terms contains p 2n-input AND gates and m
p-input OR gates. Figure 5-21 shows a small PLA with four inputs, six AND

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300 Chapter 5 Combinational Logic Design Practices

I1
I2

DO NOT COPYI3
I4

DO NOT COPYP1 P2 P3 P4 P5 P6
O1

DO NOT COPYO2

DO NOT COPYFigure 5-21 A 4 × 3 PLA with six product terms. O3

gates, and three OR gates and outputs. Each input is connected to a buffer that

produces both a true and a complemented version of the signal for use within the
array. Potential connections in the array are indicated by X’s; the device is

DO NOT COPYprogrammed by establishing only the connections that are actually needed. The
PLD fuses needed connections are made by fuses, which are actual fusible links or non-

volatile memory cells, depending on technology as we explain in Sections 5.3.4

and 5.3.5. Thus, each AND gate’s inputs can be any subset of the primary input
signals and their complements. Similarly, each OR gate’s inputs can be any

DO NOT COPYsubset of the AND-gate outputs.
As shown in Figure 5-22, a more compact diagram can be used to represent
PLA diagram a PLA. Moreover, the layout of this diagram more closely resembles the actual
DO NOT COPYFigure 5-22
internal layout of a PLA chip (e.g., Figure 5-28 on page 308).

I1

Compact representation I2

of a 4 × 3 PLA with sixI3
I4
DO NOT COPYproductterms.

DO NOT COPYP1 P2 P3 P4 P5 P6 O1
O2

O3

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.3 Combinational PLDs 301

I1

Figure 5-23

DO NOT COPYI2 A 4 × 3 PLA programmed

I3 with a set of three logic
equations.

I4

DO NOT COPYP1 P2 P3 P4 P5 P6
O1

DO NOTO2 COPY
O3
The PLA in Figure 5-22 can perform any three 4-input combinational logic
functions that can be written as sums of products using a total of six or fewer
distinct product terms, for example:

DO NOT COPYO1 = I1 ⋅ I2 + I1′ ⋅ I2′ ⋅ I3′ ⋅ I4′
O2 = I1 ⋅ I3′ + I1′ ⋅ I3 ⋅ I4 + I2
O3 = I1 ⋅ I2 + I1 ⋅ I3′ + I1′ ⋅ I2′ ⋅ I4′

These equations have a total of eight product terms, but the first two terms in the

DO NOT COPYO3 equation are the same as the first terms in the O1 and O2 equations. The

programmed connection pattern in Figure 5-23 matches these logic equations.
Sometimes a PLA output must be programmed to be a constant 1 or a PLA constant outputs

constant 0. That’s no problem, as shown in Figure 5-24. Product term P1 is
always 1 because its product line is connected to no inputs and is therefore

DO NOT COPYalways pulled HIGH; this constant-1 term drives the O1 output. No product term

drives the O2 output, which is therefore always 0. Another method of obtaining
a constant-0 output is shown for O3. Product term P2 is connected to each input
variable and its complement; therefore, it’s always 0 (X ⋅ X′ = 0).

DO NOT COPYI1 Figure 5-24

I2 A 4 × 3 PLA
I3 programmed to

produce constant

DO NOT COPYI4 0 and 1outputs.

DO NOT COPYP1 P2 P3 P4 P5 P6 O1 1
O2 0

O3 0

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302 Chapter 5 Combinational Logic Design Practices

AN UNLIKELY

DO NOT COPYGLITCH
Theoretically, if all of the input variables in Figure 5-24 change simultaneously,
the output of product term P2 could have a brief 0-1-0 glitch. This is highly

unlikely in typical applications, and is impossible if one input happens to be

unused and is connected to a constant logic signal.

DO NOT COPYOur example PLA has too few inputs, outputs, and AND gates (product
terms) to be very useful. An n-input PLA could conceivably use as many as 2n

product terms, to realize all possible n-variable minterms. The actual number of
product terms in typical commercial PLAs is far fewer, on the order of 4 to 16

DO NOT COPYper output, regardless of the value of n.
The Signetics 82S100 was a typical example of the PLAs that were intro-
duced in the mid-1970s. It had 16 inputs, 48 AND gates, and 8 outputs. Thus, it
had 2 × 16 × 48 = 1536 fuses in the AND array and 8 × 48 = 384 in the OR array.
Off-the-shelf PLAs like the 82S100 have since been supplanted by PALs,

DO NOT COPYCPLDs, and FPGAs, but custom PLAs are often synthesized to perform com-
plex combinational logic within a larger ASIC.

DO NOT COPYprogrammablearray
5.3.2 Programmable Array Logic Devices
A special case of a PLA, and today’s most commonly used type of PLD, is the
programmable array logic (PAL) device. Unlike a PLA, in which both the AND

logic (PAL) device and OR arrays are programmable, a PAL device has a fixed OR array.

The first PAL devices used TTL-compatible bipolar technology and were
introduced in the late 1970s. Key innovations in the first PAL devices, besides
the introduction of a catchy acronym, were the use of a fixed OR array and

DO NOT COPYbidirectional input/output pins.
PAL16L8 These ideas are well illustrated by the PAL16L8, shown in Figures 5-25 and

5-26 and one of today’s most commonly used combinational PLD structures. Its
programmable AND array has 64 rows and 32 columns, identified for program-
ming purposes by the small numbers in the figure, and 64 × 32 = 2048 fuses.

DO NOT COPYEach of the 64 AND gates in the array has 32 inputs, accommodating 16
variables and their complements; hence, the “16” in “PAL16L8”.

DO NOT COPYFRIENDSAND
PAL is a registered trademark of Advanced Micro Devices, Inc. Like other

FOES trademarks, it should be used only as an adjective. Use it as a noun or without a

trademark notice at your own peril (as I learned in a letter from AMD’s lawyers
in February 1989).

To get around AMD’s trademark, I suggest that you use a descriptive

DO NOT COPYname that is more indicative of the device’s internal structure: a fixed-OR
element (FOE).

Copyright © 1999 by John F. Wakerly Copying Prohibited

(1) Section 5.3 Combinational PLDs 303

DO NOTI1 COPY
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (19)
O1
0
1 COPY
2 (18)
IO2
3
COPY
4 (17)
IO3
5
COPY
6 (16)
(2) IO4
7
DO NOTI2 COPY
8 (15)
9 IO5

10 COPY
(14)
11
COPYIO6
12 (13)

13 COPYIO7
(12)
14 (3)
15 COPYO8
DO NOTI3 (11)
16 I10
17

18

19

20

21

(4)22
23
DO NOTI4
24

25

26

27

28

29 (5)
30
31DO NOTI5

32

33

34

35

36

37 (6)
38
39DO NOTI6

40

41

42

43

44

(7)45
46
DO NOTI747

48

49

50

51

52 (8)
53
54DO NOTI8
55

56

57

58

59

(9)60
61
DO NOTI962
63

Figure 5-25 Logic diagram of the PAL16L8.

Copyright © 1999 by John F. Wakerly Copying Prohibited

304 Chapter 5 Combinational Logic Design Practices

DO NOT COPYPAL16L8 1 I1 O1 19
DO 2 I2
DO
3 I3 IO2 18

NOT COPY4 I4 IO3 17
5 I5IO4 16
6 I6IO5 15
7 I7IO6 14

8 I8 IO7 13
9 I9 O8 12
NOT COPYFigure 5-26 11 I10
Traditional logic symbol for
the PAL16L8.
Eight AND gates are associated with each output pin of the PAL16L8.

Seven of them provide inputs to a fixed 7-input OR gate. The eighth, which we

DO NOT COPYoutput-enablegate
call the output-enable gate, is connected to the three-state enable input of the
output buffer; the buffer is enabled only when the output-enable gate has a 1 out-
put. Thus, an output of the PAL16L8 can perform only logic functions that can

be written as sums of seven or fewer product terms. Each product term can be a

function of any or all 16 inputs, but only seven such product terms are available.
Although the PAL16L8 has up to 16 inputs and up to 8 outputs, it is housed

in a dual in-line package with only 20 pins, including two for power and ground

DO NOT COPY(the corner pins, 10 and 20). This magic is the result of six bidirectional pins
(13–18) that may be used as inputs or outputs or both. This and other differences

between the PAL16L8 and a PLA structure are summarized below:
• The PAL16L8 has a fixed OR array, with seven AND gates permanently

DO NOT COPYconnected to each OR gate. AND-gate outputs cannot be shared; if a prod-
uct term is needed by two OR gates, it must be generated twice.
NOT COPY• Each output of the PAL16L8 has an individual three-state output enable
DO signal, controlled by a dedicated AND gate (the output-enable gate). Thus,
outputs may be programmed as always enabled, always disabled, or
enabled by a product term involving the device inputs.

HOW USEFUL
ARE SEVEN

DO NOT COPYPRODUCT
The worst-case logic function for two-level AND-OR design is an n-input XOR
(parity) function, which requires 2n−1 product terms. However, less perverse

functions with more than seven product terms of a PAL16L8 can often be built

TERMS? by decomposing them into a 4-level structure (AND-OR-AND-OR) that can be

realized with two passes through the AND-OR array. Unfortunately, besides
using up PLD outputs for the first-pass terms, this doubles the delay, since a

DO NOT COPYfirst-pass input must pass through the PLD twice to propagate to the output.

Copyright © 1999 by John F. Wakerly Copying Prohibited

DOCOMBINATIONAL, Section 5.3 Combinational PLDs 305
NOT
COMBINATORIAL! NOT COPYA step backwards in MMI’s introduction of PAL devices was their popular-

DO ization of the word “combinatorial” to describe combinational circuits.
Combinational circuits have no memory—their output at any time depends

NOT COPYon the current input combination. For well-rounded computer engineers, the

word “combinatorial” should conjure up vivid images of binomial
coefficients, problem-solving complexity, and computer-science-great
Donald Knuth.

• There is an inverter between the output of each OR gate and the external

DO NOT COPYpinofthedevice.

• Six of the output pins, called I/O pins, may also be used as inputs. This I/O pin
provides many possibilities for using each I/O pin, depending on how the
device is programmed:

– If an I/O pin’s output-control gate produces a constant 0, then the

DO NOT COPYoutput is always disabled and the pin is used strictly as an input.
– If the input signal on an I/O pin is not used by any gates in the AND
array, then the pin may be used strictly as an output. Depending on
the programming of the output-enable gate, the output may always be

DO NOT COPYenabled, or it may be enabled only for certain input conditions.
– If an I/O pin’s output-control gate produces a constant 1, then the
output is always enabled, but the pin may still be used as an input too.
In this way, outputs can be used to generate first-pass “helper terms”
for logic functions that cannot be performed in a single pass with the

DO NOT COPYlimited number of AND terms available for a single output. We’ll
show an example of this case on page 325.

– In another case with an I/O pin always output-enabled, the output
may be used as an input to AND gates that affect the very same

DO NOT COPYoutput. That is, we can embed a feedback sequential circuit in a
PAL16L8. We’ll discuss this case in \secref{palatch}.
The PAL20L8 is another combinational PLD similar to the PAL16L8,PAL16L8
except that its package has four more input-only pins and each of its AND gates
has eight more inputs to accommodate them. Its output structure is the same as

DO NOT COPYthePAL16L8’s.
5.3.3 Generic Array Logic Devices
In \chapref{SeqPLDs} we’ll introduce sequential PLDs, programmable logic
devices that provide flip-flops at some or all OR-gate outputs. These devices can

DO NOT COPYbe programmed to perform a variety of useful sequential-circuit functions.

Copyright © 1999 by John F. Wakerly Copying Prohibited

306 Chapter 5 Combinational Logic Design Practices

DOCOMBINATIONAL NOT COPYThe speed of a combinational PLD is usually stated as a single number giving
PLD SPEED the propagation delay tPD from any input to any output for either direction of
transition. PLDs are available in a variety of speed grades; commonly used
DO
NOT COPYparts run at 10 ns. In 1998, the fastest available combinational PLDs included
a bipolar PAL16L8 at 5 ns and a 3.3-V CMOS GAL22LV10 at 3.5 ns.
generic array logic One type of sequential PLD, first introduced by Lattice Semiconductor, is

GAL device

DO NOT COPYGAL16V8
called generic array logic or a GAL device, and is particularly popular. A single
GAL device type, the GAL16V8, can be configured (via programming and a
corresponding fuse pattern) to emulate the AND-OR, flip-flop, and output

structure of any of a variety of combinational and sequential PAL devices,

including the PAL16L8 introduced previously. What’s more, the GAL device
can be erased electrically and reprogrammed.

Figure 5-27 shows the logic diagram for a GAL16V8 when it has been

DO NOT COPYconfigured as a strictly combinational device similar to the PAL16L8. This
configuration is achieved by programming two “architecture-control” fuses, not

shown. In this configuration, the device is called a GAL16V8C.
The most important thing to note about the GAL16V8C logic diagram,

compared to that of a PAL16L8 on page 303, is that an XOR gate has been
inserted between each OR output and the three-state output driver. One input of
DO NOT COPYGAL16V8C
the XOR gate is “pulled up” to a logic 1 value but connected to ground (0) via a

fuse. If this fuse is intact, the XOR gate simply passes the OR-gate’s output
unchanged, but if the fuse is blown the XOR gate inverts the OR-gate’s output.
This fuse is said to control the output polarity of the corresponding output pin.

Output-polarity control is a very important feature of modern PLDs,
DO NOT COPYoutputpolarity
including the GAL16V8. As we discussed in Section 4.6.2, given a logic

function to minimize, an ABEL compiler finds minimal sum-of-products
expressions for both the function and its complement. If the complement yields

DO NOT COPYfewer product terms, it can be used if the GAL16V8’s output polarity fuse is set
to invert. Unless overridden, the compiler automatically makes the best selection
and sets up the fuse patterns appropriately.
PALCE16V8

DO NOT COPYGAL20V8
Several companies make a part that is equivalent to the GAL16V8, called
the PALCE16V8. There is also a 24-pin GAL device, the GAL20V8 or
PALCE20V8, that can be configured to emulate the structure of the PAL20L8 or

PALCE20V8 any of a variety of sequential PLDs, as described in \secref{seqGAL}.

DO NOT COPYLEGAL NOTICE GAL is a trademark of Lattice Semiconductor, Hillsboro, OR 97124.

Copyright © 1999 by John F. Wakerly Copying Prohibited

(1) Section 5.3 Combinational PLDs 307

DO NOTI1 COPY
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 (19)
O1
0
1 COPY
2 (18)
IO2
3
COPY
4 (17)
IO3
5
COPY
6 (16)
(2) IO4
7
DO NOTI2 COPY
8 (15)
9
COPYIO5
10 (14)

11 COPYIO6
(13)
12
COPYIO7
13 COPY(12)

14 (3) O8
15
DO NOTI3 (11)
16 I10
17

18

19

20

21

(4)22
23
DO NOTI4
24

25

26

27

28

29 (5)
30
31DO NOTI5

32

33

34

35

36

37 (6)
38
39DO NOTI6

40

41

42

43

44

(7)45
46
DO NOTI747

48

49

50

51

52 (8)
53
54DO NOTI8
55

56

57

58

59

(9)60
61
DO NOTI962
63

Figure 5-27 Logic diagram of the GAL16V8C.

Copyright © 1999 by John F. Wakerly Copying Prohibited

308 Chapter 5 Combinational Logic Design Practices

DO I1NOTVCC COPY I1
I1′
DO
I2I3 I3 I2
DOFigure 5-28 I2′
NOT COPYI3′
A 4 × 3 PLA built using I4 I4
TTL-like open-collector I4′

DOgates and diode logic. P1′ P2′ P3′ P4′ P5′ P6′ O1

NOT COPYVCC
O2

NOT COO3 PY
*5.3.4 Bipolar PLD Circuits

There are several different circuit technologies for building and physically
programming a PLD. Early commercial PLAs and PAL devices used bipolar

DO NOT COPYcircuits. For example, Figure 5-28 shows how the example 4 × 3 PLA circuit of
the preceding section might be built in a bipolar, TTL-like technology. Each

potential connection is made by a diode in series with a metal link that may be
present or absent. If the link is present, then the diode connects its input into a
diode-AND function. If the link is missing, then the corresponding input has no

DO NOT COPYeffect on that AND function.
A diode-AND function is performed because each and every horizontal

“input” line that is connected via a diode to a particular vertical “AND” line must
be HIGH in order for that AND line to be HIGH. If an input line is LOW, it pulls
LOW all of the AND lines to which it is connected. This first matrix of circuit
elements that perform the AND function is called the AND plane.
DO NOT COPYANDplane
Each AND line is followed by an inverting buffer, so overall a NAND

function is obtained. The outputs of the first-level NAND functions are combined
by another set of programmable diode AND functions, once again followed by

DO NOT COPYinverters. The result is a two-level NAND-NAND structure that is functionally
equivalent to the AND-OR PLA structure described in the preceding section. The
matrix of circuit elements that perform the OR function (or the second NAND

OR plane

DO NOT COPYfusiblelink
function, depending on how you look at it) is called the OR plane.
A bipolar PLD chip is manufactured with all of its diodes present, but with

a tiny fusible link in series with each one (the little squiggles in Figure 5-28). By

* Throughout this book, optional sections are marked with an asterisk.

Copyright © 1999 by John F. Wakerly Copying Prohibited

DOVCC NOT Section 5.3 Combinational PLDs 309
I1 /I1′
/I1 COPY
DOI2 COPY
I3 NOT/I2′ COPY
/I2
I4 Figure 5-29
/I3′
/I3 COPYA 4 × 3 PLA built
/I4′ using CMOS logic.
/I4

P1 P2 P3 P4 P5 P6O1

DO NOTVCC
O2

DO NOTO3

applying special input patterns to the device, it is possible to select individual
links, apply a high voltage (10–30 V), and thereby vaporize selected links.

DO NOT COPYEarly bipolar PLDs had reliability problems. Sometimes the stored

patterns changed because of incompletely vaporized links that would “grow
back,” and sometimes intermittent failures occurred because of floating shrapnel
inside the IC package. However, these problems have been largely worked out,

DO NOT COPYand reliable fusible-link technology is used in today’s bipolar PLDs.

*5.3.5 CMOS PLD Circuits

Although they’re still available, bipolar PLDs have been largely supplanted by
CMOS PLDs with a number of advantages, including reduced power consump-
tion and reprogrammability. Figure 5-29 shows a CMOS design for the 4 × 3

DO NOT COPYPLA circuit of Section 5.3.1.
Instead of a diode, an n-channel transistor with a programmable connec-
tion is placed at each intersection between an input line and a word line. If the
input is LOW, then the transistor is “off,” but if the input is HIGH, then the tran-
sistor is “on,” which pulls the AND line LOW. Overall, an inverted-input AND

DO NOT COPY(i.e., NOR) function is obtained. This is similar in structure and function to a

normal CMOS k-input NOR gate, except that the usual series connection of k
p-channel pull-up transistors has been replaced with a passive pull-up resistor
(in practice, the pull-up is a single p-channel transistor with a constant bias).

As shown in color on Figure 5-29, the effects of using an inverted-input

DO NOT COPYAND gate are canceled by using the opposite (complemented) input lines for

each input, compared with Figure 5-28. Also notice that the connection between

Copyright © 1999 by John F. Wakerly Copying Prohibited

310 Chapter 5 Combinational Logic Design Practices COPYVCC

DO NOT

DO NOT COPYfloatinggate
nonfloating gate
active-low

input lines

DO NOT COPYFigure 5-30
AND plane of an

EPLD using floating-

DO NOT COPYgate MOStransistors.
active-high AND lines

the AND plane and the OR plane is noninverting, so the AND plane performs a

true AND function.
The outputs of the first-level AND functions are combined in the OR plane

by another set of NOR functions with programmable connections. The output of

DO NOT COPYeach NOR function is followed by an inverter, so a true OR function is realized,
and overall the PLA performs an AND-OR function as desired.
In CMOS PLD technologies, the programmable links shown in

Figure 5-29 are not normally fuses. In non-field-programmable devices, such as
custom VLSI chips, the presence or absence of each link is simply established as

DO NOT COPYpart of the metal mask pattern for the manufacture of the device. By far the most
common programming technology, however, is used in CMOS EPLDs, as

discussed next.
An erasable programmable logic device (EPLD) can be programmed with

any desired link configuration, as well as “erased” to its original state, either
electronically or by exposing it to ultraviolet light. No, erasing does not cause
erasable programmable

DO NOT COPYlogicdevice(EPLD)
links to suddenly appear or disappear! Rather, EPLDs use a different technology,

floating-gate MOS

DO NOT COPYtransistor
called “floating-gate MOS.”
As shown in Figure 5-30, an EPLD uses floating-gate MOS transistors.

Such a transistor has two gates. The “floating” gate is unconnected and is

surrounded by extremely high-impedance insulating material. In the original,

manufactured state, the floating gate has no charge on it and has no effect on
circuit operation. In this state, all transistors are effectively “connected”; that is,
there is a logical link present at every crosspoint in the AND and OR planes.

DO NOT COPYTo program an EPLD, the programmer applies a high voltage to the non-
floating gate at each location where a logical link is not wanted. This causes a

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.3 Combinational PLDs 311

temporary breakdown in the insulating material and allows a negative charge to
accumulate on the floating gate. When the high voltage is removed, the negative

DO NOT COPYcharge remains on the floating gate. During subsequent operations, the negative

charge prevents the transistor from turning “on” when a HIGH signal is applied
to the nonfloating gate; the transistor is effectively disconnected from the circuit.
EPLD manufacturers claim that a properly programmed bit will retain 70%

of its charge for at least 10 years, even if the part is stored at 125°C, so for most

DO NOT COPYapplications the programming can be considered to be permanent. However,
EPLDs can also be erased.

Although some early EPLDs were packaged with a transparent lid and
used light for erasing, today’s devices are popular are electrically erasable
PLDs. The floating gates in an electrically erasable PLD are surrounded by an

DO NOT COPYextremely thin insulating layer, and can be erased by applying a voltage of the
electrically erasable
PLD

opposite polarity as the charging voltage to the nonfloating gate. Thus, the same

piece of equipment that is normally used to program a PLD can also be used to
erase an EPLD before programming it.

DO NOT COPYLarger-scale, “complex” PLDs (CPLDs), also use floating-gate program-

ming technology. Even larger devices, often called field-programmable gate field-programmable
arrays (FPGAs), use read/write memory cells to control the state of each gate array (FPGA)
connection. The read/write memory cells are volatile—they do not retain their
state when power is removed. Therefore, when power is first applied to the

DO NOT COPYFPGA, all of its read/write memory must be initialized to a state specified by a

separate, external nonvolatile memory. This memory is typically either a
programmable read-only memory (PROM) chip attached directly to the FPGA
or it’s part of a microprocessor subsystem that initializes the FPGA as part of

DO NOT COPYoverall system initialization.

*5.3.6 Device Programming and Testing
A special piece of equipment is used to vaporize fuses, charge up floating-gate
transistors, or do whatever else is required to program a PLD. This piece of
equipment, found nowadays in almost all digital design labs and production

DO NOT COPYfacilities, is called a PLD programmer or a PROM programmer. (It can be used
PLD programmer
PROM programmer

CHANGING

DO NOT COPYHARDWARE
PROMs are normally used to supply the connection pattern for a read/write-
memory-based FPGA, but there are also applications where the pattern is

ON THE FLY actually read from a floppy disk. You just received a floppy with a new software

version? Guess what, you just got a new hardware version too!
This concept leads us to the intriguing idea, already being applied in some

applications, of “reconfigurable hardware,” where a hardware subsystem is

DO NOT COPYredefined, on the fly, to optimize its performance for the particular task at hand.

Copyright © 1999 by John F. Wakerly Copying Prohibited

312 Chapter 5 Combinational Logic Design Practices

with programmable read-only memories, “PROMs,” as well as for PLDs.) A
typical PLD programmer includes a socket or sockets that physically accept the

DO NOT COPYdevices to be programmed, and a way to “download” desired programming
patterns into the programmer, typically by connecting the programmer to a PC.
PLD programmers typically place a PLD into a special mode of operation
in order to program it. For example, a PLD programmer typically programs the
PLDs described in this chapter eight fuses at a time as follows:

DO NOT COPY1. Raise a certain pin to a predetermined, high voltage (such as 14 V) to put
the device into programming mode.

2. Select a group of eight fuses by applying a binary “address” to certain
inputs of the device. (For example, the 82S100 has 1920 fuses, and would

DO NOT COPYtherefore require 8 inputs to select one of 240 groups of 8 fuses.)
3. Apply an 8-bit value to the outputs of the device to specify the desired
DO programming for each fuse (the outputs are used as inputs in programming
mode).

NOT COPY4. Raise a second predetermined pin to the high voltage for a predetermined
length of time (such as 100 microseconds) to program the eight fuses.
5. Lower the second predetermined pin to a low voltage (such as 0 V) to read
out and verify the programming of the eight fuses.

DO NOT COPY6. Repeat steps 1–5 for each group of eight fuses.
in-system Many PLDs, especially larger CPLDs, feature in-system programmability.

programmability

DO NOT COPYJTAGport
This means that the device can be programmed after it is already soldered into
the system. In this case, the fuse patterns are applied to the device serially using
four extra signals and pins, called the JTAG port, defined by IEEE standard
1149.1. These signals are defined so that multiple devices on the same printed-

circuit board can be “daisy chained” and selected and programmed during the

board manufacturing process using just one JTAG port on a special connector.
No special high-voltage power supply is needed; each device uses a charge-
pump circuit internally to generate the high voltage needed for programming.

DO NOT COPYAs noted in step 5 above, fuse patterns are verified as they are programmed
into a device. If a fuse fails to program properly the first time, the operation can

be retried; if it fails to program properly after a few tries, the device is discarded
(often with great prejudice and malice aforethought).

DO NOT COPYWhile verifying the fuse pattern of a programmed device proves that its
fuses are programmed properly, it does not prove that the device will perform the
logic function specified by those fuses. This is true because the device may have
unrelated internal defects such as missing connections between the fuses and
elements of the AND-OR array.

DO NOT COPYThe only way to test for all defects is to put the device into its normal oper-
ational mode, apply a set of normal logic inputs, and observe the outputs. The

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 313

required input and output patterns, called test vectors, can be specified by the
designer as we showed in Section 4.6.7,or can be generated automatically by a

DO NOT COPYspecial test-vector-generation program. Regardless of how the test vectors are

generated, most PLD programmers have the ability to apply test-vector inputs to
a PLD and to check its outputs against the expected results.
Most PLDs have a security fuse which, when programmed, disables the security fuse

ability to read fuse patterns from the device. Manufacturers can program this

DO NOT COPYfuse to prevent others from reading out the PLD fuse patterns in order to copy the
product design. Even if the security fuse is programmed, test vectors still work,

so the PLD can still be checked.

DO NOT COPY5.4 Decoders
A decoder is a multiple-input, multiple-output logic circuit that converts coded decoder

inputs into coded outputs, where the input and output codes are different. The
input code generally has fewer bits than the output code, and there is a one-to-
one mapping from input code words into output code words. In a one-to-one

DO NOT COPYmapping, each input code word produces a different output code word.
one-to-one mapping

The general structure of a decoder circuit is shown in Figure 5-31. The

enable inputs, if present, must be asserted for the decoder to perform its normal

mapping function. Otherwise, the decoder maps all input code words into a

DO NOT COPYsingle, “disabled,” output code word.
The most commonly used input code is an n-bit binary code, where an n-bit
word represents one of 2n different coded values, normally the integers from 0
through 2n−1. Sometimes an n-bit binary code is truncated to represent fewer
than 2n values. For example, in the BCD code, the 4-bit combinations 0000

DO NOT COPYthrough 1001 represent the decimal digits 0–9, and combinations 1010 through

1111 are not used.
The most commonly used output code is a 1-out-of-m code, which contains
m bits, where one bit is asserted at any time. Thus, in a 1-out-of-4 code with
active-high outputs, the code words are 0001, 0010, 0100, and 1000. With

DO NOT COPYactive-low outputs, the code words are 1110, 1101, 1011, and 0111.

DO NOT COPYDecoder
Figure 5-31

input map Decoder circuit structure.
code word

enable output
code word
DO NOT COPYinputs

Copyright © 1999 by John F. Wakerly Copying Prohibited

314 Chapter 5 Combinational Logic Design Practices

DO Ta ble 5 -4
DO Truth table for a 2-to-4

NOT COPYbinary decoder.
Inputs Outputs
EN I1 I0 Y3 Y2 Y1 Y0

0xx 0000

0001
0010
0100
1000
NOT COPY1 0 0
101
110
111

DO NOT COPYbinarydecoder
5.4.1 Binary Decoders

The most common decoder circuit is an n-to-2n decoder or binary decoder. Such
a decoder has an n-bit binary input code and a 1-out-of-2n output code. A binary

decoder is used when you need to activate exactly one of 2n outputs based on an

n-bit input value.
For example, Figure 5-32(a) shows the inputs and outputs and Table 5-4 is

the truth table of a 2-to-4 decoder. The input code word 1,I0 represents an integer

DO NOT COPYin the range 0–3. The output code word Y3,Y2,Y1,Y0 has Yi equal to 1 if and only
enable input if the input code word is the binary representation of i and the enable input EN is

DO NOT COPYdecode
1. If EN is 0, then all of the outputs are 0. A gate-level circuit for the 2-to-4
decoder is shown in Figure 5-32(b). Each AND gate decodes one combination of
the input code word I1,I0.

The binary decoder’s truth table introduces a “don’t-care” notation for

input combinations. If one or more input values do not affect the output values
for some combination of the remaining inputs, they are marked with an “x” for
that input combination. This convention can greatly reduce the number of rows

DO NOT COPYin the truth table, as well as make the functions of the inputs more clear.
The input code of an n-bit binary decoder need not represent the integers

from 0 through 2n−1. For example, Table 5-5 shows the 3-bit Gray-code output

I0′ I0 I1′ I1 EN
I0

Y0
DO NOT COPYFigure 5-32

A 2-to-4 decoder:

(a) inputs and outputs;2-to-4 Y1
decoder
DO NOT COPY(b)logicdiagram.I1

I0 Y0

I1 Y1 Y2

Y2Y3

DO NOT COPYEN Y3 EN

(a) (b)

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 315

Disk Position I2 I0 Binary Decoder Output

DO0° 0 NOT COPY0 Y0
I1 Table 5-5
0 Position encoding for
a 3-bit mechanical

45° 0 0 1 Y1 encoding disk.

90° 0 1 1 Y3

135° 0 1 0 Y2
180° 1 1 0 Y6
Y7
DO NOT COPY225° 1 1 1
270° 1 0 1 Y5

315° 1 0 0 Y4
DO NOT COPYof a mechanical encoding disk with eight positions. The eight disk positions can
be decoded with a 3-bit binary decoder with the appropriate assignment of

signals to the decoder outputs, as shown in Figure 5-33.

Also, it is not necessary to use all of the outputs of a decoder, or even to
decode all possible input combinations. For example, a decimal or BCD decoder decimal decoder

DO NOT COPYdecodes only the first ten binary input combinations 0000–1001 to produce BCD decoder

outputs Y0–Y9.

5.4.2 Logic Symbols for Larger-Scale Elements

Before describing some commercially available 74-series MSI decoders, we

DO NOT COPYneed to discuss general guidelines for drawing logic symbols for larger-scale

logic elements.
The most basic rule is that logic symbols are drawn with inputs on the left

and outputs on the right. The top and bottom edges of a logic symbol are not
normally used for signal connections. However, explicit power and ground

DO NOT COPYconnections are sometimes shown at the top and bottom, especially if these

connections are made on “nonstandard” pins. (Most MSI parts have power and
ground connected to the corner pins, e.g., pins 8 and 16 of a 16-pin DIP

DO NOT COPYpackage.)
3-to-8

decoder Figure 5-33
Using a 3-to-8 binary
Y0 decoder to decode a
Y1 Gray code.
DO NOT COPYSHAFTI0I0 Y2 DEG0
DEG45
DEG135

SHAFTI1 I1 Y3 DEG90

SHAFTI2I2 Y4 DEG315
EN Y5 DEG270
DO NOT COPYENABLE DEG180
Y6 DEG225
Y7

Copyright © 1999 by John F. Wakerly Copying Prohibited

316 Chapter 5 Combinational Logic Design Practices

LOGIC FAMILIES Most logic gates and larger-scale elements are available in a variety of CMOS and

DO NOT COPYfamilies, many of which we described in Sections 3.8 and 3.11. For example, the
74LS139, 74S139, 74ALS139, 74AS139, 74F139, 74HC139, 74HCT139,
74ACT139, 74AC139, 74FCT139 74AHC139, 74AHCT139, 74LC139,
74LVC139, and 74VHC139 are all dual 2-to-4 decoders with the same logic
function, but in electrically different TTL and CMOS families and sometimes in

DO NOT COPYdifferent packages. In addition, “macro” logic elements with the same pin names and
functions as the ’139 and other popular 74-series devices are available as building
blocks in most FPGA and ASIC design environments.

Throughout this text, we use “74x” as a generic prefix. And we’ll sometimes
omit the prefix and write, for example, ’139. In a real schematic diagram for a circuit

DO NOT COPYthat you are going to build or simulate, you should include the full part number, since
timing, loading, and packaging characteristics depend on the family.

DO NOT COPYLike gate symbols, the logic symbols for larger-scale elements associate an
active level with each pin. With respect to active levels, it’s important to use a
consistent convention to naming the internal signals and external pins.
Larger-scale elements almost always have their signal names defined in

terms of the functions performed inside their symbolic outline, as explained in

DO NOT COPYSection 5.1.4. For example, Figure 5-34(a) shows the logic symbol for one
section of a 74x139 dual 2-to-4 decoder, an MSI part that we’ll fully describe in
the next subsection. When the G input is asserted, one of the outputs Y0–Y3 is
asserted, as selected by a 2-bit code applied to the A and B inputs. It is apparent
from the symbol that the G input pin and all of the output pins are active low.

DO NOT COPYWhen the 74x139 symbol appears in the logic diagram for a real applica-
tion, its inputs and outputs have signals connected to other devices, and each

such signal has a name that indicates its function in the application. However,
when we describe the 74x139 in isolation, we might still like to have a name for
the signal on each external pin. Figure 5-34(b) shows our naming convention in

DO NOT COPYthis case. Active-high pins are given the same name as the internal signal, while
active-low pins have the internal signal name followed by the suffix “_L”.

Figure 5-34 NOT COPY1/274x139
G Y0
DOLogic symbol for one-half 1/2 74x139
G_L G Y0 Y0_L
of a 74x139 dual 2-to-4
decoder: (a) conventional Y1 Y1 Y1_L
symbol; (b) default signal
names associated with A A Y2 Y2_L
B B Y3 Y3_L
DOexternal pins. NOT COPYA Y2
B Y3
(a) (b)

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 317

IEEE STANDARD Throughout this book, we use “traditional” symbols for larger-scale logic elements.

DO NOT COPYLOGIC SYMBOLS The IEEE standard uses somewhat different symbols for larger-scale logic elements.
IEEE standard symbols, as well as the pros and cons of IEEE versus traditional

symbols, are discussed in Appendix A.

DO NOT COPY5.4.3 The 74x139 Dual 2-to-4 Decoder
Two independent and identical 2-to-4 decoders are contained in a single MSI

part, the 74x139. The gate-level circuit diagram for this IC is shown in 74x139
Figure 5-35(a). Notice that the outputs and the enable input of the ’139 are
active-low. Most MSI decoders were originally designed with active-low

DO NOT COPYoutputs, since TTL inverting gates are generally faster than noninverting ones.
Also notice that the ’139 has extra inverters on its select inputs. Without these

inverters, each select input would present three AC or DC loads instead of one,

DO NOT COPYconsuming much more of the fanout budget of the device that drives it.

Figure 5-35 The 74x139 dual 2-to-4 decoder: (a) logic diagram, including pin
numbers for a standard 16-pin dual in-line package;
(4)

DO NOT COPY1Y0_L
(b) traditional logic symbol; (c) logic symbol for one decoder.

74x139

(1) 1 1G 1Y0 4

1G_L NOT COPY(5) 2 1A 1Y1 5
1Y1_L3 1B 1Y2 6
DO (6) 1Y3 7
(2)
1A 1Y2_L 15 2G 2Y0 12
(3)
2Y1 11
DO1B 2Y2 10
2Y3 9
(a) NOT COPY(7) 14 2A
1Y3_L13 2B
(15)
(12) (b)
DO2G_L 2Y0_L
NOT COPY(11)
2Y1_L
1/2 74x139

G Y0

(10) Y1

2Y2_L

(9)
(14) A Y2
B Y3
DO NOT COPY2A
(13) 2Y3_L (c)

2B

Copyright © 1999 by John F. Wakerly Copying Prohibited

318 Chapter 5 Combinational Logic Design Practices

Table 5-6
Truth table for one-

DO NOT COPYhalfofa 74x139dual
Inputs Outputs
G_L B A Y3_L Y2_L Y1_L Y0_L

2-to-4 decoder. 1xx 1111

1110
1101
1011
0111
DO NOT COPY0 0 0
001
010
011

A logic symbol for the 74x139 is shown in Figure 5-35(b). Notice that all
of the signal names inside the symbol outline are active-high (no “_L”), and that

DO NOT COPYinversion bubbles indicate active-low inputs and outputs. Often a schematic may
use a generic symbol for just one decoder, one-half of a ’139, as shown in (c). In

this case, the assignment of the generic function to one half or the other of a
particular ’139 package can be deferred until the schematic is completed.

Table 5-6 is the truth table for a 74x139-type decoder. The truth tables in

DO NOT COPYsome manufacturers’ data books use L and H to denote the input and output
signal voltage levels, so there can be no ambiguity about the electrical function

of the device; a truth table written this way is sometimes called a function table.
However, since we use positive logic throughout this book, we can use 0 and 1
without ambiguity. In any case, the truth table gives the logic function in terms of
the external pins of the device. A truth table for the function performed inside
DO NOT COPYfunctiontable
the symbol outline would look just like Table 5-4, except that the input signal

names would be G, B, A.
Some logic designers draw the symbol for 74x139s and other logic func-

DO NOT COPYtions without inversion bubbles. Instead, they use an overbar on signal names
inside the symbol outline to indicate negation, as shown in Figure 5-36(a). This
notation is self-consistent, but it is inconsistent with our drawing standards for
bubble-to-bubble logic design. The symbol shown in (b) is absolutely incorrect:
according to this symbol, a logic 1, not 0, must be applied to the enable pin to

DO NOT COPYenablethedecoder.

DOFigure 5-36 NOT COPY1/274x139
G Y0
More ways to 1/2 74x139
symbolize a 74x139: G Y0
(a) correct but to be
avoided; (b) incorrect (a) Y1 (b) Y1
because of double
NOT COPYA Y2 A Y2
DOnegations. B Y3 B Y3

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 319

BAD NAMES Some manufacturers’ data sheets have inconsistencies similar to Figure 5-36(b). For

DO NOT COPYexample, Texas Instruments’ data sheet for the 74AHC139 uses active low-names
like 1G for the enable inputs, with the overbar indicating an active-low pin, but
active-high names like 1Y0 for all the active-low output pins. On the other hand,
Motorola’s data sheet for the 74VHC139 correctly uses overbars on the names for
both the enable inputs and the outputs, but the overbars are barely visible in the

DO NOT COPYdevice’s function table due to a typographical problem.
I’ve also had the personal experience of building a printed-circuit board with
many copies of a new device from a vendor whose documentation clearly indicated
that a particular input was active low, only to find out upon the first power-on that
the input was active high.

DO NOT COPYThe moral of the story is that you have to study the description of each device
to know what’s really going on. And if it’s a brand-new device, whether from a com-
mercial vendor or your own company’s ASIC group, you should double-check all of
the signal polarities and pin assignments before committing to a PCB. Be assured,

DO NOT COPYhowever, that the signal names in this text are consistent and correct.

5.4.4 The 74x138 3-to-8 Decoder 74x138
The 74x138 is a commercially available MSI 3-to-8 decoder whose gate-level
circuit diagram and symbol are shown in Figure 5-37; its truth table is given in

DO NOT COPYTable 5-7. Like the 74x139, the 74x138 has active-low outputs, and it has three
enable inputs (G1, /G2A, /G2B), all of which must be asserted for the selected

output to be asserted.
The logic function of the ’138 is straightforward—an output is asserted if

DO NOT COPYand only if the decoder is enabled and the output is selected. Thus, we can easily

write logic equations for an internal output signal such as Y5 in terms of the
internal input signals:
DO NOT COPYenable
Y5 = G1 ⋅ G2A ⋅ G2B ⋅ C ⋅ B′ ⋅ A













select

However, because of the inversion bubbles, we have the following relations

between internal and external signals:
G2A = G2A_L′

DO NOT COPYG2B = G2B_L′
Y5 = Y5_L′

Therefore, if we’re interested, we can write the following equation for the exter-
nal output signal Y5_L in terms of external input signals:

DO NOT COPYY5_L = Y5′ = (G1 ⋅ G2A_L′ ⋅ G2B_L′ ⋅ C ⋅ B′ ⋅ A)′
= G1′ + G2A_L + G2B_L + C′ + B + A′

Copyright © 1999 by John F. Wakerly Copying Prohibited

320 Chapter 5 Combinational Logic Design Practices

Ta b l e 5 - 7 Truth table for a 74x138 3-to-8 decoder.

DO NOT COPYInputs
Outputs

G1 G2A_L G2B_L C B A Y7_L Y6_L Y5_L Y4_L Y3_L Y2_L Y1_L Y0_L

0x

DO NOT COPYx 1
x xxx 11111111
x xxx 11111111

xx 1 xxx 11111111

0 000 11111110
0 001 11111101
0 010 11111011
10
10

DO NOT COPY1 0
10 0 011 11110111

10
10

DO NOT COPY1 0
0 100 11101111
0 101 11011111
0 110 10111111

10 0 111 01111111

On the surface, this equation doesn’t resemble what you might expect for a

DO NOT COPYdecoder, since it is a logical sum rather than a product. However, if you practice
bubble-to-bubble logic design, you don’t have to worry about this; you just give
the output signal an active-low name and remember that it’s active low when you
connect it to other inputs.

DO NOT COPY5.4.5 Cascading Binary Decoders
Multiple binary decoders can be used to decode larger code words. Figure 5-38
shows how two 3-to-8 decoders can be combined to make a 4-to-16 decoder. The
availability of both active-high and active-low enable inputs on the 74x138
makes it possible to enable one or the other directly based on the state of the

DO NOT COPYmost significant input bit. The top decoder (U1) is enabled when N3 is 0, and the
bottom one (U2) is enabled when N3 is 1.
To handle even larger code words, binary decoders can be cascaded hierar-
chically. Figure 5-39 shows how to use half of a 74x139 to decode the two high-

DO NOT COPYorder bits of a 5-bit code word, thereby enabling one of four 74x138s that decode
the three low-order bits.

5.4.6 Decoders in ABEL and PLDs
Nothing in logic design is much easier than writing the PLD equations for a

DO NOT COPYdecoder. Since the logic expression for each output is typically just a single prod-
uct term, decoders are very easily targeted to PLDs and use few product-term
resources.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 321

DO(a) NOT (15) (b) 74x138
NOT
(6) NOT Y0_L 6 G1 Y0 15
NOT 4 G2A Y1 14
G1 NOT COPY(14) 5 G2B Y2 13
Y1_L Y3 12
(4) (13) 1A Y4 11
Y2_L 2B Y5 10
DOG2A_L 3C Y6 9
(5) COPY(12) Y7 7

G2B_L Y3_L

DO COPY(11)
Y4_L
(1) Figure 5-37
(10) The 74x138 3-to-8
A COPYY5_L
(9)
DO(2) Y6_L
B decoder: (a) logic
diagram, including pin
(3) numbers for a
standard 16-pin dual
DOC
in-line package;

(b) traditional logic
symbol.
COPY(7)
Y7_L
NOT COPY+5V 74x138
DO R Y0 15 DEC0_L Figure 5-38
DO 6 G1 Y1 14 DEC1_L Design of a 4-to-16
Y2 13 DEC2_L decoder using
4 G2A Y3 12 DEC3_L 74x138s.
5 G2B

N0 1A Y4 11 DEC4_L
N1 2B Y5 10 DEC5_L
N2 3C Y6 9 DEC6_L
Y7 7 DEC7_L
NOT COPYN3
EN_L U1

DO NOT COPY74x138
DO 6 G1 Y0 15 DEC8_L
4 G2A Y1 14 DEC9_L
5 G2B Y2 13 DEC10_L
Y3 12 DEC11_L

Y4 11 DEC12_L
Y5 10 DEC13_L
Y6 9 DEC14_L
Y7 7 DEC15_L
NOT COPY1 A
2B
3C
U2

Copyright © 1999 by John F. Wakerly Copying Prohibited

322 Chapter 5 Combinational Logic Design Practices

DO NOT 6 G174x138
DON0 NOT
COPY4 G2A Y0 15 DEC0_L
N1 5 G2B Y1 14 DEC1_L
N2 Y2 13 DEC2_L
1A Y3 12 DEC3_L
2B Y4 11 DEC4_L
Y5 10 DEC5_L
COPY3 C Y6 9 DEC6_L
Y7 7 DEC7_L

DO NOT COPY6 G1 U2
4 G2A74x138
5 G2B
DO NOT1/274x139 Y0 15 DEC8_L
EN3_L 1 1G 1Y0 4 EN0X7_L 1A Y1 14 DEC9_L
2BY2 13 DEC10_L
Y3 12 DEC11_L
COPY3 C Y4 11 DEC12_L
Y5 10 DEC13_L
1Y1 5 EN8X15_L Y6 9 DEC14_L
1Y2 6 EN16X23_L Y7 7 DEC15_L
1Y3 7 EN24X31_L
DON3 NOT2 1A COPY6 G1 U3
N4 4 G2A74x138
3 1B 5 G2B
U1 Y0 15 DEC16_L
1A Y1 14 DEC17_L
DO NOT Y2 13 DEC18_L
EN1 COPY2 B Y3 12 DEC19_L
EN2_L 3C Y4 11 DEC20_L
Y5 10 DEC21_L
DO NOT Y6 9 DEC22_L
Y7 7 DEC23_L
U4

COPY74x138
6 G1Y0 15 DEC24_L
DO NOT 4 G2A Y1 14 DEC25_L
DO NOT 5 G2B Y2 13 DEC26_L
Y3 12 DEC27_L
COPY1 A Y4 11 DEC28_L
2B Y5 10 DEC29_L
Y6 9 DEC30_L
COPY3 C Y7 7 DEC31_L

U5

Figure 5-39 Design of a 5-to-32 decoder using 74x138s and a 74x139.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 323

Ta b l e 5 - 8 An ABEL program for a 74x138-like 3-to-8 binary decoder.
module Z74X138

DO NOT COPYtitle '74x138 Decoder PLD
J. Wakerly, Stanford University'

Z74X138 device 'P16L8';
" Input pins

DO NOT COPYA, B, C, !G2A, !G2B, G1
pin 1, 2, 3, 4, 5, 6;

" Output pins pin 19, 18, 17, 16 istype 'com';
!Y0, !Y1, !Y2, !Y3
!Y4, !Y5, !Y6, !Y7 NOT COPYpin 15, 14, 13, 12 istype 'com';

DO" Constant expression

ENB = G1 & G2A & G2B;

equations COPY
Y0 = ENB & !C & !B & !A; COPY
Y1 = ENB & !C & !B & A;

DO NOTY2 = ENB & !C & B & !A;
Y3 = ENB & !C & B & A;

C & !B & !A;
C & !B & A;
C & B & !A;
C & B & A;
Y4 = ENB &
Y5 = ENB &
Y6 = ENB &

DO NOTY7 = ENB &
end Z74X138

For example, Table 5-8 is an ABEL program for a 74x138-like 3-to-8

DO NOT COPYbinary decoder as realized in a PAL16L8. A corresponding logic diagram with
signal names is shown in Figure 5-40. In the ABEL program, notice the use of

the “!” prefix in the pin declarations to specify active-low inputs and outputs,
even though the equations are written in terms of active-high signals.

DO NOT COPYPAL16L8
A 1 I1 Figure 5-40

Logic diagram for
2 I2 O1 19
DOB 3 I3 IO2 18
C4 I4 IO3 17
G2A_L 5 I5
G2B_L NOT COPYIO4 16
Y0_L the PAL16L8 used as
Y1_L a 74x138 decoder.
Y2_L
Y3_L

G1_L 6 I6 IO5 15 Y4_L

N.C. 7 I7IO6 14 Y5_L COPY
N.C. 8 I8IO7 13 Y6_L
N.C. 9 I9O8 12 Y7_L

DO NOTN.C. 11 I10

Z74X138

Copyright © 1999 by John F. Wakerly Copying Prohibited

324 Chapter 5 Combinational Logic Design Practices

Also note that this example defines a constant expression for ENB. Here,
ENB is not an input or output signal, but merely a user-defined name. In the

DO NOT COPYequations section, the compiler substitutes the expression (G1 & G2A & G2B)
everywhere that “ENB” appears. Assigning the constant expression to a user-
defined name improves the program’s readability and maintainability.
If all you needed was a ’138, you’d be better off using a real ’138 than a
PLD. However, if you need nonstandard functionality, then the PLD can usually

DO NOT COPYachieve it much more cheaply and easily than an MSISSI-based solution. For
example, if you need the functionality of a ’138 but with active-high outputs,

you need only to change two lines in the pin declarations of Table 5-8:
Y0, Y1, Y2, Y3

DO NOT COPYY4, Y5, Y6, Y7
pin 19, 18, 17, 16 istype ’com’;
pin 15, 14, 13, 12 istype ’com’;

Since each of the equations required a single product of six variables (including
the three in the ENB expression), each complemented equation requires a sum of
six product terms, less than the seven available in a PAL16L8. If you use a
PAL16V8 or other device with output polarity selection, then the compiler

DO NOT COPYselects non-inverted output polarity to use only one product term per output.
Another easy change is to provide alternate enable inputs that are ORed

DO NOT COPYEN1, !EN2
with the main enable inputs. To do this, you need only define additional pins and
modify the definition of ENB:

pin 7, 8;

...

ENB = G1 & G2A & G2B # EN1 # EN2;

This change expands the number of product terms per output to three, each

DO NOT COPYhaving a form similarto
Y0 = G1 & G2A & G2B & !C & !B &!A

# EN1 & !C & !B & !A
# EN2 & !C & !B & !A;

(Remember that the PAL16L8 has a fixed inverter and the PAL16V8 has a

DO NOT COPYselectable inverter between the AND-OR array and the output of the PLD, so the
actual output is active low as desired.)

If you add the extra enables to the version of the program with active-high
outputs, then the PLD must realize the complement of the sum-of-products

DO NOT COPYexpression above. It’s not immediately obvious how many product terms this
expression will have, and whether it will fit in a PAL16L8, but we can use the
ABEL compiler to get the answer for us:

!Y0 = C # B # A # !G2B & !EN1 & !EN2
# !G2A & !EN1 & !EN2

DO NOT COPY# !G1 & !EN1 & !EN2;
The expression has a total of six product terms, so it fits in a PAL16L8.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 325

Ta b l e 5 - 9 ABEL program fragment showing two-pass logic.

DO NOT COPY...

" Output pins
!Y0, !Y1, !Y2, !Y3 pin 19, 18, 17, 16 istype 'com';

equations

DO NOT COPYENB = G1 & G2A & G2B # EN1 # EN2;
!Y4, !Y5, !Y6, ENB pin 15, 14, 13, 12 istype 'com';

Y0 = POL $ (ENB & !C & !B & !A);

...

As a final tweak, we can add an input to dynamically control whether the

DO NOT COPYoutput is active high or active low, and modify all of the equations as follows:
POL pin 9;
... COPY
Y0 = POL $ (ENB & !C & !B & !A);
Y1 = POL $ (ENB & !C & !B & A);

DO NOT...

Y7 = POL $ (ENB & C & B & A);

As a result of the XOR operation, the number of product terms needed per output
increases to 9, in either output-pin polarity. Thus, even a PAL16V8 cannot

DO NOT COPYimplement the function as written.
The function can still be realized if we create a helper output to reduce the helper output

product term explosion. As shown in Table 5-9, we allocate an output pin for the
ENB expression, and move the ENB equation into the equations section of the
program. This reduces the product-term requirement to 5 in either polarity.

DO NOT COPYBesides sacrificing a pin for the helper output, this realization has the
helper output

disadvantage of being slower. Any changes in the inputs to the helper expression

must propagate through the PLD twice before reaching the final output. This is
called two-pass logic. Many PLD and FPGA synthesis tools can automatically two-pass logic
DO NOT COPYTable 5-10
Truth table for a CS_L RD_L A2 A1 A0 Output(s) to Assert

1 x x xx none
customized decoder x
0 none
DO NOT COPYfunction.0
1 x xx

0 0 0 0 BILL_L, MARY_L

0 0 0 1 MARY_L, KATE_L

0 0 0 10 JOAN_L

0 0 0 11PAUL_L
0 0 1 00ANNA_L
FRED_L
DO NOT COPY0 0 1 0 1
0 0 1 10 DAVE_L

0 0 1 11 KATE_L

Copyright © 1999 by John F. Wakerly Copying Prohibited

326 Chapter 5 Combinational Logic Design Practices

Figure 5-41+5V 74x138 74x08 BILL_L
Customized
R Y0 15 1 3 MARY_L
DDOO NNOOTT CCOOPPYYdecodercircuit.6 G1Y1 14
Y2 13 2 JOAN_L
4 G2A Y3 12 PAUL_L
CS_L 5 G2B U2 ANNA_L
RD_L FRED_L
DAVE_L
A0 1A Y4 11 74x08
A1 2B Y5 10
A2 3C Y6 9 4
Y7 7

6 KATE_L
U2
DO NOT COPYgenerate logic with two or more passes if a required expression cannot beU1 5

realized in just one pass through the logic array.

Decoders can be customized in other ways. A common customization is
for a single output to decode more than one input combination. For example,

DO NOT COPYsuppose you needed to generate a set of enable signals according to Table 5-10
on the preceding page. A 74x138 MSI decoder can be augmented as shown in
Figure 5-41 to perform the required function. This approach, while potentially
less expensive than a PLD, has the disadvantages that it requires extra compo-

DO NOT COPYnents and delay to create the required outputs, and it is not easily modified.
Ta b l e 5 - 1 1 ABEL equations for a customized decoder.

module CUSTMDEC
title 'Customized Decoder PLD

DO NOT COPYJ. Wakerly, Stanford University'
CUSTMDEC device ’P16L8’;

" Input pins
!CS, !RD, A0, A1, A2
" Output pins

DO NOT COPY!BILL, !MARY, !JOAN, !PAUL
pin 1, 2, 3, 4, 5;
pin 19, 18, 17, 16 istype 'com';

!ANNA, !FRED, !DAVE, !KATE pin 15, 14, 13, 12 istype 'com';

equations A0);
BILL = CS & RD & (!A2 & !A1 & !A0); A0);
MARY = CS & RD & (!A2 & !A1 & !A0 # !A2 & !A1 &

DO NOT COPYKATE = CS & RD & (!A2 & !A1 & A0 # A2 & A1 &
JOAN = CS & RD & (!A2 & A1 & !A0);

PAUL = CS & RD & (!A2 & A1 & A0);
ANNA = CS & RD & ( A2 & !A1 & !A0);
FRED = CS & RD & ( A2 & !A1 & A0);

DO NOT COPYDAVE = CS & RD & ( A2 & A1 & !A0);
end CUSTMDEC

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 327

A PLD solution to the same problem is shown in Table 5-11. Each of the
last six equations uses a single AND gate in the PLD. The ABEL compiler will

DO NOT COPYalso minimize the MARY equation to use just one AND gate. Once again, active-

high output signals could be obtained just by changing two lines in the declara-
tion section:
pin 19, 18, 17, 16 istype ’com’;
BILL, MARY, JOAN, PAUL
NOT COPYpin 15, 14, 13, 12 istype ’com’;
DOANNA, FRED, DAVE, KATE
Another way of writing the equations is shown in Table 5-12. In most

applications, this style is more clear, especially if the select inputs have numeric
significance.

DO NOT COPYTable 5 -12 Equivalent ABEL equations for a customized decoder.

ADDR = [A2,A1,A0]; COPY
COPY
equations

DO NOTBILL = CS & RD & (ADDR == 0);

MARY = CS & RD & (ADDR == 0) # (ADDR == 1);
KATE = CS & RD & (ADDR == 1) # (ADDR == 7);
JOAN = CS & RD & (ADDR == 2);
PAUL = CS & RD & (ADDR == 3);
ANNA = CS & RD & (ADDR == 4);

DO NOTFRED = CS & RD & (ADDR == 5);

DAVE = CS & RD & (ADDR == 6);

5.4.7 Decoders in VHDL

DO NOT COPYThere are several ways to approach the design of decoders in VHDL. The most

primitive approach would be to write a structural equivalent of a decoder logic
circuit, as Table 5-13 does for the 2-to-4 binary decoder of Figure 5-32 on
page 314. Of course, this mechanical conversion of an existing design into the
equivalent of a netlist defeats the purpose of using VHDL in the first place.

DO NOT COPYInstead, we would like to write a program that uses VHDL to make our

decoder design more understandable and maintainable. Table 5-14 shows one
approach to writing code for a 3-to-8 binary decoder equivalent to the 74x138,
using the dataflow style of VHDL. The address inputs A(2 downto 0) and the
active-low decoded outputs Y_L(0 to 7) are declared using vectors to improve

DO NOT COPYreadability. A select statement enumerates the eight decoding cases and

assigns the appropriate active-low output pattern to an 8-bit internal signal
Y_L_i. This value is assigned to the actual circuit output Y_L only if all of the
enable inputs are asserted.

DO NOT COPYThis design is a good start, and it works, but it does have a potential pitfall.

The adjustments that handle the fact that two inputs and all the outputs are
active-low happen to be buried in the final assignment statement. While it’s true

Copyright © 1999 by John F. Wakerly Copying Prohibited

328 Chapter 5 Combinational Logic Design Practices

Ta b l e 5 - 1 3 VHDL structural program for the decoder in Figure 5-32.

DO NOT COPYlibrary IEEE;
use IEEE.std_logic_1164.all;

entity V2to4dec is COPY
port (I0, I1, EN: in STD_LOGIC;
Y0, Y1, Y2, Y3: out STD_LOGIC );

DO NOTend V2to4dec;
architecture V2to4dec_s of V2to4dec is
signal NOTI0, NOTI1: STD_LOGIC;
component inv port (I: in STD_LOGIC; O: out STD_LOGIC ); end component;
component and3 port (I0, I1, I2: in STD_LOGIC; O: out STD_LOGIC ); end component;

DO NOT COPYbegin
U1: inv port map (I0,NOTI0);

U2: inv port map (I1,NOTI1); COPY
U3: and3 port map (NOTI0,NOTI1,EN,Y0);
U4: and3 port map ( I0,NOTI1,EN,Y1);

DO NOTU5: and3 port map (NOTI0, I1,EN,Y2);
U6: and3 port map ( I0, I1,EN,Y3);
end V2to4dec_s;

DO NOT COPYTa ble 5- 14 Dataflow-style VHDL program for a 74x138-like 3-to-8 binary decoder.
library IEEE;

use IEEE.std_logic_1164.all;
entity V74x138 is

DO NOT COPYport (G1, G2A_L, G2B_L: in STD_LOGIC;
-- enable inputs

A: in STD_LOGIC_VECTOR (2 downto 0); -- select inputs

Y_L: out STD_LOGIC_VECTOR (0 to 7) ); -- decoded outputs

end V74x138;
architecture V74x138_a of V74x138 is

DO NOT COPYsignal Y_L_i: STD_LOGIC_VECTOR (0 to 7);
begin
with A select Y_L_i <=
"01111111" when "000", COPY
"10111111" when "001",
"11011111" when "010",

DO NOT"11101111" when "011",
"11110111" when "100",

"11111011" when "101", COPY
"11111101" when "110",
"11111110" when "111",

DO NOT"11111111" when others;
Y_L <= Y_L_i when (G1 and not G2A_L and not G2B_L)='1' else "11111111";

end V74x138_a;

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 329

Ta b l e 5 - 1 5 VHDL architecture with a maintainable approach to active-level handling.

DO NOT COPYarchitecture V74x138_b of V74x138 is
signal G2A, G2B: STD_LOGIC; -- active-high version of inputs

signal Y: STD_LOGIC_VECTOR (0 to 7); -- active-high version of outputs

signal Y_s: STD_LOGIC_VECTOR (0 to 7);
begin

G2A <= not G2A_L; -- convert inputs

DO NOT COPYG2B <= not G2B_L; -- convert inputs
-- internal signal

Y_L <= Y; -- convert outputs

with A select Y_s <= COPY
"10000000" when "000",
"01000000" when "001",
"00100000" when "010",

DO NOT"00010000" when "011",
"00001000" when "100",

"00000100" when "101", COPY
"00000010" when "110",
"00000001" when "111",

DO NOT"00000000" when others;
Y <= not Y_s when (G1 and G2A and G2B)='1' else "00000000";

end V74x138_b;

that most VHDL programs are written almost entirely with active-high signals,

DO NOT COPYif we’re defining a device with active-low external pins, we really should handle
them in a more systematic and easily maintainable way.

Table 5-15 shows such an approach. No changes are made to the entity
declarations. However, active-high versions of the active-low external pins are
defined within the V74x138_a architecture, and explicit assignment statements

DO NOT COPYare used to convert between the active-high and active-low signals. The decoder
function itself is defined in terms of only the active-high signals, probably the

biggest advantage of this approach. Another advantage is that the design can be
easily modified in just a few well-defined places if changes are required in the

DO NOT COPYexternalactive levels.

OUT-OF-ORDER In Table 5-15, we’ve grouped all three of the active-level conversion statements
EXECUTION together at the beginning of program, even a value isn’t assigned to Y_L until after a

DO NOT COPYvalue is assigned to Y, later in the program. Remember that this is OK because the
assignment statements in the architecture body are executed “concurrently.” That is,
an assignment to any signal causes all the other statements that use that signal to be
re-evaluated, regardless of their position in the architecture body.

You could put the “Y_L <= Y” statement at the end of the body if its current

DO NOT COPYposition bothers you, but the program is a bit more maintainable in its present form,
with all the active-level conversions together.

Copyright © 1999 by John F. Wakerly Copying Prohibited

330 Chapter 5 Combinational Logic Design Practices

Ta b l e 5 - 1 6 Hierarchical definition of 74x138-like decoder with active-level handling.

DO NOT COPYarchitecture V74x138_c of V74x138 is
signal G2A, G2B: STD_LOGIC; -- active-high version of inputs

signal Y: STD_LOGIC_VECTOR (0 to 7); -- active-high version of outputs

component V3to8dec port (G1, G2, G3: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (2 downto 0);
Y: out STD_LOGIC_VECTOR (0 to 7) ); end component;

DO NOT COPYbegin
G2A <= not G2A_L; -- convert inputs

G2B <= not G2B_L; -- convert inputs
DO NOT COPYend V74x138_c;
Y_L <= not Y; -- convert outputs

U1: V3to8dec port map (G1, G2A, G2B, A, Y);

Active levels can be handled in an even more structured way. As shown in
Table 5-16, the V74x138 architecture can be defined hierarchically, using a fully
active-high V3to8dec component that has its own dataflow-style definition in

DO NOT COPYTable 5-17. Once again, no changes are required in the top-level definition of the
V74x138 entity. Figure 5-42 shows the relationship between the entities.

Still another approach to decoder design is shown in Table 5-18, which can
replace the V3to8dec_a architecture of Table 5-17. Instead of concurrent state-
DO NOT COPYTable 5-17
library IEEE;
Dataflow definition of use IEEE.std_logic_1164.all;

an active-high 3-to-8
DO NOT COPYdecoder.
entity V3to8dec is
port (G1, G2, G3: in STD_LOGIC;
A: in STD_LOGIC_VECTOR (2 downto 0);

Y: out STD_LOGIC_VECTOR (0 to 7) );

end V3to8dec;

DO NOT COPYarchitecture V3to8dec_a of V3to8dec is
signal Y_s: STD_LOGIC_VECTOR (0 to 7);
begin
with A select Y_s <=
"10000000" when "000",
DO
NOT COPY"01000000" when "001",
"00100000" when "010",

"00010000" when "011",

"00001000" when "100",
"00000100" when "101",

DO NOT COPY"00000010" when "110",
"00000001" when "111",
"00000000" when others;
Y <= Y_s when (G1 and G2 and G3)='1'
else "00000000";
end V3to8dec_a;

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 331

DO NOT COPYentityV74x138
entity V74x138
entity V3to8dec

G1 Y_L[0:7] G1 G1

G2A_L G2A
G2A_L NOT COPYnot G2
Y[0:7] Y[0:7] Y_L[0:7]
DOG2B_L not
A[2:0] G2B_L G2B
not G3

A[2:0] A[2:0]

(a) (b)

Figure 5-42 VHDL entity V74x138: (a) top level; (b) internal structure using

DO NOT COPYarchitecture V74x138_c.
NAME MATCHING In Figure 5-42, the port names of an entity are drawn inside the corresponding box.

The names of the signals that are connected to the ports when the entity is used are
drawn on the signal lines. Notice that the signal names may match, but they don’t
have to. The VHDL compiler keeps everything straight, associating a scope with

DO NOT COPYeach name. The situation is completely analogous to the way variable and parameter
names are handled in structured, procedural programming languages like C.

ments, this architecture uses a process and sequential statements to define the

DO NOT COPYdecoder’s operation in a behavioral style. However, a close comparison of the
two architectures shows that they’re really not that different except for syntax.

architecture V3to8dec_b of V3to8dec is
signal Y_s: STD_LOGIC_VECTOR (0 to 7);

DO NOT COPYbegin
Table 5-18
Behavioral-style
architecture definition

process(A, G1, G2, G3, Y_s) for a 3-to-8 decoder.

begin COPY
case A is
when "000" => Y_s <= "10000000";

DO NOTwhen "001" => Y_s <= "01000000";
when "010" => Y_s <= "00100000";
when "011" => Y_s <= "00010000";
when "100" => Y_s <= "00001000"; COPY
when "101" => Y_s <= "00000100";
when "110" => Y_s <= "00000010";

DO NOTwhen "111" => Y_s <= "00000001";
when others => Y_s <= "00000000";

end case; COPY
if (G1 and G2 and G3)='1' then Y <= Y_s;
else Y <= "00000000";

DO NOTend if;

end process;
end V3to8dec_b;

Copyright © 1999 by John F. Wakerly Copying Prohibited

332 Chapter 5 Combinational Logic Design Practices

Ta ble 5- 19
Truly behavioral

DO NOT COPYarchitecturedefinition
architecture V3to8dec_c of V3to8dec is
begin
process (G1, G2, G3, A)

for a 3-to-8 decoder. variable i: INTEGER range 0 to 7;

begin

DO NOT COPYY <= "00000000";
if (G1 and G2 and G3) = '1' then
for i in 0 to 7 loop
if i=CONV_INTEGER(A) then Y(i) <= '1'; end if;
end loop;

end if;
end process;

DO NOT COPYend V3to8dec_c;
As a final example, a more truly behavioral, process-based architecture for
the 3-to-8 decoder is shown in Table 5-19. (Recall that the CONV_INTEGER func-
tion was defined in \secref{VHDLconv}.) Of the examples we’ve given, this is

DO NOT COPYthe only one that describes the decoder function without essentially embedding
a truth table in the VHDL program. In that respect, it is more flexible because it
can be easily adapted to make a binary decoder of any size. In another respect, it
is less flexible in that it does not have a truth table that can be easily modified to

DO NOT COPYmake custom decoders like the one we specified in Table 5-10 on page 325.
*5.4.8 Seven-Segment Decoders

Look at your wrist and you’ll probably see a seven-segment display. This type
of display, which normally uses light-emitting diodes (LEDs) or liquid-crystal
display (LCD) elements, is used in watches, calculators, and instruments to
display decimal data. A digit is displayed by illuminating a subset of the seven
DO NOT COPYseven-segmentdisplay
line segments shown in Figure 5-43(a).

A seven-segment decoder has 4-bit BCD as its input code and the “seven-
segment code,” which is graphically depicted in Figure 5-43(b), as its output
code. Figure 5-44 and Table 5-20 are the logic diagram truth table and for a
74x49 seven-segment decoder. Except for the strange (clever?) connection of the
seven-segment decoder

DO NOT COPY74x49
“blanking input” BI_L, each output of the 74x49 is a minimal product-of-sums

DO NOT COPYFigure 5-43 Seven-segment display: (a) segment identification; (b) decimal digits.
a

f b NOT
g
DOe c COPY
d

(a) (b)

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 333

DO NOT COPY(a)
(11)
a

DO NOT COPY

(10)
(b) 3 b

DO NOT COPYBI74x49

11

a

10
b

59
Ac

18
Bd
(9)
2 6
c
Ce

4 13

DO NOT COPYDf

12

g

DO NOT COPY(8)
d

(3) (6)

DO NOT COPYBI_L e

DO(5) NOT COPY (13)
A
B (1) f

DO(2) NOT COPY
C (12) g

DO(4) NOT COPY
D
Figure 5-44 The 74x49 seven-segment decoder: (a) logic diagram, including

pin numbers; (b) traditional logic symbol.

Copyright © 1999 by John F. Wakerly Copying Prohibited

334 Chapter 5 Combinational Logic Design Practices

DO NOT COPYTable 5-20 Truth table for a 74x49 seven-segment decoder.Inputs
Outputs

DO BI_L D C B A a bcde fg
DO
DO NOT0 x x x x COPY0 0 0 0 0 0 0
DO 1 0000 1 111110
DO 1 0001 0 110000

NOT1 0 0 1 0 COPY1 1 0 1 1 0 1
1 0011 1 111001
1 0100 0 110011
1 0101 1 011011

NOT1 0 1 1 0 COPY0 0 1 1 1 1 1
1 0111 1 110000
1 1000 1 111111

NOT1 1 0 0 1 COPY1 1 1 0 0 1 1
1 1010 0 001101
1 1011 0 011001
1 1100 0 100011

NOT1 1 1 0 1 COPY1 0 0 1 0 1 1
1 1110 0 001111
1 1111 0 000000

realization for the corresponding segment, assuming “don’t-cares” for the non-
decimal input combinations. The INVERT-OR-AND structure used for each

DO NOT COPYoutput may seem a little strange, but it is equivalent under the generalized
DeMorgan’s theorem to an AND-OR-INVERT gate, which is a fairly fast and
compact structure to build in CMOS or TTL.
Most modern seven-segment display elements have decoders built into
them, so that a 4-bit BCD word can be applied directly to the device. Many of the

DO NOT COPYolder, discrete seven-segment decoders have special high-voltage or high-
current outputs that are well suited for driving large, high-powered display
elements.
Table 5-21 is an ABEL program for a seven-segment decoder. Sets are

DO NOT COPYused to define the digit patterns to make the program more readable.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.4 Decoders 335

Ta b l e 5 - 2 1 ABEL program for a 74x49-like seven-segment decoder.

DO NOT COPYmodule Z74X49H

title 'Seven-Segment_Decoder
J. Wakerly, Micro Design Resources, Inc.'

Z74X49H device 'P16L8';
" Input pins

DO NOT COPYA, B, C, D
pin 1, 2, 3, 4;

!BI pin 5;

" Output pins
SEGA, SEGB, SEGC, SEGD

DO NOT COPYSEGE, SEGF, SEGG
pin 19, 18, 17, 16 istype 'com';

pin 15, 14, 13 istype 'com';

" Set definitions

DIGITIN = [D,C,B,A]; COPY
SEGOUT = [SEGA,SEGB,SEGC,SEGD,SEGE,SEGF,SEGG]; COPY
COPY
DO NOT" Segment encodings for digits COPY
DIG0 = [1,1,1,1,1,1,0]; " 0

DIG1 = [0,1,1,0,0,0,0]; " 1

DIG2 = [1,1,0,1,1,0,1];"2
DIG3 = [1,1,1,1,0,0,1];"3
DIG4 = [0,1,1,0,0,1,1];"4
"5
DO NOTDIG5 = [1,0,1,1,0,1,1];
DIG6 = [1,0,1,1,1,1,1]; " 6 'tail' included

DIG7 = [1,1,1,0,0,0,0]; " 7
DIG8 = [1,1,1,1,1,1,1]; " 8
DIG9 = [1,1,1,1,0,1,1]; " 9 'tail' included

DO NOTDIGA = [1,1,1,0,1,1,1]; " A

DIGB = [0,0,1,1,1,1,1]; " b
DIGC = [1,0,0,1,1,1,0]; " C

DIGD = [0,1,1,1,1,0,1]; " d
DIGE = [1,0,0,1,1,1,1]; " E

DO NOTDIGF = [1,0,0,0,1,1,1]; " F
equations

SEGOUT = !BI & ( (DIGITIN ==
# (DIGITIN ==
# (DIGITIN ==

DO NOT COPY# (DIGITIN ==
0) & DIG0 # (DIGITIN == 1) & DIG1
2) & DIG2 # (DIGITIN == 3) & DIG3
4) & DIG4 # (DIGITIN == 5) & DIG5
6) & DIG6 # (DIGITIN == 7) & DIG7

# (DIGITIN == 8) & DIG8 # (DIGITIN == 9) & DIG9

# (DIGITIN == 10) & DIGA # (DIGITIN == 11) & DIGB
# (DIGITIN == 12) & DIGC # (DIGITIN == 13) & DIGD

DO NOT COPY# (DIGITIN == 14) & DIGE # (DIGITIN == 15) & DIGF );

end Z74X49H

Copyright © 1999 by John F. Wakerly Copying Prohibited

336 Chapter 5 Combinational Logic Design Practices

5.5 Encoders

DO NOT COPYA decoder’s output code normally has more bits than its input code. If the
device’s output code has fewer bits than the input code, the device is usually
encoder called an encoder. For example, consider a device with eight input bits repre-

senting an unsigned binary number, and two output bits indicating whether the
number is prime or divisible by 7. We might call such a device a lucky/prime

DO NOT COPYencoder.
2n-to-n encoder Probably the simplest encoder to build is a 2n-to-n or binary encoder. As

binary encoder shown in Figure 5-45(a), it has just the opposite function as a binary decoder—
its input code is the 1-out-of-2n code and its output code is n-bit binary. The
equations for an 8-to-3 encoder with inputs I0–I7 and outputs Y0–Y2 are given

DO NOT COPYbelow:
Y0 = I1 + I3 + I5 + I7

Y1 = I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 + I7

DO NOT COPYThe corresponding logic circuit is shown in (b). In general, a 2n-to-n encoder can
be built from n 2n−1-input OR gates. Bit i of the input code is connected to OR
gate j if bit j in the binary representation of i is 1.
DO NOT COPYFigure 5-45
Binary encoder: Binary Y0
(a) general structure; encoder

DO NOT COPY(b)8-to-3 encoder. I0
I0 Y0 I1 Y1
I1 Y1 I2
2n inputs I2 n outputs I3

I4

I5 Y2
I6
(b) I7
Yn–1
I2n–1

DO NOT COPY(a)
5.5.1 Priority Encoders
The 1-out-of-2 n coded outputs of an n-bit binary decoder are generally used to
control a set of 2n devices, where at most one device is supposed to be active at

DO NOT COPYany time. Conversely, consider a system with 2n inputs, each of which indicates
a request for service, as in Figure 5-46. This structure is often found in micro-

processor input/output subsystems, where the inputs might be interrupt requests.

In this situation, it may seem natural to use a binary encoder of the type

shown in Figure 5-45 to observe the inputs and indicate which one is requesting

DO NOT COPYservice at any time. However, this encoder works properly only if the inputs are
guaranteed to be asserted at most one at a time. If multiple requests can be made

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.5 Encoders 337

Request

DO NOT COPYencoder
REQ1 Figure 5-46
A system with 2n
REQ2
REQ3 requestors, and a “request

encoder” that indicates
Requests Requestor's
number
DO NOT COPYforservice
REQN which request signal is

asserted at any time.

simultaneously, the encoder gives undesirable results. For example, suppose that

DO NOT COPYinputs I2 and I4 of the 8-to-3 encoder are both 1; then the output is 110, the
binary encoding of 6.

Either 2 or 4, not 6, would be a useful output in the preceding example, but priority
how can the encoding device decide which? The solution is to assign priority to
the input lines, so that when multiple requests are asserted, the encoding device

DO NOT COPYproduces the number of the highest-priority requestor. Such a device is called a
priority encoder. priority encoder

The logic symbol for an 8-input priority encoder is shown in Figure 5-47.
Input I7 has the highest priority. Outputs A2–A0 contain the number of the
highest-priority asserted input, if any. The IDLE output is asserted if no inputs

DO NOT COPYareasserted.
In order to write logic equations for the priority encoder’s outputs, we first

define eight intermediate variables H0–H7, such that Hi is 1 if and only if Ii is the Priority
highest priority 1 input: encoder

DO NOT COPYH7 = I7 I7
H6 = I6 ⋅ I7′

H5 = I5 ⋅ I6′ ⋅ I7′ I6 A2
… I5 A1
I4 A0
DO NOT COPYH0 = I0 ⋅ I1′ ⋅ I2′ ⋅ I3′ ⋅ I4′ ⋅ I5′ ⋅ I6′ ⋅ I7′ I3

I2 IDLE

Using these signals, the equations for the A2–A0 outputs are similar to the ones
for a simple binary encoder:

A2 = H4 + H5 + H6 + H7

DO NOT COPYA1 = H2+H3+H6+H7
I1
I0

Figure 5-47
Logic symbol for
A0 = H1 + H3 + H5 + H7
The IDLE output is 1 if no inputs are 1:

DO NOT COPYIDLE = (I0 + I1 + I2 + I3 + I4 + I5 + I6 + I7)′
a generic 8-input
priority encoder.

= I0′ ⋅ I1′ ⋅ I2′ ⋅ I3′ ⋅ I4′ ⋅ I5′ ⋅ I6′ ⋅ I7′

Copyright © 1999 by John F. Wakerly Copying Prohibited

338 Chapter 5 Combinational Logic Design Practices

DO NOT COPY74x148
5.5.2 The 74x148 Priority Encoder
The 74x148 is a commercially available, MSI 8-input priority encoder. Its logic
symbol is shown in Figure 5-48 and its schematic is shown in Figure 5-49. The

main difference between this IC and the “generic” priority encoder of

Figure 5-47 is that its inputs and outputs are active low. Also, it has an enable
input, EI_L, that must be asserted for any of its outputs to be asserted. The
complete truth table is given in Table 5-22.

Instead of an IDLE output, the ’148 has a GS_L output that is asserted when
74x148

DO NOT COPY5 EI
4 I7

3

I6
2 I5
1 I4

13 I3

DO NOT COPY12 I2
A2 6 the device is enabled and one or more of the request inputs is asserted. The
A1 7 manufacturer calls this “Group Select,” but it’s easier to remember as “Got
A0 9 Something.” The EO_L signal is an enable output designed to be connected to
the EI_L input of another ’148 that handles lower-priority requests. /EO is
GS 14 asserted if EI_L is asserted but no request input is asserted; thus, a lower-priority

11 I1 EO 15 ’148 may be enabled.

10 I0

Figure 5-48

DO NOT COPYLogicsymbolfor
Figure 5-50 shows how four 74x148s can be connected in this way to
accept 32 request inputs and produce a 5-bit output, RA4–RA0, indicating the
highest-priority requestor. Since the A2–A0 outputs of at most one ’148 will be
enabled at any time, the outputs of the individual ’148s can be ORed to produce
the 74x148 8-input

DO NOT COPYpriorityencoder.
RA2–RA0. Likewise, the individual GS_L outputs can be combined in a 4-to-2
encoder to produce RA4 and RA3. The RGS output is asserted if any GS output
is asserted.

Ta b l e 5 - 2 2 Truth table for a 74x148 8-input priority encoder.

Inputs

DO NOT COPY/EI /I0 /I1 /I2 /I3 /I4 /I5 /I6 /I7
Outputs
/A2 /A1 /A0 /GS /EO

1xxxxxxxx 111 1 1
0xxxxxxx0

DO NOT COPY0 x x x x x x 0 1
000 0 1
001 0 1

0xxxxx011 010 0 1

0xxxx0111
0xxx01111

DO NOT COPY0 x x 0 1 1 1 1 1
011 0 1
100 0 1
101 0 1

110 0 1
111 0 1
111 1 0
0x0111111
001111111

DO NOT COPY0 1 1 1 1 1 1 1 1

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.5 Encoders 339

(10)

DO NOT COPYI0_L
(15)

EO_L

(11) (14)

DO NOT COPYI1_L GS_L

(12)

DO NOT COPYI2_L
(9)
A0_L
(13)

DO NOT COPYI3_L

(1)

DO NOT COPYI4_L
(7)

A1_L
(2)

DO NOT COPYI5_L
(3)

DOI6_L NOT COPY
(4)
DO NOT COPYI7_L
(6)

A2_L

(5)

EI_L

Figure 5-49 Logic diagram for the 74x148 8-input priority encoder, including

DO NOT COPYpin numbers for a standard 16-pin dual in-line package.

Copyright © 1999 by John F. Wakerly Copying Prohibited

340 Chapter 5 Combinational Logic Design Practices

DO NOT74x148 COPY
5 EI
REQ31_L 4 I7
3 6 G3A2_L
REQ30_L I6 A2
2 7 G3A1_L
REQ29_L I5 A1
DO NOTREQ28_L1 9 G3A0_L COPY
REQ27_L13I4 G3GS_L
REQ26_L12I3A0
REQ25_L11I2
I1 14

10 GS

REQ24_L 15

EO

I0

DO NOTG3EO_L U1 COPY
74x148
5 EI
REQ23_L 4 I7
3 6 G2A2_L
REQ22_L I6 A2
DO NOTREQ21_L2 7 G2A1_L COPY74x00
REQ20_L1I5 G2A0_L 1 RA4
REQ19_L13I4A1 3
REQ18_L12I3 G2GS_L 2
I2 9
U5
11 A0

REQ17_L 14

GS
15
I1
EO
DO NOT10
REQ16_LI0 COPY74x00
4
G2EO_L U2 6
74x148 5
RA3

5 EI U5

DO NOTREQ15_L4 I7 6 G1A2_L COPY1 74x20
REQ14_L3I6 G1A1_L 2
REQ13_L2I5A2 G1A0_L 4 6 RA2
REQ12_L1I4 5 U6
REQ11_L13I37

A1

9

A0

12 I2 14 G1GS_L 9 74x20
GS
REQ10_L 15 COPY10
DO NOT11 12 8 RA1
REQ9_LI1EO 13 U6
10I0U3
REQ8_L 1 74x20
G1EO_L
COPY2
74x148 4 6 RA0
5 U7
DO NOT5 EI
REQ7_L 4 I7 G0A2_L 9 74x20
3 6 G0A1_L
REQ6_L I6 G0A0_L 10
2 A2
REQ5_L I5 COPY8
REQ4_L 1 I4 7 12 RGS
13 13 U7
A1
REQ3_L
9

A0

I3 G0GS_L

12 14
11
10 GS

15

EO
DO NOTREQ2_L I2
REQ1_LI1
REQ0_LI0

U4

Figure 5-50 Four 74x148s cascaded to handle 32 requests.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.5 Encoders 341

5.5.3 Encoders in ABEL and PLDs
Encoders can be designed in ABEL using an explicit equation for each input

DO NOT COPYcombinations, as in Table 5-8 on page 323, or using truth tables. However, since
the number of inputs is usually large, the number of input combinations is very

large, and this method often is not practical.

For example, how would we specify a 15-input priority encoder for inputs
P0–P14? We obviously don’t want to deal with all 215 possible input combina-

DO NOT COPYtions! One way to do it is to decompose the priority function into two parts. First,
we write equations for 15 variables Hi (0≤ i≤ 14) such that Hi is 1 if Pi is the

highest-priority asserted input. Since by definition at most one Hi variable is 1 at
any time, we can combine the Hi’s in a binary encoder to obtain a 4-bit number
identifying the highest-priority asserted input.

DO NOT COPYAn ABEL program using this approach is shown in Table 5-23, and a logic
diagram for the encoder using a single PAL20L8 or GAL20V8 is given in

Figure 5-51. Inputs P0–P14 are asserted to indicate requests, with P14 having
the highest priority. If EN_L (Enable) is asserted, then the Y3_L–Y0_L outputs

DO NOT COPYgive the number (active low) of the highest-priority request, and GS is asserted

if any request is present. If EN_L is negated, then the Y3_L–Y0_L outputs are
negated and GS is negated. ENOUT_L is asserted if EN_L is asserted and no
request is present.

Notice that in the ABEL program, the equations for the Hi variables are

DO NOT COPYwritten as “constant expressions,” before the equations declaration. Thus,
these signals will not be generated explicitly. Rather, they will be incorporated in

the subsequent equations for Y0–Y3, which the compiler cranks on to obtain
DO NOT COPYP0 1 I1
PAL20L8

P1 2 I2 Figure 5-51
Logic diagram for a
PLD-based 15-input
priority encoder
DO NOT COPYP5 6 I6 IO3 20P2 3 I3
P3 4 I4 O1 22
ENOUT_L
P4 5 I5 IO2 21 Y0_L
Y1_L
P6 7 I7 IO4 19
P7 8 I8 IO5 18 Y2_L

DO NOT COPYP10 11 I11 Y3_L
P8 9 I9 IO6 17 GS
P9 10 I10 IO7 16
O8 15

P11 13 I12
P12 14 I13
P13 23 I14

DO NOT COPYPRIOR15
P14

EN_L

Copyright © 1999 by John F. Wakerly Copying Prohibited

342 Chapter 5 Combinational Logic Design Practices

Ta b l e 5 - 2 3 An ABEL program for a 15-input priority encoder.

DO NOT COPYmodule PRIOR15

title '15-Input Priority Encoder
J. Wakerly, DAVID Systems, Inc.'

PRIOR15 device 'P20L8';
" Input pins

DO NOT COPYP0, P1, P2, P3, P4, P5, P6, P7
pin 1, 2, 3, 4, 5, 6, 7, 8;

P8, P9, P10, P11, P12, P13, P14 pin 9, 10, 11, 13, 14, 23, 16;

!EN pin 17;
" Output pins NOT COPYpin 18, 19, 20, 21 istype 'com';
!Y3, !Y2, !Y1, !Y0 pin 15, 22 istype 'com';

DOGS, !ENOUT
" Constant expressions

H14 = EN&P14; COPY
H13 = EN&!P14&P13;
H12 = EN&!P14&!P13&P12;

DO NOTH11 = EN&!P14&!P13&!P12&P11;
H10 = EN&!P14&!P13&!P12&!P11&P10;

H9 = EN&!P14&!P13&!P12&!P11&!P10&P9;

H8 = EN&!P14&!P13&!P12&!P11&!P10&!P9&P8;
H7 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&P7;
H6 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&P6;

DO NOT COPYH5 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&P5;
H4 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&P4;

H3 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&P3;
H2 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&P2;
H1 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&!P2&P1;

DO NOT COPYH0 = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&!P2&!P1&P0;
equations
Y3 = H8 # H9 # H10 # H11 # H12 # H13 # H14; COPY
Y2 = H4 # H5 # H6 # H7 # H12 # H13 # H14;
Y1 = H2 # H3 # H6 # H7 # H10 # H11 # H14;

DO NOTY0 = H1 # H3 # H5 # H7 # H9 # H11 # H13;
GS = EN&(P14#P13#P12#P11#P10#P9#P8#P7#P6#P5#P4#P3#P2#P1#P0);
ENOUT = EN&!P14&!P13&!P12&!P11&!P10&!P9&!P8&!P7&!P6&!P5&!P4&!P3&!P2&!P1&!P0;

DO NOT COPYend PRIOR15
minimal sum-of-products expressions. As it turns out, each Yi output has only
seven product terms, as you can see from the structure of the equations.
The priority encoder can be designed even more intuitively use ABEL’s
DO NOT COPYWHEN statement. As shown in Table 5-24, a deeply nested series of WHEN state-
ments expresses precisely the logical function of the priority encoder. This
program yields exactly the same set of output equations as the previous program.

Copyright © 1999 by John F. Wakerly Copying Prohibited

Section 5.5 Encoders 343

Ta b l e 5 - 2 4 Alternate ABEL program for the same 15-input priority encoder.

DO NOT COPYmodule PRIOR15W

title '15-Input Priority Encoder'
PRIOR15W device 'P20L8';

" Input pins
P0, P1, P2, P3, P4, P5, P6, P7

DO NOT COPYP8, P9, P10, P11, P12, P13, P14
pin 1, 2, 3, 4, 5, 6, 7, 8;
pin 9, 10, 11, 13, 14, 23, 16;

!EN pin 17;

" Output pins NOT COPYpin 18, 19, 20, 21 istype 'com';
!Y3, !Y2, !Y1, !Y0 pin 15, 22 istype 'com';
GS, !ENOUT

DO" Sets
Y = [Y3..Y0];

equations
WHEN !EN THEN Y = 0;

DO NOT COPYELSE WHEN P14 THEN Y = 14;
ELSE WHEN P13 THEN Y = 13;

ELSE WHEN P12 THEN Y = 12;

ELSE WHEN P11 THEN Y = 11; COPY
ELSE WHEN P10 THEN Y = 10;
ELSE WHEN P9 THEN Y = 9;

DO NOTELSE WHEN P8 THEN Y = 8;
ELSE WHEN P7 THEN Y = 7;

DO NOTELSE WHEN P6 THEN Y = 6; COPY
ELSE WHEN P5 THEN Y = 5;
ELSE WHEN P4 THEN Y = 4;
ELSE WHEN P3 THEN Y = 3;
ELSE WHEN P2 THEN Y = 2;
ELSE WHEN P1 THEN Y = 1;

ELSE WHEN P0 THEN Y = 0;
ELSE {Y = 0; ENOUT = 1;};

DO NOT COPYGS = EN&(P14#P13#P12#P11#P10#P9#P8#P7#P6#P5#P4#P3#P2#P1#P0);
end PRIOR15W

5.5.4 Encoders in VHDL

DO NOT COPYThe approach to specifying encoders in VHDL is similar to the ABEL approach.

We could embed the equivalent of a truth table or explicit equations into the
VHDL program, but a behavioral description is far more intuitive. Since
VHDL’s IF-THEN-ELSE construct best describes prioritization and is available

DO NOT COPYonly within a process, we use the process-based behavioral approach.
Table 5-25 is a behavioral VHDL program for a priority encoder whose
function is equivalent to the 74x148. It uses a FOR loop to look for an asserted

Copyright © 1999 by John F. Wakerly Copying Prohibited

344 Chapter 5 Combinational Logic Design Practices

Ta b l e 5 - 2 5 Behavioral VHDL program for a 74x148-like 8-input priority encoder.

DO NOT COPYlibrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity V74x148 is
port (

DO NOT COPYEI_L: in STD_LOGIC;
I_L: in STD_LOGIC_VECTOR (7 downto 0);
A_L: out STD_LOGIC_VECTOR (2 downto 0);
EO_L, GS_L: out STD_LOGIC
);

DO NOT COPYend V74x148;
architecture V74x148p of V74x148 is

signal EI: STD_LOGIC; -- active-high version of input
DO NOT COPYsignal A: STD_LOGIC_VECTOR (2 downto 0); -- active-high version of outputs
signal I: STD_LOGIC_VECTOR (7 downto 0); -- active-high version of inputs

signal EO, GS: STD_LOGIC; -- active-high version of outputs

begin

process (EI_L, I_L, EI, EO, GS, I, A)

variable j: INTEGER range 7 downto 0;
begin

EI <= not EI_L; -- convert input

DO NOT COPYI <= not I_L; -- convert inputs
EO <= '1'; GS <= '0'; A <= "000";

DO NOTif (EI)='0' then EO <= '0'; COPY
else for j in 7 downto 0 loop
if GS = '1' then null;
elsif I(j)='1' then
GS <= '1'; EO <= '0'; A <= CONV_STD_LOGIC_VECTOR(j,3);

end if;

end loop;
end if;
EO_L <= not EO; -- convert output

DO NOT COPYGS_L <= not GS; -- convert output
A_L <= not A; -- convert outputs

end process;
end V74x148p;

DO NOT COPYinput, starting with the highest-priority input. Like some of our previous pro-
grams, it performs explicit active-level conversion at the beginning and end.

Also recall that the CONV_STD_LOGIC_VECTOR(j,n) function was defined in
\secref{VHDLconv} to convert from an integer j to a STD_LOGIC_VECTOR of a

DO NOT COPYspecified length n. This program is easily modified to use a different priority
order or a different number of inputs, or to add more functionality such as find-
ing a second-highest-priority input, as explored in Exercises \exref–\exref.

Copyright © 1999 by John F. Wakerly Copying Prohibited