Introduction to basic electricity and electronics technology by Earl D Gates

peopLe in eLeCtroniCS

DigitaL eLeCtroniC CirCuitS iBm
IBM coined the term hexadecimal consisting of the
francis Bacon (1561–1626) Greek prefix hex and the Latin suffix decimal. The
Bacon invented a “bilateral alphabet code,” a binary reason for not using an all-Latin name is that the
system that used the symbols A and B rather than name would have been sexadecimal.
0 and 1 to develop ciphers and codes.
maurice Karnaugh (1924– )
george Boole (1815–1864) In 1953, Karnaugh refined the Veitch diagram into the
Boole was a founder of the computer science field; he Karnaugh map method.
invented Boolean logic, which is the basis of modern
digital computer logic. gottfried Leibniz (1646–1716)
In 1679, Leibniz invented the binary system, of critical
gary Boone and michael J. Cochran importance in the development of modern computers.
In 1971, Boone and Cochran created the first
microcontroller, also referred to as a microcomputer. emanuel Swedenborg (1688–1772)
In 1718, Swedenborg wrote a manuscript on a new
William henry eccles (1875–1966) and frank arithmetic that changes at the number 8 instead of at
Wilfred Jordan (1882–?) the usual number 10.

In 1918, Eccles and Jordan invented the first electronic edward W. Veitch (1924– )
flip-flop, initially called the Eccles–Jordan trigger In 1952, Veitch developed a graphical procedure for
circuit. simplifying the optimization of logic circuits, referred
to as the Veitch diagram.
frank gray (1887–1969)
In 1947, Gray introduced the term reflected binary
code, which was later named Gray-to-Gray code by
others who used it.

385

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41C h a p t e r

Binary number System

oBJeCtiVeS Key termS

After completing this chapter, the student 41 bit 41-4 base 16
will be able to:
41-1 base 2 41-4 hexadecimal
■ Describe the binary number system. number system
41-1 base 10
■ Identify the place value for each bit in a binary 41-5 binary-coded
number. 41-1 binary number decimal (BCD)
system
■ Convert binary numbers to decimal, octal, and 41-5 8421 code
hexadecimal numbers. 41-3 base 8

■ Convert decimal, octal, and hexadecimal 41-3 octal numbers
numbers to binary numbers.
41-3 octal number
■ Convert decimal numbers to 8421 BCD code. system

■ Convert 8421 BCD code numbers to decimal
numbers.

386

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Binary Number System Chapter 41 387

Anumber system is nothing more than a code. ■ figure 41-1
For each distinct quantity, there is an assigned
symbol. When the code is learned, counting Decimal number and equivalent binary table.
can be accomplished. This leads to arithmetic and
higher forms of mathematics. Decimal Number Binary Number
24 23 22 21 20
The simplest number system is the binary number 0 16 8 4 2 1
system. The binary system contains only two digits, 0 1
and 1. These digits have the same value as in the deci- 2 0 00 0 0
mal number system. 3 0 00 0 1
4 0 00 1 0
The binary number system is used in digital and 5 0 00 1 1
microprocessor circuits because of its simplicity. Bi- 6 0 01 0 0
nary data are represented by binary digits, called bits. 7 0 01 0 1
The term bit is derived from binary digit. 8 0 01 1 0
9 0 01 1 1
  41–1  BinAry nuMBErs 10 0 10 0 0
11 0 10 0 1
The decimal system is called a base-10 system be- 12 0 10 1 0
cause it contains 10 digits, 0 through 9. The binary  13 0 10 1 1
number system is a base-2 system because it con- 14 0 11 0 0
tains two digits, 0 and 1. The position of the 0 or 1 in 15 0 11 0 1
a binary number indicates its value within the num- 16 0 11 1 0
ber. This is referred to as its place value or weight. The 17 0 11 1 1
place value of the digits in a binary number increases 18 1 00 0 0
by powers of two. 19 1 00 0 1
20 1 00 1 0
Powers of 2: Place Value 21 1 00 1 1
32 16 8 4 2 1 22 1 01 0 0
25 24 23 22 21 20 23 1 01 0 1
24 1 01 1 0
Counting in binary starts with the numbers 0 and 1. 25 1 01 1 1
When each digit has been used in the 1’s place, 26 1 10 0 0
another digit is added in the 2’s place and the count 27 1 10 0 1
continues with 10 and 11. This uses up all combina- 28 1 10 1 0
tions of two digits, so a third digit is added in the 4’s 29 1 10 1 1
place and the count continues with 100, 101, 110, and 30 1 11 0 0
111. Now a fourth digit is needed in the 8’s place to 31 1 11 0 1
continue, and so on. Figure 41-1 shows the binary 1 11 1 0
counting sequence. © 2014 Cengage Learning 1 11 1 1

To determine the largest value that can be repre- EXAMPLE:  Two bits (two place values) can be used to
sented by a given number of places in base 2, use the count from 0 to 3 because:
following formula:
2n 2 1 5 22 2 1 5 4 2 1 5 3
Highest number 5 2n 2 1 Four bits (four place values) are needed to count
from 0 to 15 because:
where n represents the number of bits (or number of
place values used). 2n 2 1 5 24 2 1 5 16 2 1 5 15

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388 SeCtion 6 DIgItAl ElECtronIC CIrCuIts

  41–1  QuEstions right of the decimal zero point. All digits to the right
of the zero point have weights that are negative powers
1. What is the advantage of the binary number of two, or fractional place values.

system over the decimal number system for Powers Place
of 2 Value
digital circuits?
2. Where are binary numbers used? 25 5 32
3. How is the largest value of a binary number de- 24 5 16
23 5 8
termined for a given number of place values? 22 5 4
4. What is the maximum value of a binary num- 21 5 2
20 5 1
ber with each of the following?
a. 4 bits decimal point
b. 8 bits
c. 12 bits 221 5 1 5 1 5 0.5
d. 16 bits 21 2
5. Write the following numbers in binary:
a. 310 222 5 1 5 1 5 0.25
b. 710 22 4
c. 1610
d. 3110 223 5 1 5 1 5 0.125
23 8

224 5 1 5 1 5 0.0625
24 16
BinAry And dEciMAL 
  41–2  convErsion EXAMPLE:  Determine the decimal value of the
binary number 111011.011.
As stated, a binary number is a weighted number with
a place value. The value of a binary number can be de- Binary Place Value
termined by adding the product of each digit and its Number Value
place value. The method for evaluating a binary num-
ber is shown by the following example: 1 3 32 5 32
1 3 16 5 16
1 38 58
EXAMPLE: 0 34 50
Binary: Place Value 1 32 52
32 16 8 4 2 1 1 31 51
1 0 1 10 1 0 3 0.5 5 0
1 3 0.25 5 0.25
Value: 1 3 32 5 32 1 1 3 0.125 5 0.125
0 3 16 5 0
138 58 111011.0112 5 59.37510
134 54
032 50 In working with digital equipment, it is often nec-
1131 51 essary to convert from binary to decimal form and
1011012 5 4510 vice versa. The most popular way to convert decimal
numbers to binary numbers is to progressively divide
The number 45 is the decimal equivalent of the binary the decimal number by 2, writing down the remainder
number 101101. after each division. The remainders, taken in reverse
order, form the binary number.
Fractional numbers can also be represented in bi-
nary form by placing digits to the right of the binary EprXoAgrMessPivLeEly: dTiovidceonbyve2r(tL1S1B105toleaastbsiinganrifyicnanutmbbite).r,
zero point, just as decimal numbers are placed to the

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Binary Number System Chapter 41 389

11 4 2 5 5 with a remainder of 1 LSB and
5 4 2 5 2 with a remainder of 1
2 4 2 5 1 with a remainder of 0 0.65 3 2 5 1.30 5 0.30 with a carry of 1 LSB
1 4 2 5 0 with a remainder of 1 0.30 3 2 5 0.60 5 0.60 with a carry of 0
(1 4 2 5 0 means that 2 will no longer divide into 1, 0.60 3 2 5 1.20 5 0.20 with a carry of 1
so 1 is the remainder.) Decimal 11 is equal to 1011 in 0.20 3 2 5 0.40 5 0.40 with a carry of 0
binary. 0.40 3 2 5 0.80 5 0.80 with a carry of 0
0.80 3 2 5 1.60 5 0.60 with a carry of 1
The process can be simplified by writing the num- 0.60 3 2 5 1.20 5 0.20 with a carry of 1
bers in an orderly fashion as shown here for convert-
ing 2510 to a binary number. Decimal 0.65 5 Binary 0.1010011

EXAMPLE: t1i0o1nC0,o0b.me1c0ba1iun0s0ien1tg1h2te.hTceohtniwsveo1r2sn-ibuoimnt nobufermthsbereefrrsauicslttaisoninnawp2pa0rs.o6tx5eir1mm0 5ai--
nated after 7 bits.
2 25 LSB

2 12 1

26 0

23 0

21 1   41–2  QuEstions

01

Decimal number 25 is equal to binary number 11001. 1. What is the value of each position in an 8-bit
Fractional numbers are done a little differently: The
binary number?
number is multiplied by 2 and the carry is recorded as 2. What is the value of each position to the right
the binary fraction.
of the decimal point for eight places?
EXAMPLE:  To convert decimal 0.85 to a binary frac- 3. Convert the following binary numbers to
tion, progressively multiply by 2.
decimal numbers:
LSB
0.85 3 2 5 1.70 5 0.70 with a carry of 1 a. 10012
0.70 3 2 5 1.40 5 0.40 with a carry of 1 b. 111011112
0.40 3 2 5 0.80 5 0.80 with a carry of 0 c. 110000102
0.80 3 2 5 1.60 5 0.60 with a carry of 1 d. 10101010.11012
0.60 3 2 5 1.20 5 0.20 with a carry of 1 e. 10110111.00012
0.20 3 2 5 0.40 5 0.40 with a carry of 0 4. What is the process for converting decimal

Continue to multiply by 2 until the needed accu- numbers to binary digits?
racy is reached. Decimal 0.85 is equal to 0.110110 in 5. Convert the following decimal numbers to
binary form.
binary form:
EXAMPLE:  Convert decimal 20.65 to a binary num- a. 2710
ber. Split 20.65 into an integer of 20 and a fraction of b. 34.610
0.65 and apply the methods previously shown. c. 34610
d. 321.45610
e. 746510

2 20 LSB

2 10 0

25 0   41–3  octAL nuMBErs
Years ago, computers used octal numbers for repre-
22 1 senting binary numbers. Using octal numbers allows
the reading of large binary numbers by breaking the
21 0

01

Decimal 20 5 Binary 10100

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

390 SeCtion 6 DIgItAl ElECtronIC CIrCuIts

■ figure 41-2 Convert to octal: 100 101 001 110 000 111 0102
4 5 1 6 0 7 28
Decimal and binary equivalent of octal numbers.

Decimal Number Binary Number Octal Number Octal ecqounivvearltenatniso:c4t5al16n0u7m2b8 er to a binary equivalent
To
0 requires reversing the process and converting the octal
1 00 000 0 number to binary groups of three, as shown by the
2 00 001 1 following example:
3 00 010 2
4 00 011 3 EXAMPLE:
5 00 100 4 CBLOSeeiocnpantadaavrrlezyanreteuetrqomttoushbiecbveaianrnnl:uea1bmnr6eytb7::de020rr000os151:p141p118e10d0161r1e11s01u71l00t1i0n200g00i10n000:111050102140802
6 00 101 5
7 00 110 6 11101110100001011002
00 111 7
8 Like binary numbers, each octal number is a
9 01 000 10 weighted number with a place value. The value of an
10 01 001 11 octal number can be determined by adding the prod-
11 01 010 12 uct of each digit and its place value. Figure 41-3 shows
12 01 011 13 octal place values. The method for converting an oc-
13 01 100 14 tal number to a decimal is shown by the following
14 01 101 15 example:
15 01 110 16
16 01 111 17 EXAMPLE
17 10 000 20 Octal number: 60728
18 10 001 21 Value: 6 3 512 5 3072
19 10 010 22
20 10 011 23 0 3 64 5 0
21 10 100 24 7 3 8 5 56
22 10 101 25 231 52
23 10 110 26 60728 5 313010
10 111 27
24
25 11 000 30
26 11 001 31
27 11 010 32
28 11 011 33
29 11 100 34
30 11 101 35
31 11 110 36
11 111 37
© 2014 Cengage Learning
To convert a decimal number to an octal equivalent
requires dividing the number by eight, as shown by
binary number into groups of three. This speeded up converting 238210 to an octal number in the following
the entering and reading of binary numbers from a example:
computer, thus resulting in reduced error.
■ figure 41-3
Figure 41-2 shows octal numbers with their deci-
mal and binary equivalents. The advantage is that octal Place values of octal numbers.
numbers are converted directly from 3 bits of binary
numbers. The octal number system is referred to Powers of 8 Place Value
as base 8. There are only eight digits (0–7) and then
it recycles like the decimal system (0–9). 80 1
81 8
To convert binary to an octal number requires 82 64
dividing the binary number into groups of three, 83 512
starting from the right, as shown by the following 84 4096
example: 85 32768
EXAMPLE: 86 262144
BSeinpaarryatneuinmtobegrro1u00p1s0o1f0t0h1r1ee1:00001110102 87 2097152
100 101 001 110 000 111 0102
© 2014 Cengage Learning

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Binary Number System Chapter 41 391

EXAMPLE ■ figure 41-4

Decimal number: 23w82it1h0 Decimal and binary equivalent of hexadecimal numbers.
2832 ÷ 8 5 354
354÷ 8 5 44 remainder of 0 (LSB) Hexadecimal
with remainder of 2 Number
44 ÷ 8 5 5 with remainder of 4 Decimal Number Binary Number
5 ÷ 8 5 will not divide, therefore yields 5 (most 0
significant 0 0 0000 1
Resulting in 238210 5 54208 bit [MSB]) 1 0 0001 2
2 0 0010 3
  41–3  QuEstions 3 0 0011 4
4 0 0100 5
1. Why are octal numbers used with computers? 5 0 0101 6
2. Convert the following binary numbers to octal 6 0 0110 7
7 0 0111
numbers: 8
8 0 1000 9
a. 1010111111100100010002 9 0 1001 A
b. 11110110100001101012 10 0 1010 B
c. 100111001110001010012 11 0 1011 C
12 0 1100 D
3. Convert the following octal numbers to binary 13 0 1101 E
14 0 1110 F
numbers: 15 0 1111 10
16 1 0000 11
a. 756342018 17 1 0001 12
b. 364251078 18 1 0010 13
c. 175364208 19 1 0011 14
20 1 0100 15
4. Convert the following octal numbers to decimal 21 1 0101 16
22 1 0110 17
numbers: 23 1 0111
18
a. 6538 24 1 1000 19
b. 47218 25 1 1001 1A
c. 753648 26 1 1010 1B
27 1 1011 1C
5. 28 1 1100 1D
29 1 1101 1E
30 1 1110 1F
31 1 1111

Convert the following decimal numbers to octal © 2014 Cengage Learning

numbers:

a. 45310 hexadecimal numbers with their decimal and binary
b. 102810 equivalents. The advantage of hexadecimal num-
c. 3204710 bers is that they are converted directly from 4 bits of
binary numbers.
  41–4  HEXAdEciMAL nuMBErs
The hexadecimal number system is used pri- To convert binary to a hexadecimal number
marily for entering and reading data of microproces- requires dividing the binary number into groups of
sor-based 4-, 8-, 16-, 32-, and 64-bit systems. Using four, starting from the right, as shown by the following
hexadecimal numbers allows the breaking of a binary example:
number into groups of four to reduce chance of error EXAMPLE:
when entering data. SBeinpaarryatneuinmtobegrro1u0p0s1o0f10fo0u1r1:100001110102
C1 o0n01v0er1t0to01h1e1xa0d0e0c0im11a1l:0102
The hexadecimal number system is referred H11 0ex02a1d0e1c0i9m01al1e1Cq0u0i0v0a6l1e1n1t 0Ais1110622 9C6A16
to as base 16. There are 16 digits: 0, 1, 2, 3, 4, 5,
6, 7, 8, 9, A, B, C, D, E, and F. Figure 41-4 shows

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

392 SeCtion 6 DIgItAl ElECtronIC CIrCuIts

To convert a hexadecimal number to a binary sthheowfonllobwyincognevxearmtipnlge:4192910 to an octal number in
equivalent requires reversing the process and convert-
ing the hexadecimal number to binary groups of four, EXAMPLE:
as shown by the following example: Decimal number: 4192910

EXAMPLE: 41929 ÷ 16 5 2620 with remainder of 9 (LSB)
Hexadecimal number: 6A67FA4D27C16F 12 (C)
Separate the numbers: 4 D 2 C16 2620 ÷ 16 5 163 with remainder of 3
163 ÷16 5 10 with remainder of
Convert to binary: 10 ÷ 16 5 will not divide, therefore yields
0011 1010 0111 1111 0100 1101 0010 11002
Binary equivalent: 10 (A) (MSB)
Resulting in 4192910 5 A3C916
L00e1ad11z0e1r0o0s1c1a1n1b1e11d0r1o0p0p1e1d0, 1re0s0u1l0ti1n1g0i0n2:

1110100111111101001101001011002   41–4  QuEstions

Like binary numbers, each hexadecimal number is 1. Why are hexadecimal numbers used with
a weighted number with a place value. The value of a
hexadecimal number can be determined by adding the computers?
product of each digit and its place value. Figure 41-5 2. Convert the following binary numbers to
shows hexadecimal place values. The method for con-
verting a hexadecimal number to a decimal is shown hexadecimal numbers:
by the following example:
a. 1010111111100100010002
b. 11110110100001101012
c. 100111001110001011012

EXAMPLE: 3. Convert the following hexadecimal numbers
Hexadecimal number: 4AC916
Value: 4 3 4096 5 16384 to binary numbers:

110 2 A 3 256 5 2560 a. 42C116
112 2 C 3 16 5 192 b. 5B0716
c. A75C642E16
931 59 4. Convert the following hexadecimal numbers
4AC916 5 1914510
To convert a decimal number to a hexadecimal to decimal numbers:
equivalent requires dividing the number by 16 as
a. 6E5316
b. A7C116
c. 7F3BE16
5. Convert the following decimal numbers

■ figure 41-5 to hexadecimal numbers:
a. 4537410
Place values of hexadecimal numbers. b. 3204710
c. 6732610

Powers of 16 Place Value   41–5  Bcd codE

160 1 An 8421 code is a binary-coded decimal (Bcd)
161 16 code consisting of four binary digits. It is used to repre-
162 256 sent the digits 0 through 9. The 8421 designation refers
163 4096 to the binary weight of the 4 bits.
164 65536
165 1048576
166 16777216
167 268435456

© 2014 Cengage Learning Powers of 2: 23 22 21 20

Binary weight: 8 4 2 1

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Binary Number System Chapter 41 393

The main advantage of this code is that it permits   41–5  QuEstions
easy conversion between decimal and binary form.
This is the predominant BCD code used and is the one 1. What is the 8421 code and how is it used?
referred to unless otherwise stated. 2. What is the advantage of BCD code?
3. What are the similarities between BCD code
Each decimal digit (0 through 9) is represented by a
binary combination as follows:

Decimal 8421 Code and the hexadecimal number system?
0 0000 4. Convert the following decimal numbers into
1 0001
2 0010 BCD code:
3 0011
4 0100 a. 1710
5 0101 b. 10010
6 0110 c. 25610
7 0111 d. 77810
8 1000 e. 857310
9 1001 5. Convert the following BCD codes into decimal

Although 16 numbers (24) can be represented by numbers:
four binary positions, the six code combinations above a. 1000 0010BCD
decimal 9 (1010, 1011, 1100, 1101, 1110, and 1111) are b. 0111 0000 0101BCD
invalid in the 8421 code. c. 1001 0001 0011 0100BCD
d. 0001 0000 0000 0000BCD
To express any decimal number in the 8421 code, e. 0100 0110 1000 1001BCD
replace each decimal digit by the appropriate 4-bit
code.     suMMAry
● The binary number system is the simplest number
EXAMPLE:  Convert the following decimal numbers
into a BCD code: 5, 13, 124, 576, and 8769. system.
● The binary number system contains two digits,
87156271594631111100000 5 01000101000000010111B0000C1100D11111101B000C111D101000BB1CC0DD01BCD
5 0 and 1.
5 ● The binary number system is used to represent
5
5 data for digital and computer systems.
● Binary data are represented by binary digits called bits.
To determine a decimal number from an 8421 code ● The term bit is derived from binary digit.
number, break the code into groups of 4 bits. Then ● The place value of each higher digit’s position in a
write the decimal digit represented by each 4-bit group.
binary number is increased by a power of 2.
EXAMPLE:  Find the decimal equivalent for each ● The largest value that can be represented by a
of the following BCD codes: 10010101, 1001000,
1100111, 1001100101001, and 1001100001110110. given number of places in base 2 is 2n 21, where n
represents the number of bits.
0001 0011 1001 10010011010010111001BBBBBCCCCCDDDDD 5 199643588721711000961100 ● The value of a binary digit can be determined by
1001 1000 0100 5 adding the product of each digit and its place value.
0110 5 ● Fractional numbers are represented by negative
0010 5 powers of 2.
0111 5 ● To convert from a decimal number to a binary num-
ber, divide the decimal number by 2, writing down
the remainder after each division. The remainders,
taken in reverse order, form the binary number.
● Octal numbers allow reading large binary numbers
by breaking the binary number into groups of three.

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

394 SeCtion 6 DIgItAl ElECtronIC CIrCuIts

● The octal number system is referred to as base 8. ● The hexadecimal number system is used with
● Similar steps are used to convert octal numbers to microprocessor-based systems.

decimal and decimal numbers to octal as with the ● As with octal and binary number systems, the
binary number system. hexadecimal number system uses similar steps for
● The hexadecimal number system breaks binary converting to and from decimal numbers.
numbers into groups of four to reduce error when
entering data. ● The 8421 code, a binary-coded decimal (BCD)
● The hexadecimal number system is a base-16 code, is used to represent digits 0 through 9.
system.
● The advantage of the BCD code is ease of convert-
ing between decimal and binary forms of a number.

Chapter 41 SeLf-teSt

1. What represents the decimal equivalent of 0 9. Convert the following binary numbers to

through 27 in binary? hexadecimal numbers:
2. How many binary bits are required to repre-
a. 110010010111001010100111000011012
sent the decimal number 100? b. 001100011011111001001111001101002
3. Describe the process for converting a decimal c. 100110101100010011001111010001102

number to a binary number. 10. Convert the following hexadecimal numbers to
4. Convert the following binary numbers to their
binary numbers:

decimal equivalents: a. 7B23C67F16
b. D46F17C916
a. 100101.0010112 c. 78F3E69D16
b. 111101110.111011102
c. 1000001.000001012 11. Convert the following hexadecimal numbers to

5. Convert the following binary numbers to octal decimal numbers:

numbers: a. 3C67F16
b. 6F17C916
a. 110010010111001010100111000011012 c. 78F3E69D16
b. 001100011011111001001111001101002
c. 100110101100010011001111010001102 12. Convert the following decimal numbers to

6. Convert the following octal numbers to binary hexadecimal numbers:

numbers: a. 68710
b. 976210
a. 6531728 c. 1867310
b. 7730128
c. 0332578 13. Describe the process for converting decimal

7. Convert the following octal numbers to decimal numbers to BCD.
14. Convert the following BCD numbers to their
numbers:

a. 3172048 decimal equivalents:
b. 7012538 a. 0100 0001 0000 0110BCD
c. 0357168 b. 1001 0010 0100 0011BCD
c. 0101 0110 0111 1000BCD
8. Convert the following decimal numbers to octal

numbers:

a. 68710
b. 976210
c. 1867310

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

42C H A P T E R

Basic Logic Gates

OBjECTivEs KEy TERms 42-4 NAND gate

After completing this chapter, the student 42-1 AND function 42-5 NOR gate
will be able to: 42-1 AND gate
42-1 truth table 42-6 exclusive OR
■ Identify and explain the function of the basic 42-2 OR function gate (XOR)
logic gates. 42-2 OR gate
42-3 high 42-6 XNOR
■ Draw the symbols for the basic logic gates. 42-3 low (exclusive NOR)
■ Develop truth tables for the basic logic gates. 42-3 NOT gate gate

42-7 buffer

42-7 three-state buffer

395

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396 sECTiON 6 DIgITAl ElEcTRONIc cIRcuITs

All digital equipment, whether simple or com- inputs are designated A and B. The output is desig-
plex, is constructed of only a few basic circuits. nated Y. The total number of possible combinations in
These circuits, referred to as logic elements, the truth table is determined by the following formula:
perform some logic function on binary data.
N 5 2n
There are two basic types of logic circuits: decision- where:
making and memory. Decision-making logic circuits
monitor binary inputs and produce an output based N 5 the total number of possible combinations
on the status of the inputs and the characteristics of n 5 the total number of input variables
the logic circuit. Memory circuits are used to store bi-
nary data. EXAMPLE: N 5 22 5 4
For two input variables, N 5 23 5 8
42–1 AND GAtE For three input variables, N 5 24 5 16
The AND gate is a logic circuit that has two or more For four input variables, N 5 28 5 256
inputs and a single output. The AND gate produces an For eight input variables,
output of 1, only when all its inputs are 1s. If any of the
inputs are 0s, the output is 0. The AND gate uses the rules of multiplication. The
AND function is known for multiplication-like results.
Figure 42-1 shows the standard symbol used for The output of an AND gate is represented by the equa-
AND gates. An AND gate can have any number of in- tion Y 5 A·B or Y 5 AB. The AND function is typically
puts greater than one. Shown in the figure are symbols represented by the two variables A and B as AB.
representing the more commonly used gates of two,
three, four, and eight inputs. 42–1 QuEstioNs

The operation of the AND gate is summarized by 1. under what conditions does an AND gate
the table in Figure 42-2. Such a table, called a truth produce a 1 output?
table, shows the output for each possible input. The
2. Draw the symbol used to represent a two-input
■ FiGuRE 42-1 AND gate.

logic symbol for an AND gate. 3. Develop a truth table for a three-input AND
gate.
A Y 5 AB A Y 5 ABC
4. What logical operation is performed by an
B B Y5 AND gate?
C ABCDEFGH
5. What is the algebraic output of an AND gate?

A © 2014 Cengage Learning
B
C
D
A Y5 E 42–2 oR GAtE
B ABCD F An oR gate produces a 1 output if any of its inputs
C G are 1s. The output is a 0 if all the inputs are 0s. The
D H output of a two-input OR gate is shown in the truth
table in Figure 42-3. The total number of possible
■ FiGuRE 42-2 combinations is expressed by N 5 22 5 4. The truth
table shows all four combinations.
Truth table for a two-input AND gate.
An OR gate performs the basic operation of addi-
Inputs Output tion. The algebraic expression for the output of an OR
BA Y gate is Y 5 A 1 B. The plus sign designates the oR
00 0 function.
01 0
10 0 Figure 42-4 shows the logic symbol for an OR
11 1 gate. The inputs are labeled A and B, and the output is

© 2014 Cengage Learning

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Basic Logic Gates CHAPTER 42 397

■ FiGuRE 42-3 The purpose of the inverter is to make the output
state the opposite of the input state. The two states as-
Truth table for a two-input OR gate. sociated with logic circuits are 1 and 0. A 1 state can
also be referred to as a high, to indicate that the volt-
Inputs A Output age is higher than in the 0 state. A 0 state can also be
B 0 Y referred to as a low, to indicate that the voltage is
0 1 0 lower than in the 1 state. If a 1, or high, is applied to
0 0 1 the input of an inverter, a 0, or low appears on its out-
1 1 1 put. If a 0, or low, is applied to the input, a 1, or high,
1 1 appears on its output.

© 2014 Cengage Learning Y5 The operation of an inverter is summarized in
A1B1C Figure 42-5. The input to an inverter is labeled A and
■ FiGuRE 42-4 the Y output is labeled A (read “A NOT” or “NOT A”).
Y5 The bar over the letter A indicates the complement of
logic symbol for an OR gate. A1B1C1D1 A. Because the inverter has only one input, only two
E1F1G1H input combinations are possible.
A Y5 A
B A1B B The symbol used to represent an inverter or NOT
C function is shown in Figure 42-6. The triangle portion
of the symbol represents the circuit, and the circle, or
A “bubble,” represents the circuit inversion, or comple-
mentary characteristic. The choice of symbol depends
AB © 2014 Cengage Learning on where the inverter is used. If the inverter uses a 1
C as the qualifying input, the symbol in Figure 42-6A is
used. If the inverter uses a 0 as the qualifying input,
B Y5 D the symbol in Figure 42-6B is used.

C A1B1C1D E
F

DG

H

labeled Y. An OR gate can have any number of inputs ■ FiGuRE 42-5
greater than one. Shown in the figure are OR gates
with two, three, four, and eight inputs. Truth table for an inverter.

42–2 QuEstioNs Inputs Output
A Y
1. What conditions produce a 1 output for an 0 1
OR gate? 1 0

2. Draw the symbol used to represent a two-input © 2014 Cengage Learning Y50
OR gate.
■ FiGuRE 42-6
3. Develop a truth table for a three-input OR gate.
4. What operation is performed by an OR gate? logic symbol for an inverter.
5. What algebraic expression represents the
A51
output of an OR gate?

42–3 Not GAtE A50 (A) © 2014 Cengage Learning
The simplest logic circuit is the Not gate. It per- Y51
forms the function called inversion, or complementa-
tion, and is commonly referred to as an inverter. (B)

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398 sECTiON 6 DIgITAl ElEcTRONIc cIRcuITs

42–3 QuEstioNs is the complement of the output of an AND gate. Any
0 in the input yields a 1 output.
1. What operation is performed by a NOT circuit?
2. Develop a truth table for the NOT circuit. The algebraic formula for NAND-gate output is
3. Draw the symbols used to represent the NOT circuit. Y 5 AB, where Y is the output and A and B are the
4. Why are two different symbols used to inputs. NAND gates are available with two, three, four,
eight, and thirteen inputs.
represent the NOT circuit?
5. What is the algebraic sum of a NOT gate? NAND gates are the most widely available gates
on the market. The availability and flexibility of the
NAND gate allows it to be used for other types of
gates. Figure 42-9 shows how a two-input NAND gate
can be used to generate other logic functions.

42–4 NAND GAtE 42–4 QuEstioNs

A NAND gate is a combination of an inverter and 1. What is a NAND gate?
an AND gate. It is called a NAND gate from the NOT- 2. Why is the NAND gate so often used in
AND function it performs. The NAND gate is the
most commonly used logic function. This is because circuits?
it can be used to construct an AND gate, OR gate, 3. Draw the logic symbol used to represent a
inverter, or any combination of these functions.
NAND gate.
The logic symbol for a NAND gate is shown in 4. What is the algebraic expression for a
Figure 42-7. Also shown is its equivalency to an AND
gate and an inverter. The bubble on the output end of NAND gate?
the symbol means to invert the AND function. 5. Develop a truth table for a three-input

Figure 42-8 shows the truth table for a two-input NAND gate.
NAND gate. Notice that the output of the NAND gate
■ FiGuRE 42-7 42–5 NoR GAtE

logic symbol for a NAND gate. A NoR gate is a combination of an inverter and an
A Y 5 AB OR gate. Its name derives from its NOT-OR func-
B tion. Like the NAND gate, the NOR gate can also be
used to construct an AND gate, an OR gate, and an
A AB Y 5 AB © 2014 Cengage Learning inverter.
B
The logic symbol for the NOR gate is shown in
■ FiGuRE 42-8 Figure 42-10. Also shown is its equivalency to an OR
gate and an inverter. The bubble on the output of the
Truth table for a two-input NAND gate. symbol means to invert the OR function.

Inputs Output Figure 42-11 shows the truth table for a two-input
BA Y NOR gate. Notice that the output is the complement
00 1 of the OR-function output. A 1 occurs only when
01 1 0 is applied to both inputs. A 1 input produces a
10 1 0 output.
11 0
The algebraic expression for NOR-gate output is
© 2014 Cengage Learning Y 5 A 1 B, where Y is the output, and A and B are the
inputs. NOR gates are available with two, three, four,
and eight inputs.

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Basic Logic Gates CHAPTER 42 399

■ FiGuRE 42-9

using the NAND gate to generate other logic functions.

Logic Logic Symbol Logic Functions Using Only NAND Gates
Inverter AA AA

AND A A AB
B AB B A1B

A A1B A
OR B B

NOR A A1B A A1B
B B

XOR A AB A AB
B B

XNOR A AB A AB
B B

© 2014 Cengage Learning ■ FiGuRE 42-11

■ FiGuRE 42-10 Truth table for a two-input NOR gate.

logic symbol for a NOR gate. Y 5 A1B © 2014 Cengage Learning Inputs Output
A Y 5 A1B BA Y
B 00 1
01 0
A A1B 10 0
B 11 0

© 2014 Cengage Learning

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

400 sECTiON 6 DIgITAl ElEcTRONIc cIRcuITs

42–5 QuEstioNs ■ FiGuRE 42-14 Y5A B

1. What is a NOR gate? logic symbol for an exclusive NOR gate.
2. Why is the NOR gate useful in designing
© 2014 Cengage Learning
digital circuits?
3. Draw the symbol used to represent a NOR gate. A
4. What is the algebraic expression for a NOR gate?
5. Develop a truth table for a three-input NOR gate. B

42–6 EXcLusivE oR AND NoR GAtEs ■ FiGuRE 42-15

A less common but still important gate is called an Truth table for an exclusive NOR gate.
exclusive oR gate, abbreviated as XoR. An XOR
gate has only two inputs, unlike the OR gate, which Inputs Output
may have several inputs. However, the XOR is similar BA Y
to the OR gate in that it generates a 1 output if either 00 1
input is a 1. The exclusive OR is different when both 01 0
inputs are 1s or 0s. In that case, the output is a 0. 10 0
11 1
The symbol for an XOR gate is shown in Fig-
ure 42-12. Also shown is the equivalent logic circuit. © 2014 Cengage Learning
Figure 42-13 shows the truth table for an XOR gate.
The algebraic output is written as Y 5 A!B. It is read The complement of the XOR gate is the XNoR
as “Y equals A exclusive or B.” (exclusive NoR) gate. Its symbol is shown in
Figure 42-14. The bubble on the output implies inver-
sion or complement.

Also shown is the equivalent logic circuit. Fig-
ure 42-15 shows the truth table for an XNOR gate. The
algebraic output is written as Y 5 A!B, read as “Y
equals A exclusive nor B.”

■ FiGuRE 42-12 Y5A B 42–6 QuEstioNs

logic symbol for an exclusive OR gate. 1. What is the difference between an OR gate
and an XOR gate?
© 2014 Cengage Learning
2. Draw the symbol used to represent an XOR gate.
A 3. Develop a truth table for an XOR gate.
4. Draw the symbol used to represent an XNOR gate.
B 5. Write the algebraic expressions for XOR and

■ FiGuRE 42-13 XNOR gates.

Truth table for an exclusive OR gate. 42–7 BuffER

Inputs Output A buffer is a special logic gate that isolates con-
BA Y ventional gates from other circuitry and provides a
00 0 high driving current for heavy circuit loads or fan-
01 1 out. Fan-out refers to the number of input gates
10 1
11 0

© 2014 Cengage Learning

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Basic Logic Gates CHAPTER 42 401

connected to a single logic gate output. Buffers pro- ■ FiGuRE 42-18 Y50
vide noninverting input and output. A 1 in provides a Y51
1 out and a 0 in provides a 0 out. Figure 42-16 shows How a three-state buffer functions.
the schematic symbol for a basic buffer with its truth
table. A50

Another type of buffer is the three-state buffer Standard logic EN 5 0
shown with its truth table in Figure 42-17. The three- operation
state buffer has the usual 1 and 0 output states but it
also has a third state, which is referred to as a high- A51
impedance state. This state provides an open circuit
between the input circuitry and the output and is
controlled by the EN line. The EN line represents an
enable/disable control input. Figure 42-18 shows how
the three-state buffer operates.

■ FiGuRE 42-16

logic symbol for a buffer and truth table.

A Y Standard logic EN 5 0
operation

Input Output A 5 0 or 1 Y 5 No output

A Y © 2014 Cengage Learning
0 0
1 1

© 2014 Cengage Learning

High impedance EN 5 1
state
■ FiGuRE 42-17

logic symbol for a three-state buffer and
truth table.

AY

EN 42–7 QuEstioNs

Input Output 1. How does a buffer differ from an inverter?
2. What function does a buffer serve?
A Y 3. Draw the symbols for a buffer and a three-state
0 or 1 0 or 1
0 or 1 No output buffer.
4. Develop a truth table for a three-state buffer.
© 2014 Cengage Learning 5. What conditions must exist for no output from a

three-state buffer?

EN
0
1

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

402 sECTiON 6 DIgITAl ElEcTRONIc cIRcuITs

suMMARy ● A NAND gate produces 1 output when any of the
● An AND gate produces a 1 output when all of its inputs are 0s.

inputs are 1s. ● A NOR gate is a combination of an OR gate and an
● An AND gate performs the basic operation of inverter.

multiplication. ● A NOR gate produces a 1 output only when both
● An OR gate produces a 1 output if any of its inputs inputs are 0s.

are 1s. ● An exclusive OR (XOR) gate produces a 1 output
● An OR gate performs the basic operation of addition. only if both inputs are different.
● A NOT gate performs the function called inversion
● An exclusive NOR (XNOR) gate produces a
or complementation. 1 output only when both inputs are the same.
● A NOT gate converts the input state to an opposite
● A buffer isolates conventional gates from other
output state. circuitry.
● A NAND gate is a combination of an AND gate
● A buffer provides a high current for heavy loads or
and an inverter. fan-outs.

● A three-state buffer has a high-impedance third
state.

CHAPTER 42 sELF-TEsT

1. Draw the schematic symbol for a six-input 8. Develop the truth table for a four-input

AND gate. NAND gate.
2. Develop the truth table for a four-input AND gate. 9. Draw the schematic symbol for an eight-input
3. Draw the schematic symbol for a six-input
NOR gate.
OR gate. 10. Develop the truth table for a four-input NOR gate.
4. Develop the truth table for a four-input OR gate. 11. What is the significance of the XOR gate?
5. What is the purpose for the NOT circuit? 12. The XNOR gate has what maximum number of
6. How does an inverter for an input signal differ
inputs?
from the inverter for an output signal? 13. Draw the schematic symbol for a buffer.
7. Draw the schematic symbol for an eight-input 14. What purpose does the buffer serve?
15. Draw the schematic symbol for a three-state buffer.
NAND gate.

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

43C H A P T E R

Simplifying Logic Circuits

ObjECTivES KEy TERmS

After completing this chapter, the student will be 43 Boolean 43-1 Veitch diagram
able to: algebra 43-2 Karnaugh map

■ Explain the function of Veitch diagrams. 43 Boolean
expression
■ Describe how to use a Veitch diagram to
simplify Boolean expressions.

■ Explain the function of a Karnaugh map.

■ Describe how to simplify a Boolean expression
using a Karnaugh map.

403

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

404 SECTiON 6 DigitAl ElEctronic circuits

Digital circuits are being used more and more in E X A M P L E :   Reduce AB 1 AB 1 AB 5 Y to its
electronics, not only in computers but also in simplest form.
applications such as measurement, automatic
control, robotics, and in situations requiring decisions. Step 1. Draw the Veitch diagram. There are two
All of these applications require complex switching variables, A and B, so use the two-variable chart.
circuits that are formed from the five basic logic gates:
the AND, OR, NAND, and NOR gates and the inverter. AA

The significant point about these logic gates is that B
they only have two operating conditions. They are
either ON (1) or OFF (0). When logic gates are inter- B © 2014 Cengage Learning
connected to form more complex circuits, it is neces-
sary to obtain the simplest circuit possible. Step 2. Plot the logic function by placing an X in
each square representing a term.
Boolean  algebra offers a means of express-
ing complex switching functions in equation form. A AB 1 AB 1 AB
Boolean expression is an equation that expresses 1st 2nd 3rd
the output of a logic circuit in terms of its input. Veitch term term term
diagrams and Karnaugh maps provide a fast and easy
way to reduce a logic equation to its simplest form. Plot 1st term AB.

  43–1  VEitch DiAgrAMs A A
Veitch diagrams provide a fast and easy method for
reducing a complicated expression to its simplest form. B
They can be constructed for one, two, three, or four
variables. Figure 43-1 shows several Veitch diagrams. B © 2014 Cengage Learning

To use a Veitch diagram, follow these steps, as Plot 2nd term AB. A
illustrated in the example:
1. Draw the diagram based on the number of variables. A
2. Plot the logic functions by placing an X in each B

square representing a term. B © 2014 Cengage Learning
3. Obtain the simplified logic function by looping

adjacent groups of X’s in groups of eight, four,
two, or one. Continue to loop until all X’s are
included in a loop.
4. “OR” the loops with one term per loop. (Each ex-
pression is pulled off the Veitch diagram and “OR”ed
using the 1 symbol, for example, ABC 1 BCD.)
5. Write the simplified expression.

■ FiguRE 43-1 A A A A
B D
two-, three-, and four-variable Veitch diagrams.

AA

BB

D © 2014 Cengage Learning

BB B
C
CC C C D
C

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Simplifying Logic Circuits CHAPTER 43 405

Plot 3rd term AB. A EXAMPLE:  Find the simplified expression for
ABC 1 ABC 1 ABC 1 ABC 5 Y
A
B Step 1. Draw a three-variable Veitch diagram.

B © 2014 Cengage Learning AA

B

B © 2014 Cengage Learning

Step 3. Loop adjacent groups of X’s in the largest CC C
group possible. Start by analyzing the chart for the
largest groups possible. The largest group possible Step 2. Place an X for each term on the Veitch
here is two. diagram.

AA AA

BB

B © 2014 Cengage Learning B © 2014 Cengage Learning

One possible group is the one indicated by the dotted CC C
line.
Step 3. Loop the groups.
AA
B AA

B B

Another group is the one indicated by this dotted© 2014 Cengage LearningB © 2014 Cengage Learning
line.
CC C
AA
B © 2014 Cengage Learning Step 4. Write the term for each loop, one term per
expression:
B
AB, BC .
Step 4. “OR” the groups: Either A or B 5 A 1 B. Step 5. The simplified expression is: AB 1 BC 5 Y.
Step 5. The simplified expression for AB 1 AB 1 Notice the unusual looping on the two bottom
AB 5 Y is A 1 B 5 Y obtained from the Veitch squares. The four corners of the Veitch diagram are
diagram. considered connected as if the diagram were formed
into a ball.

EXAMPLE:  Find the simplified expression for
ABCD 1 ABCD 1 ABCD 1 ABCD 1
ABCD 1 ABCD 5 Y

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

406 SECTiON 6 DigitAl ElEctronic circuits

Step 1. Draw a four-variable Veitch diagram.   43–2  KArnAugh MAPs
Another technique for reducing complex Boolean
A A expressions is Karnaugh  maps, which Maurice
B D Karnaugh developed in 1953. His technique is similar
to using Veitch diagrams. Figure 43-2 shows several
B C D © 2014 Cengage Learning Karnaugh maps. It can be cumbersome to solve prob-
C lems with five or six variables with either Veitch dia-
D grams or Karnaugh maps. Those types of problems are
C best solved by other techniques or computer software
designed specifically for them.
Step 2. Place an X for each term on the Veitch
diagram.

A A ■ FiguRE 43-2
B D
two-, three-, and four-variable Karnaugh maps.
D © 2014 Cengage Learning BB

B A

CC C D A

Step 3. Loop the groups. D
D
AA

B

© 2014 Cengage Learning C C
AB
B C D AB
C C AB

Step 4. Write the term for each loop, one term per
expression: AD, ABC.

Step 5. “OR” the terms to form the simplified
expression: AD 1 ABC 5 Y.

  43–1  QuEstions AB © 2014 Cengage Learning

1. What is the function of a Veitch diagram? CD CD CD CD
2. How many variables can be represented on a AB
AB
Veitch diagram? AB
3. list the steps for using a Veitch diagram. AB
4. simplify the following three-variable

expressions using Veitch diagrams:
a. ABc 1 ABc 1 ABc 1 ABc 1 ABc 5 Y
b. ABc 1 ABc 1 ABc 1 ABc 1 AB1 ABc 5 Y
5. simplify the following four-variable expressions

using Veitch diagrams:
a. ABcD 1 ABcD 1 ABcD 1 ABcD 1

ABcD 1 ABcD 1 ABcD 5 Y
b. AB 1 ABD 1 BcD 1 Bc 1 ABcD 5 Y

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Simplifying Logic Circuits CHAPTER 43 407

To use a Karnaugh map, follow these steps: Plot 3rd term AB. B B
1. Draw the diagram based on the number of 1
A © 2014 Cengage Learning
variables. As Figure 43-2 shows, a two-variable 1
map requires 22 5 4 squares, a three-variable map A1
requires 23 5 8 squares, and a four-variable map
requires 24 5 16 squares—the same requirements Step 3. Loop adjacent groups of 1s in the largest© 2014 Cengage Learning
as a Veitch diagram. group possible. Start by analyzing the map for the larg-
2. Plot the logic functions by placing a “1” in each est groups possible. The largest group here is two.
square representing a term.
3. Obtain the simplified logic function by looping BB
adjacent groups of 1s in groups of eight, four, A1
or two. Continue to loop until all 1s are included.
4. “OR” the loops with one term per loop. (Each A1 1
expression is pulled off the Karnaugh map and
“OR”ed using the “1 ” symbol, for example,© 2014 Cengage LearningOne possible group is the one indicated by the dotted
ABC 1 BCD.) line.
5. Write the simplified expression.
EXAMPLE:  Reduce AB 1 AB 1 AB 5 Y to its sim- BB
plest form. A1
Step 1. Draw the Karnaugh map. There are two
variables, A and B, so use the two-variable map.

BB

A

A © 2014 Cengage Learning

A1 1

Step 2. Plot the logic function by placing a “1” in Another group is the one indicated by this dotted line.© 2014 Cengage Learning
each square representing a term.
BB
AB 2 first term A1
AB 2 second term
AB 2 third term

Plot 1st term AB.

B B A1 1

A 1 © 2014 Cengage Learning Step 4. “OR” the groups: either A or B 5 A 1 B.
Step 5. The simplified expression for AB 1
A B AB 1 AB 5 Y is A 1 B 5 Y obtained from the
1 Karnaugh map.
Plot 2nd term AB.
EXAMPLE:  Find the simplified expression for
B ABC 1 ABC 1 ABC 1 ABC 5 Y
A
© 2014 Cengage Learning
A1

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

408 SECTiON 6 DigitAl ElEctronic circuits

Step 1. Draw the Karnaugh map. There are three EXAMPLE:  Find the simplified expression for ABCD 1
variables, A, B, and C, so use the three-variable map. ABCD 1 ABCD 1 ABCD 1 ABCD 1 ABCD 5 Y

CC Step 1. Draw the Karnaugh map. There are four
AB variables, A, B, C, and D, so use the four-variable
map.
AB
CD CD CD CD
AB

AB AB © 2014 Cengage Learning

AB AB © 2014 Cengage Learning

Step 2. Place a “1” in each square representing a AB
term on the map.
Step 2. Place a “1” in each square representing a
CC term on the map.
AB 1
CD CD CD CD
AB AB 1 1

AB 1 1 © 2014 Cengage Learning AB 1 1

AB 1 AB © 2014 Cengage Learning

Step 3. Loop adjacent groups of 1s in the largest AB 1 1
group possible.
Step 3. Loop adjacent groups of 1s in the largest
CC group possible.

AB 1 CD CD CD CD
AB 1 1
AB

AB 1 1 © 2014 Cengage Learning

AB 1 1

AB 1 AB © 2014 Cengage Learning

Step 4. Write the term for each loop, one term per AB 1 1
expression:

AB, BC .
Step 5. The simplified expression is: AB 1 BC 5 Y.

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Simplifying Logic Circuits CHAPTER 43 409

Step 4. Write the term for each loop, one term per     suMMAry
expression: AD, ABC. ● Veitch diagrams provide a fast and easy way to

Step 5. The simplified expression is: AD 1 ABC 5 Y. reduce complicated expressions to their simplest
form.
  43–2  QuEstions ● Veitch diagrams can be constructed from two,
three, or four variables.
1. What is the function of a Karnaugh map? ● The simplest logic expression is obtained from a
2. What is the maximum number of variables that Veitch diagram by looping groups of one, two, four,
or eight X’s and “OR”ing the looped terms.
can be represented with a Karnaugh map? ● Like Veitch diagrams, Karnaugh maps provide a
3. list the steps for using a Karnaugh map. fast and easy method to reduce complex Boolean
4. simplify the following three-variable expressions to their simplest form.
● Karnaugh maps can be constructed for two, three,
expressions using Karnaugh maps: or four variables.
a. ABc 1 ABc 1 ABc 1 ABc 1 ABc 5 Y ● The simplest logic expression is obtained from a
b. ABc 1 ABc 1 ABc 1 ABc 1 AB1 ABc 5 Y Karnaugh map by looping groups of one, two, four,
5. simplify the following four-variable expressions or eight 1s and “OR”ing the looped terms.
using Karnaugh maps:
a. ABcD 1 ABcD 1 ABcD 1 ABcD 1

ABcD 1 ABcD 1 ABcD 5 Y
b. AB 1 ABD 1 BcD 1 Bc 1 ABcD 5 Y

CHAPTER 43 SELF-TEST

1. Describe the procedure for using the Veitch diagram to simplify logic circuits.
2. simplify the following Boolean expressions by using a Veitch diagram:

a. ABc 1 ABc 1 ABc 1 ABc 1 ABc 5 Y
b. ABc 1 ABc 1 ABc 1 ABc 1 ABc1 ABc 5 Y
c. ABcD 1 ABcD 1 AcD 1 ABc 1 AB 1 ABcD 5 Y
d. ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 5 Y
e. ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 5 Y
3. Describe the procedure for using a Karnaugh map to simplify logic circuits.
4. simplify the following Boolean expressions by using a Karnaugh map:
a. ABc 1 ABc 1 ABc 1 ABc 1 ABc 5 Y
b. ABc 1 ABc 1 ABc 1 ABc 1 ABc1 ABc 5 Y
c. ABcD 1 ABcD 1 AcD 1 ABc 1 AB 1 ABcD 5 Y
d. ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 5 Y
e. ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 1 ABcD 5 Y

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

44C H A P T E R

Sequential Logic Circuits

ObjECTivES KEy TERmS

After completing this chapter, the student 44 sequential logic 44-3 shift register
will be able to: circuit
44-4 byte
■ Describe the function of a flip-flop. 44-1 clocked flip-flop
44-1 D flip-flop 44-4 dynamic RAM
■ Identify the basic types of flip-flops. 44-1 JK flip-flop (DRAM)
44-1 latch
■ Draw the symbols used to represent flip-flops. 44-1 RS flip-flop 44-4 electrically
44-1 transparent erasable PROM
■ Describe how flip-flops are used in digital (EEPROM)
circuits. latch
44-2 asynchronous 44-4 memory
■ Describe how a counter and shift register 44-2 counter
operates. 44-2 decade counter 44-4 nibble
44-2 modulus
■ Identify the different types of counters and shift 44-2 parallel counter 44-4 programmable
registers. 44-2 ripple counter read-only
44-2 stage memory (PROM)
■ Draw the symbols used to represent counters 44-2 synchronous
and shift registers. 44-2 synchronous 44-4 random-access
memory (RAM)
■ Identify applications of counters and shift counter
registers. 44-2 up–down 44-4 read-only
memory (ROM)
counter
44-4 static RAM
(SRAM)

44-4 word

410

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Sequential Logic Circuits CHAPTER 44 411

Sequential logic circuits consist of circuits holding its output to a low. When the Q output is low,
requiring timing and memory devices. The ba- the flip-flop is said to be in the RESET state. It remains
sic building block for sequential logic circuits is in this state indefinitely, until a high is applied to the S
the flip-flop. Flip-flops can be wired together to form input of gate 2. When a high is applied to the S input
counters, shift registers, and memory devices. of gate 2, the output of gate 2 becomes a low and is
coupled to the input of gate 1. Because the R input of
The flip-flop belongs to a category of digital circuits gate 1 is a low, the output changes to a high. The high
called multivibrators. A multivibrator is a regenerative is coupled back to the input of gate 2, ensuring that the
circuit with two active devices. It is designed so that Q output remains a low. When the Q output is high,
one device conducts while the other device is cut off. the flip-flop is said to be in the SET state. It remains
Multivibrators can store binary numbers, count pulses, in the SET state until a high is applied to the R input,
synchronize arithmetic operations, and perform other causing the flip-flop to RESET.
essential functions in digital systems.
An “illegal” or “unallowed” condition occurs when
There are three types of multivibrators: bistable, a high is applied to both the R and S inputs simultane-
monostable, and astable. The bistable multivibrator is ously. In this case, the Q and Q outputs both try to go
called a flip-flop. low, but Q and Q cannot be in the same state at the
same time without violating the definition of flip-flop
44–1 Flip-Flops operation. When the highs on the R and S inputs are
A flip-flop is a bistable multivibrator whose output removed simultaneously, both of the outputs attempt
to go high. Because there is always some difference in
is either a high or low voltage, a 1 or a 0. The output the gates, one gate dominates and becomes high. This
stays high or low until an input called a trigger is forces the other gate to remain low. An unpredictable
applied. mode of operation exists and therefore the output state
of the flip-flop cannot be determined.
The basic flip-flop is the Rs flip-flop. It is
formed by two cross-coupled NOR or NAND gates Figure 44-2 shows the truth table for operation of
(Figure 44-1). The RS flip-flop has two outputs, Q and an RS flip-flop. Figure 44-3 is a simplified symbol used
Q, and two controlling inputs, R (Reset) and S (Set). to represent an RS flip-flop.
The outputs are always opposite or complementary: If
Q 5 1, then Q 5 0, and vice-versa. Another type of flip-flop is called a clocked
flip-flop. It is different from the RS flip-flop in that
To understand the operation of the circuit, assume an additional input is required for operation. The
that the Q output, R input, and S input are all low. third input is called the clock or trigger. Figure 44-4
The low on the Q output is connected to one of the shows a logic diagram for a clocked flip-flop. A high at
inputs of gate 2. The S input is low. The output of gate either input of the flip-flop portion activates the flip-
2 is high. This high is coupled to the input of gate 1, flop, causing it to change states. The portion labeled
“steering gate” steers or directs the clock pulses to
■ FiguRE 44-1 either input gate.

Basic flip-flop circuit. Q ■ FiguRE 44-2

R Truth table for an RS flip-flop.

SQ © 2014 Cengage Learning Inputs Outputs
SQ SR QQ
00 NC NC
RQ 01 01
10 10
11 00

NC = No change

© 2014 Cengage Learning

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

412 SECTiON 6 DIgITAl ElEcTROnIc cIRcuITS

■ FiguRE 44-3 ■ FiguRE 44-5

logic symbol for an RS flip-flop. logic symbol for a positive-edge-triggered RS flip-flop.

SQ © 2014 Cengage Learning SQ © 2014 Cengage Learning
RQ CLK
RQ

■ FiguRE 44-4 Q is important in computers and calculators when each
Q step must be performed in an exact order. Figure 44-5
logic circuit for a clocked RS flip-flop. shows the logic symbol used to represent a positive-
edge-triggered RS flip-flop.
S
A D flip-flop is useful where only 1 data bit (1 or 0)
CLK © 2014 Cengage Learning is to be stored. Figure 44-6 shows the logic diagram
for a D flip-flop. It has a single data input and a clock
R Basic input. The D flip-flop is also referred to as a delay flip-
Steering gate flip-flop flop. The D input is delayed one clock pulse from get-
ting to the output (Q). Sometimes the D flip-flop has
The clocked flip-flop is controlled by the logic state a PS (preset) input and CLR (clear) input. The preset
of the S and R inputs when a clock pulse is present. A input sets output Q to a 1 when a low or 0 is applied to
change in the state of the flip-flop occurs only when it. The clear input clears the Q output to a 0 when it is
the leading edge of the clock pulse is applied. The enabled by a low or 0. D flip-flops are wired together
leading edge of the clock pulse is a positive-going tran- to form shift registers and storage registers. These reg-
sition (low to high). This means that the pulse goes isters are widely used in digital systems.
from a zero voltage level to a positive voltage level.
This is referred to as positive-edge-triggered (the edge The JK flip-flop is the most widely used flip-flop.
of the pulse is what triggers the circuit). It has all the features of the other types of flip-flops.
It is also edge triggered, accepting data only at the J
As long as the clock input is low, the S and R in- and K inputs that are present at the active clock edge
puts can be changed without affecting the state of the (high to low or low to high). This allows the accept-
flip-flop. The only time that the effects of the S and ing of input data on J and K at a precise instant. The
R inputs are felt is when a clock pulse occurs. This is logic diagram and symbol for the JK flip-flop is shown
referred to as synchronous operation. The flip-flop in Figure 44-7. J and K are the inputs. The significant
operates in step with the clock. Synchronous operation feature of the JK flip-flop is that when both the J and
K inputs are high, repeated clock pulses cause the
output to toggle or change state. The two asynchro-
nous inputs, PS (preset) and CLR (clear), override the

■ FiguRE 44-6 Q DQ

logic circuit and symbol for the D flip-flop.

D

CLK CLK © 2014 Cengage Learning
QQ

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Sequential Logic Circuits CHAPTER 44 413

■ FiguRE 44-7

logic circuit and symbol for the JK flip-flop.

K JQ JQ
Q

CLK CLK CLK

J Q KQ © 2014 Cengage Learning
KQ

(A) (B)

Positive-edges Negative-edges
triggered triggered

synchronous inputs, the J and K data inputs, and the 44–1 Questions
clock input. JK flip-flops are widely used in many digi-
tal circuits, especially counter circuits. Counters are 1. What is a flip-flop?
found in almost every digital system. 2. What are the different types of flip-flops?
3. What is meant by a clocked flip-flop?
A latch is a device that serves as a temporary buf- 4. What is the difference between an asynchro-
fer memory. It is used to hold data after the input sig-
nal is removed. The D flip-flop is a good example of a nous input and a synchronous input?
latch device. Other types of flip-flops can also be used. 5. What is a latch?

A latch is used when inputting to a seven-segment 44–2 CounteRs
display. Without a latch, the information being dis-
played is removed when the input signal is removed. A counter is a logic circuit that can count a sequence
With the latch, the information is displayed until it is of numbers or states when activated by a clock input.
updated. The output of a counter indicates the binary number
stored in the counter at any given time. The number
Figure 44-8 shows a 4-bit latch. The unit has four of counts or states through which a counter progresses
D flip-flops enclosed in a single IC package. The E before returning to its original state (recycling) is
(enable) inputs are similar to the clock input of the called the modulus of the counter.
D flip-flop. The data are latched when the enable line
drops to a low, or 0. When the enable is high, or 1, the A flip-flop can act as a simple counter when con-
output follows the input. This means that the output nected as shown in Figure 44-9. Assuming that initially
will change to whatever state the input is in; for exam-
ple, if the input is high, the output will become high; if
the input is low, the output will become low. This con-
dition is referred to as a transparent latch.

■ FiguRE 44-8 Q0 ■ FiguRE 44-9
Q1
Four-bit latch. Q2 JK flip-flop set up for counting.
Q3 1
D0
D1 JQ
D2
D3 CLK

© 2014 Cengage Learning
© 2014 Cengage Learning
E0 –1 KQ
E2–3

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

414 SECTiON 6 DIgITAl ElEcTROnIc cIRcuITS

■ FiguRE 44-10 ■ FiguRE 44-11

Input and output waveforms of JK flip-flop set up Two-stage counter.
as a counter.
1
A B

CLK 1 2 34 JQ
CLK
Q JQ K
CLK
© 2014 Cengage Learning
© 2014 Cengage Learning
Q KQ

the flip-flop is reset, the first clock pulse causes it to Notice that the Q output of the first stage is cou-
set (Q 5 1). The second clock pulse causes it to reset pled to the clock input of the second stage. The second
(Q 5 0). Because the flip-flop has set and reset, two stage only changes state when triggered by the transi-
clock pulses have occurred. tion of the output of the first stage. Because of the de-
lay through the flip-flop, the second flip-flop does not
Figure 44-10 shows the output waveform of the change state at the same time the clock pulse is applied.
flip-flop. Notice that the Q output is high (1) after ev- Therefore, the two flip-flops are never simultaneously
ery odd clock pulse and low (0) after every even clock triggered, which results in asynchronous operation.
pulse. Therefore, when the output is high, an odd
number of clock pulses have occurred. When the out- Asynchronous counters are commonly referred to
put is low, either no clock pulses or an even number of as ripple counters. The input clock pulse is first felt
clock pulses has occurred. In this case, it is not known by the first flip-flop. The effect is not felt by the second
which has occurred. flip-flop immediately because of the delay through the
first flip-flop. In a multistage counter, the delay is felt
A single flip-flop produces a limited counting se- through each flip-flop, so the effect of the input clock
quence, 0 or 1. To increase the counting capacity, ad- pulse “ripples” through the counter. Figure 44-12 shows
ditional flip-flops are needed. The maximum number a three-stage binary counter and timing chart for each
of binary states in which a counter can exist depends of the stages. A truth table shows the counting sequence.
on the number of flip-flops in the counter. This can be
expressed as Synchronous means “occurring at the same time.”
A synchronous counter is a counter in which each
N 5 2n stage is clocked at the same time. This is accomplished
where: N 5 maximum number of counter states by connecting the clock input to each stage of the
counter (Figure 44-13). A synchronous counter is also
n 5 number of flip-flops in counter called a parallel counter because the clock input is
Binary counters fall into two categories based on connected in parallel to each flip-flop.
how the clock pulses are used to sequence the coun-
ter. The two categories are asynchronous and A synchronous counter operates as follows. Initially
synchronous. the counter is reset with both flip-flops in the 0 state.
Asynchronous means “not occurring at the same When the first clock pulse is applied, the first flip-flop
time.” With respect to counter operations, asynchro- toggles and the output goes high. The second flip-flop
nous means that the flip-flops do not change states does not toggle because of the delay from the input
at the same time. This is because the clock pulse to the actual changing of the output state. Therefore,
is not connected to the clock input of each stage. there is no change in the second flip-flop output state.
Figure 44-11 shows a two-stage counter connected for When the second clock pulse is applied, the first flip-
asynchronous operation. Each flip-flop in a counter is flop toggles and the output goes low. Because there is
referred to as a stage. a high from the output of the first stage, the second

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Sequential Logic Circuits CHAPTER 44 415

■ FiguRE 44-12 A B C

Three-stage binary counter. JQ JQ
CLK CLK
1
KQ K
JQ

CLK
KQ

Number of Binary Count Sequence Decimal
Clock Pulses CBA Count
000
0 001 0
1 010 1
2 011 2
3 100 3
4 101 4
5 110 5
6 111 6
7 000 7
8 0
Count sequence

Clock 0 1 2 3 4 5 6 7 8
pulses

A

B © 2014 Cengage Learning

C

stage toggles and its output goes high. After four One application of a counter is frequency divi-
clock pulses, the counter recycles to its original state. sion. A single flip-flop produces an output pulse for
Figure 44-14 shows a timing chart for this sequence of every two input pulses. Therefore, it is essentially a
events with a two-stage synchronous counter. divide-by-two device with an output one-half the
frequency of the input. A two-stage binary counter is
Figure 44-15 shows a three-stage binary counter a divide-by-four device with an output equal to one-
and timing chart. Figure 44-16 shows a four-stage syn- fourth the input clock frequency. A four-stage binary
chronous counter and logic symbol.

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

416 SECTiON 6 DIgITAl ElEcTROnIc cIRcuITS

■ FiguRE 44-13 ■ FiguRE 44-14

Two-stage synchronous counter. Input and output waveforms for the two-stage
synchronous counter.

1A B CLK 0 1 2 3 4

JQ JQ

CLK CLK © 2014 Cengage LearningA
© 2014 Cengage Learning
KK B

■ FiguRE 44-15 B C

Three-stage binary counter and timing chart.

1A

JQ JQ JQ
CLK CLK CLK

K K K

CLK 0 1234567 8

Outputs Binary Count Sequence Decimal © 2014 Cengage Learning
A CBA Count
000
B 001 0
010 1
C 011 2
100 3
Number of 101 4
Clock Pulses 110 5
111 6
0 000 7
1 0
2
3
4
5
6
7
8

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

■ FiguRE 44-16 Sequential Logic Circuits CHAPTER 44 417

logic symbol for a four-stage synchronous counter. CD

1 AB

JQ JQ JQ JQ © 2014 Cengage Learning
CLK CLK CLK CLK
KK K K

CLK QA A
QB
QC B
QD
C

D

■ FiguRE 44-17

A counter as a frequency divider.

CLK QA A

QB B
QC C
QD D

CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A © 2014 Cengage Learning
B
C
D

counter is a divide-by-16 device with the output by 16 (24), a five-stage counter by 32 (25), and so on.
equal to one-sixteenth the input clock frequency Notice that the modulus of the counter is the same as
(Figure 44-17). the division factor.

A binary counter with n stages divides the clock Decade counters have a modulus of 10, or 10
frequency by a factor of 2n. A three-stage counter states in their counting sequence. A common decade
divides the frequency by 8 (23), a four-stage counter counter is the BCD (8421) counter, which produces a

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

418 SECTiON 6 DIgITAl ElEcTROnIc cIRcuITS

■ FiguRE 44-18 A B C D

Synchronous BcD decade counter.

1

JQ JQ JQ JQ
CLK CLK CLK CLK
KK K K

CLK © 2014 Cengage Learning
0

■ FiguRE 44-19 ■ FiguRE 44-20

logic symbol for a decade counter. logic symbol for an up–down counter.

QA QA
QB
CLK QC © 2014 Cengage Learning CLK QB
QD QC
© 2014 Cengage Learning
Up/Down QD

binary-coded-decimal sequence (Figure 44-18). The the first flip-flop in a ripple counter. If a 0 is fed back
AND and OR gates detect the occurrence of the ninth to the JK input of the first flip-flop (Figure 44-22), it
state and cause the counter to recycle on the next clock prevents the first flip-flop from toggling, thereby stop-
pulse. The symbol for a decade counter is shown in ping the count.
Figure 44-19.
44–2 Questions
An up–down counter can count in either di-
rection through a certain sequence. It is also referred 1. What function does a counter serve?
to as a bidirectional counter. The counter can be re- 2. How many counting sequences are available
versed at any point in the counting sequence. Its sym-
bol is shown in Figure 44-20. An up–down counter with an eight-stage counter?
can consist of any number of stages. Figure 44-21 3. How does an asynchronous counter operate?
shows the logic diagram for a BCD up–down coun- 4. How does a synchronous counter differ from an
ter. The inputs to the JK flip-flops are enabled by the
up–down input qualifying the up or down set of the asynchronous counter?
AND gates. 5. How can a counter be made to stop at any

Counters can be stopped after any sequence of count desired?
counting by using a logic gate or combination of logic
gates. The output of the gate is fed back to the input of

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

■ FiguRE 44-21 Sequential Logic Circuits CHAPTER 44 419

logic diagram for a BcD up–down counter. BC
JQ JQ
Up/Down A CLK CLK
KQ K
Clock 1
JQ
CLK © 2014 Cengage Learning
KQ

■ FiguRE 44-22

A low applied to the JK input of the first flip-flop prevents it from toggling, stopping the count.

CD
AB

1 JQ JQ JQ JQ © 2014 Cengage Learning
Clock

KQ KQ KQ KQ

44–3 shiFt RegisteRs register is valuable in performing a variety of logic
A shift register is a sequential logic circuit widely operations.
used to store data temporarily. Data can be loaded
into and removed from a shift register in either a par- Shift registers are constructed of flip-flops wired
allel or serial format. Figure 44-23 shows the four dif- together. Flip-flops have all the functions necessary for
ferent methods of loading and reading data in a shift a register: They can be reset, preset, toggled, or steered
register. Because of its ability to move data 1 bit at a to a 1 or 0 level. Figure 44-24 shows a basic shift regis-
time from one storage medium to another, the shift ter constructed from four flip-flops. It is called a 4-bit
shift register because it consists of four binary storage
■ FiguRE 44-23 elements. A significant feature of the shift register is
that it can move data to the right or left a number of bit
Methods of loading and reading data in a shift register. positions. This is equivalent to multiplying or divid-
ing a number by a specific factor. The data are shifted

Serial IN Serial IN ■ FiguRE 44-24
Serial OUT Parallel OUT
Shift register constructed from four flip-flops.

AB CD

Parallel IN Parallel IN © 2014 Cengage LearningDataDQ DQ DQ DQ
Parallel OUT Serial OUT © 2014 Cengage Learning
Clock CLK CLK CLK CLK
Clear Q Q Q Q

CLR CLR CLR CLR

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

420 SECTiON 6 DIgITAl ElEcTROnIc cIRcuITS

■ FiguRE 44-25 ■ FiguRE 44-27

A typical shift register constructed of JK flip-flops. loading a shift register using parallel input.

AB CD Data IN

1 AB C D
Data
PR PR PR PR PS PS PS PS
1
Clock J AQ J BQ J CQ J DQ © 2014 Cengage Learning J AQ J BQ J CQ J DQ
CLK CLK CLK CLK © 2014 Cengage LearningCLKCLKCLKCLK

KQ KQ KQ KQ KQ KQ KQ KQ

CLR CLR CLR CLR

CLR CLR CLR CLR

1 bit position at a time for each input clock pulse. The Clock AB CD
clock pulses have full control over the shift register Clear
operations.
Data OUT
Figure 44-25 shows a typical 4-bit shift register
constructed of JK flip-flops. The serial data and their conversion. Figure 44-27 shows how a shift register
complements are applied to the JK inputs of the A flip- can be loaded by a parallel input. For parallel opera-
flop. The other flip-flops are cascaded, with the out- tions, the input data are preset into the shift register.
puts of one connected to the inputs of the next. The Once the data are in the shift register, they can be
toggles of all the flip-flops are connected together, and shifted out serially, as discussed earlier.
the clock pulse is applied to this line. Because all the
flip-flops are toggled together, this is a synchronous For serial-to-parallel data conversion, the data are
circuit. Also, the clear inputs of each flip-flop are tied initially shifted into the shift register with clock pulses.
together to form a reset line. Data applied to the in- Once the data are in the shift register, the outputs of
put are shifted through the flip-flops 1 bit position for the individual flip-flops are monitored simultaneously,
each clock pulse. For example, if the binary number and the data are routed to their destination.
1011 is applied to the input of the shift register and a
shift pulse is applied, the number stored in the shift Shift registers can perform arithmetic operations
register is shifted out and lost while the external num- such as multiplication or division. Shifting a binary
ber is shifted in. Figure 44-26 shows the sequence of number stored in the shift register to the right has the
events for storing a number in the shift register. same effect as dividing the number by some power of
2. Shifting the binary number stored in the shift reg-
One of the most common applications of a shift ister to the left has the same effect as multiplying the
register is serial-to-parallel or parallel-to-serial data number by some power of 2. Shift registers are a sim-
ple and inexpensive means of performing multiplica-
■ FiguRE 44-26 tion and division of numbers.

Storing a number in a shift register. Shift registers are often used for temporary stor-
age. They are capable of storing one or more binary
Initial condition 1011 0 0 0 0 © 2014 Cengage Learning words. There are three requirements for this applica-
101 1 0 0 0 0 tion of a shift register: First, it must be able to accept
After 1st and store data. Second, it must be able to retrieve or
shift pulse 10 1 1 0 0 0 0 read out the data on command. Third, when the data
10 1 1 00 0 0 are read, they must not be lost. Figure 44-28 shows the
After 2nd external circuitry required to enable a shift register to
shift pulse 1 0 1 10000 read and maintain the data stored in it. The read/write
After 3rd Data lost line, when high, allows new data to be stored in the
shift pulse shift register. Once the data are stored, the read/write
line goes low, enabling gate 2, which allows the data to
After 4th recirculate while reading out the data.
shift pulse

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Sequential Logic Circuits CHAPTER 44 421

■ FiguRE 44-28

Shift register circuitry for maintaining and reading data.

Data
Read/write

Shift register © 2014 Cengage Learning

Output

MSB LSB

44–3 Questions types of memories have evolved, each designed for a
particular application.
1. What is the function of a shift register?
2. What is a significant feature of a shift register? Memory is built from storage registers. Storage reg-
3. From what are shift registers constructed? isters store the digital data, such as programs or data,
4. What is a common application of a shift on a short term in digital systems. The flip-flop is the
basic building block for storage registers.
register?
5. What arithmetic operations can a shift register A 4-bit register stores 4 bits, referred to as a nibble;
an 8-bit register stores 8 bits, called a byte; and a
perform, and how does it perform them? larger register stores a word. Typical word sizes are
16, 32, 64, and 128 bits. Registers with 4, 8, and 16 bits
44–4 MeMoRy are shown in Figure 44-29. By looking at the Q output,
the status of the data stored can be checked in any of
Memory serves to store digital data on a temporary or these registers. The complementary data are also avail-
permanent basis. Because of the different ways that the able by looking at the Q output.
stored data are used in digital systems, many different
Figure 44-30 shows how data are stored in a larger
memory configuration. A matrix of storage elements
capable of storing a 1 or a 0 is organized into words
that a decoder can locate by a specific address.

■ FiguRE 44-29

Four-, 8-, and 16-bit registers.

4210 64 32 16 8 4 2 1 0
LSB LSB

Q4 Q3 Q2 Q1 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1

0101

Q4 Q3 Q2 Q1 10110111

Complementary data Complementary data available
(A) (B)

16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 0 © 2014 Cengage Learning
LSB

Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1

Complementary data available
(C)

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

422 SECTiON 6 DIgITAl ElEcTROnIc cIRcuITS

■ FiguRE 44-30

large memory array (8 bit).

One byte 7
6
A0 0 Decoder 57 15
A1 1 46 31
A2 2 35 47 © 2014 Cengage Learning
A3 4 24 63
A4 8 13 79
A5 16 02 95
A6 32 1 111
A7 64 00 127
0 143
16 159
32 175
48 191
64 207
80 223
96 239
112 256
128
144
160
176
192
208
224
240

The technology used in making the memory inte- to both read and write data. It is also volatile. This
grated circuits (chips) is based on either bipolar (also means that the stored data will be lost if the power
referred to as transistor-to-transistor logic [TTL]) or is shut off.
metal-oxide semiconductor (MOS) transistors. Bi-
polar memory is faster than MOS memory, but MOS Two types of RAM are available: static and dynamic.
memory can be packed with a higher density, provid- static RAM (sRAM) uses a bistable circuit as the stor-
ing more memory locations in the same amount of age element. It loses data when the power is removed.
area required by bipolar memory. Dynamic RAM (DRAM) is different because it uses
capacitors to store the data. The drawback is that the
Data are stored digitally in two types of memory: capacitors discharge over time and must be recharged
random-access memory and read-only memory. or refreshed periodically to maintain the stored data.
Random-access memory (RAM) is used for the Even with the additional support circuit requirement,
temporary storage of programs, data, control infor- SRAMs are still cheaper and have a higher density, re-
mation, and so on. It provides random access to the ducing the circuit board area required.
stored data, with all storage locations being reached
in the same amount of time. RAM has the capability Read-only memory (RoM) allows data to be
permanently stored and allows the data to be read

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Sequential Logic Circuits CHAPTER 44 423

■ FiguRE 44-31

Rom family chart.

ROM

Bipolar MOS
(TTL)

Mask PROM Mask PROM EPROM EPROM © 2014 Cengage Learning
ROM ROM

from memory at any time, with no provision for data 44–4 Questions
to be written to it. ROMs are considered nonvola-
tile memory. ROMs use the same decoder circuitry 1. What is memory?
as RAM. The stored data are retained even when the 2. What are the two types of technology used to
power is removed. ROMs may be programmed during
manufacture to be either permanent or replaceable by make memory chips?
the user, but they are not easily altered and require the 3. What are the two types of memory devices?
use of a special device called a burner. 4. What is meant by the term volatile?
5. Describe a situation in which it would be ad-
Figure 44-31 shows the ROM family chart. The
mask-programming process takes place during the vantageous to convert from EPROM memory
manufacturing process. The transistor-emitter con- design to the mask ROM.
nection is either made or not made through a mask
during manufacture. The mask does the programming. suMMARy

programmable read-only memory (pRoM) ● A flip-flop is a bistable multivibrator whose output
can be programmed after manufacture. The program is either a high or a low.
is entered into the PROM by blowing a fusible link.
Initially, all emitter links are connected as 1s in all ● Types of flip-flops include these listed here:
storage locations. The emitter links where 0s occur are ● RS flip-flop
blown open with a high-current surge. PROMs cannot ● Clocked RS flip-flop
be reprogrammed. ● D flip-flop
● JK flip-flop
electrically erasable pRoMs (eepRoMs)
can be programmed and erased by using an electrical ● Flip-flops are used in digital circuits such as
charge. By applying a high voltage (around 21 volts), counters.
a single byte or the entire chip can be erased in about
10 milliseconds. Erasing can be done with the chip in ● A latch is a temporary buffer memory.
the circuit. EEPROMs are used where data needs to be
maintained for later use, such as the custom guide in a
television satellite system.

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

424 SECTiON 6 DIgITAl ElEcTROnIc cIRcuITS

● A counter is a logic circuit that can count a ● Memory stores data temporarily or permanently.
sequence of numbers or states. ● Memory is built from shift registers.
● A 4-bit register stores a nibble.
● A single flip-flop produces a count sequence of 0 ● An 8-bit register stores a byte.
or 1. ● A 16-bit register stores a word.
● Bipolar memory is faster than MOS memory.
● The maximum number of binary states a counter ● MOS memory can pack a higher density, providing
can have depends on the number of flip-flops
contained in the counter. more memory locations in the same area for
bipolar memory.
● Counters can be either asynchronous or ● Data is stored into two types of memory: random-
synchronous. access memory (RAM) or read-only memory
(ROM).
● Asynchronous counters are called ripple counters. ● Two types of RAM are available: static RAM
● Synchronous counters clock each stage at the same (SRAM) or dynamic RAM (DRAM).
● Programmable read-only memory (PROM) can be
time. programmed after manufacture.
● Shift registers are used to store data temporarily. ● Electrically erasable PROMs (EEPROMs) can be
● Shift registers are constructed of flip-flops wired programmed and erased using an electrical charge.

together.
● Shift registers can move data to the left or right.
● Shift registers are used for serial-to-parallel and

parallel-to-serial data conversions.
● Shift registers can perform multiplication and

division.

CHAPTER 44 SELF-TEST

1. Describe how an RS flip-flop changes states 6. For what functions or applications can the shift

from a high on the Q output to a high on the register be used?
7. Define bit, nibble, byte, and word.
Q output. 8. What is meant by complementary data?
2. What is the major difference between the D 9. What is the advantage of MOS memory or

flip-flop and the clocked RS flip-flop? bipolar memory?
3. What components make up a counter, and how 10. Describe the difference between static and

is it constructed? dynamic RAM.
4. Draw a schematic for a counter that will count 11. What is the difference between RAM and ROM?
12. Which type of ROM can be reprogrammed?
to 10 and then repeat.
5. How does a shift register differ from a counter?

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

45C H A P T E R

Combinational Logic Circuits

ObjECTivEs KEy TERms

After completing this chapter, the student will be 45 combinational 45-4 full subtractor
able to: logic circuit
45-4 half adder
■ Describe the functions of encoders, decoders, 45-1 decimal-to-
multiplexers, adders, subtractors, and binary encoder 45-4 half subtractor
comparators.
45-1 decimal-to- 45-4 subtractor
■ Identify the schematic symbols for encoders, binary priority
decoders, multiplexers, adders, subtractors, and encoder 45-5 programmable
comparators. array logic
45-1 encoder (PAL®)
■ Identify applications for combinational logic
circuits. 45-2 decoder 45-5 programmable
logic array (PLA)
■ Develop truth tables for the different 45-3 multiplexer
combinational logic circuits. 45-5 programmable
45-4 adder logic device
(PLD)
45-4 comparator

45-4 full adder

425

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Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

426 sECTiON 6 DIgItAL ELEctronIc cIrcuIts

Combinational logic circuits are circuits that 45–1 EncodErs
combine the basic components of AND gates, OR An encoder is a combinational logic circuit that
gates, and inverters to produce more sophisticated accepts one or more inputs and generates a multibit
circuits. The output of a combinational logic circuit is binary output. Encoding is the process of converting
a function of the states of the inputs, the types of gates any keyboard character or number as input to a coded
used, and the interconnection of the gates. The most output such as a binary or BCD form.
common of the combinational circuits are decoders,
encoders, multiplexers, and arithmetic circuits. Figure 45-1 shows a decimal-to-binary
encoder. Its function is to take a single digit (0 to 9) as
■ FiguRE 45-1 input and to output a 4-bit code representation of the
digit. This is referred to as a 10-line-to-4-line encoder.
Decimal-to-binary encoder. That is, if the digit 4 on the keyboard is entered, this
produces a low output, or a 0, on line 4, which pro-
9 D © 2014 Cengage Learning duces the 4-bit code 0100 as an output.
8
7 C Figure 45-2 shows a decimal-to-binary priority
56 B encoder. The priority function means that if two keys
4 are pressed simultaneously, the encoder produces a
3 A BCD output corresponding to the highest-order deci-
2 LSB mal digit appearing on the input. For example, if both
1

■ FiguRE 45-2

Decimal-to-binary priority encoder.

A© 2014 Cengage Learning
1
2
3
4

B
5
6
7
8

C
9

D

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Combinational Logic Circuits CHAPTER 45 427

■ FiguRE 45-3 ■ FiguRE 45-4

Logic symbol for a decimal-to-binary priority encoder. Binary-to-decimal decoder.

0 © 2014 Cengage LearningA 0
1 © 2014 Cengage LearningB 1
2A 2
3B 3
4C 4
5D 5
6
7
8
9

a 5 and a 2 are applied to the encoder, the BCD out- C6
put is 1010, or the inverse of decimal 5. This type of D7
encoder is built into a single integrated circuit and
consists of approximately 30 logic gates. Figure 45-3 8
shows the symbol for a priority encoder. 9

This type of encoder is used to translate the dec- readout or display. This type of decoder is called a
imal input from a keyboard to an 8421 BCD code. 1-of-10 decoder or a 4-line-to-10-line decoder.
The decimal-to-binary encoder and the decimal-to-
binary priority encoder are found wherever there is Figure 45-4 shows the 10 NAND gates required
keyboard input, including in calculators, cell phones, for decoding a 4-bit BCD number to its approximate
computer keyboard inputs, electronic typewriters, output (one decimal digit). When all the inputs to a
telephones, and teletypewriters (TTY). NAND gate are 1, its output is 0. All other outputs
from the NAND gates in the decoder are 1s. Rather
45–1 QuEstions than draw all the logic gates each time the circuit is
used, the symbol shown in Figure 45-5 is used.
1. What is encoding?
2. What does an encoder accomplish? ■ FiguRE 45-5
3. What is the difference between a normal
Logic symbol for a binary-to-decimal decoder.
encoder and a priority encoder?
4. Draw the logic symbol for a decimal-to-binary

priority encoder.

45–2 dEcodErs 0 © 2014 Cengage Learning
A decoder is one of the most frequently used com- 1
binational logic circuits. It processes a complex 2
binary code into a recognizable digit or character. A3
For example, it might decode a BCD number into B4
one of the 10 possible decimal digits. The output of C5
such a decoder is used to operate a decimal number D6
7
8
9

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

428 sECTiON 6 DIgItAL ELEctronIc cIrcuIts

■ FiguRE 45-6 ■ FiguRE 45-7

Logic symbols for a 1-of-8 decoder (A) and a 1-of-16 seven-segment display configuration.
decoder (B).

A 0 A 0 © 2014 Cengage Learning a
B 1 of 8 1 B 1 © 2014 Cengage Learning
C 2 C 1 of 16 2 fb
3 D 3 g
4 4
5 (B) 5 ec
6 6
7 7 d
8 d.p.
(A) 9
10 displays: a common anode and a common cathode. In
11 each case, the LED segment has to be forward biased
12 for light to be emitted. For a common cathode, a high
13 (1) lights up the segment; a low (0) does not.
14
15 Figure 45-10 shows the decoding logic circuit re-
quired to produce the output for a seven-segment dis-
Two other types of decoder circuits are the 1-of-8 play with a BCD input. Referring to Figure 45-7, notice
(octal, or base-8) decoder and the 1-of-16 (hexadeci- that segment a is activated for digits 0, 2, 3, 5, 7, 8, and
mal, or base-16) decoder (Figure 45-6). The 1-of-8 9; segment b is activated for digits 0, 1, 2, 3, 4, 7, 8,
decoder accepts a 3-bit input word and decodes it to and 9; and so on. Boolean expressions can be formed
one of eight possible outputs. The 1-of-16 decoder ac- to determine the logic circuitry needed to drive each
tivates 1 of 16 output lines by a 4-bit code word. It is segment of the display. The logic symbol for a BCD-
also called a 4-line-to-16-line decoder. to-seven-segment decoder is shown in Figure 45-11.
This represents the circuit contained in an integrated
A special type of decoder is the standard 8421 circuit.
BCD-to-seven-segment decoder. It accepts a BCD
input code and generates a special 7-bit output code 45–2 QuEstions
to energize a seven-segment decimal readout display
(Figure 45-7). The display consists of seven LED seg- 1. What is a decoder?
ments that are lit in different combinations to produce 2. What are the uses of decoders?
each of the 10 decimal digits, 0 through 9 (Figure 45-8). 3. Draw the logic symbol for a 1-of-10 decoder.
Besides seven-segment LED displays, there are incan- 4. What is the purpose of a seven-segment decoder?
descent and liquid crystal (LCD) displays. 5. What codes can be used in decoders?

Each of these displays operates on the same prin-
ciple. A segment is activated by either a high or low
voltage level. Figure 45-9 shows two types of LED

■ FiguRE 45-8

using the seven-segment display to form the 10 decimal digits.

© 2014 Cengage Learning

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

■ Figure 45-9 Combinational Logic Circuits Chapter 45 429© 2014 Cengage Learning

Differences between the two types of LED displays: a © 2014 Cengage Learning ■ Figure 45-11
common cathode (A), and a common anode (B).
Logic symbol for a BCD-to-seven-segment decoder.
1VCC
a
aa b
bb Ac
cc Bd
dd Ce
ee Df
ff g
gg d.p.
d.p. d.p.
■ Figure 45-12
(A) (B)
A single-pole, multiposition switch can be used as
a multiplexer.

© 2014 Cengage Learning

■ Figure 45-10 a
b
Binary-to-seven-segment display decoder. c
d
A e
B f
C g
D

© 2014 Cengage Learning

45–3 Multiplexers Multiposition switches are widely used in many
A multiplexer is a circuit used to select and route electronic circuits. However, circuits that operate at
any one of several input signals to a single output. An high speed require the multiplexer to switch at high
example of a nonelectronic circuit multiplexer is a speed and to be automatically selected. A mechanical
single-pole, multiposition switch (Figure 45-12). switch cannot perform this task satisfactorily. There-
fore, multiplexers used to perform high-speed switch-
ing are constructed of electronic components.

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

430 sECTiON 6 DIgItAL ELEctronIc cIrcuIts

Multiplexers handle two basic types of data: analog ■ FiguRE 45-14
and digital. For analog applications, multiplexers are
built of relays and transistor switches. For digital appli- Logic symbol for an eight-input multiplexer.
cations, multiplexers are built from standard logic gates.
0
Digital multiplexers allow digital data from sev-
eral individual sources to be routed through a com- 1
mon line for transmission to a common destination.
A basic multiplexer has several input lines with a 2
single output line. The input lines are activated by data
selection input that identifies the line the data are to 3 1 of 8 Y
be received on. Figure 45-13 shows the logic circuit for 4
an eight-input multiplexer. Notice that there are three
input-control lines, labeled A, B, and C. Any of the 5
eight input lines can be selected by the proper expres-
sion of the input-control line. The symbol used to rep- 6 © 2014 Cengage Learning
resent a digital multiplexer is shown in Figure 45-14.
7
Figure 45-15 shows the symbol for a 1-of-16 multi-
plexer. Notice that there are four input-control lines to ABC
activate the 16 data input lines.
■ FiguRE 45-15
In addition to data line selection, a common ap-
plication of a multiplexer is parallel-to-serial data Logic symbol for a 16-input multiplexer.

■ FiguRE 45-13 0

Logic circuit for an eight-input multiplexer. 1
0
1 2
2
3 3
4
5 4
6
7 5

A 6
B
C 7 1 of 16 Y
8

9

10

11

12

13

14

15
© 2014 Cengage Learning
© 2014 Cengage LearningABCD

conversion. A parallel binary word is applied to the
input of the multiplexer. Then, by sequencing through
the enabling codes, the output becomes a serial repre-
sentation of the parallel input word.

Figure 45-16 shows a multiplexer set up for par-
allel-to-serial conversion. A 3-bit binary input word
from a counter is used to select the desired input. The
parallel input word is connected to each of the input

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Combinational Logic Circuits CHAPTER 45 431

■ FiguRE 45-16 ■ FiguRE 45-17

using a multiplexer for parallel-to-serial conversion. truth table constructed using addition rules.

20 0 0 Inputs Outputs
21 1 BA S C0
22 1 1 00 00
23 0 01 10
8-Bit 24 1 2 Y 1 00 1 0 11 0 10 10
shift 25 0 3 1 of 8 11 01
register 26 0 4 multi-
27 1 5 plexer © 2014 Cengage Learning

6 © 2014 Cengage Learning

7A B C

Counter

represented by tCo0a.nTahdedseert.erms are used by industry
when referring
lines of the multiplexer. As the counter is incremented, The sum column of the truth table is the same
the input select code is sequenced through each of its as the output column in the truth table of an exclu-
states. The output of the multiplexer is equal to the sive OR gate (Figure 45-18). The carry column is the
parallel signal applied. same as the output in a truth table for an AND gate

(Figure 45-19).
Figure 45-20 shows an AND gate and an exclusive
45–3 QuEstions OR gate connected in parallel to provide the necessary
logic function for single-bit addition. The carry out-
1. What is a multiplexer? put (C0) is produced with the AND gate, and the sum
2. How are multiplexers used?
3. Draw a logic diagram for a multiplexer. ■ FiguRE 45-18
4. What types of data can a multiplexer handle?
5. How can a multiplexer be set up for parallel-to- truth table for an exclusive or gate.

serial conversion? A Y
B

45–4 ArithMEtic circuits AddEr B A Y
0 0 0
An adder is the primary computation unit in a digital 0 1 1
computer. Few routines are performed by a computer 1 0 1
in which the adder is not used. Adders are designed to 1 1 0
work in either serial or parallel circuits. Because the
parallel adder is faster and used more often, it is cov- © 2014 Cengage Learning
ered in more detail here.
■ FiguRE 45-19 Y
To understand how an adder works, it is necessary
to review the rules for adding: truth table for an AnD gate.

A
B

001 1 B A Y
0 0 0
10 11 10 11 0 1 0
1 0 0
0 1 1 Carry 1   0 1 1 1

Figure 45-17 shows a truth table based on these © 2014 Cengage Learning
rules. Note that the Greek letter sigma (S) is used
to represent the sum column. The carry column is

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

432 sECTiON 6 DIgItAL ELEctronIc cIrcuIts

■ FiguRE 45-20 ■ FiguRE 45-22

Half-adder circuit. Logic circuit for a full adder using two half adders.

A S CIN S
B

A© 2014 Cengage Learning COUT
B © 2014 Cengage Learning

C0

output (S) is produced with the XOR gate. The inputs ■ FiguRE 45-23
A and B are connected to both the AND gate and the
XOR gate. The truth table for the circuit is the same Logic symbols for half adder (A) and full adder (B).
as the truth table developed using the binary addi-
tion rules (Figure 45-17). Because the circuit does not AS C1 S
take into account any carries, it is referred to as a half A FA
adder. It can be used as the LSB adder for a binary HA
addition problem.
B C0 B C0
An adder that takes into account the carry is called (A) (B)
a full adder. A full adder accepts three inputs and
generates a sum and carry output. Figure 45-21 shows © 2014 Cengage Learning
ttohhueetptcruautr.trhytainbpleufto.rTahfeulCl 0adoduetrp.uTthreeCpr1eisnepnuttsrtehperecsaernrtys
A single full adder is capable of adding two single-
Figure 45-22 shows a full adder constructed of bit numbers and an input carry. To add binary num-
two half adders. The results of the first half adder are bers with more than 1 bit, additional full adders must
“OR”ed with the second half adder to form the carry be used. Remember, when one binary number is added
output. The carry output is a 1 if both inputs to the to another, each column that is added generates a sum
first XOR gate are 1s or if both inputs to the second and a carry of 1 or 0 to the next higher-order column.
XOR gate are 1s. Figure 45-23 shows the symbols used To add two binary numbers, a full adder is required
to represent a half adder and a full adder. for each column. For example, to add a 2-bit number
to another 2-bit number, two adders are required. Two
■ FiguRE 45-21 3-bit numbers require three adders, two 4-bit numbers
require four adders, and so on. The carry generated by
truth table for a full adder. each adder is applied to the input of the next higher-
order adder. Because no carry input is required for the
Inputs Outputs least significant position, a half adder is used.
CIN B S C0
00 00 Figure 45-24 shows a 4-bit parallel adder. The least
00 10 nsiegxntifhiciagnhteirn-pourdt ebritbs iatrsearreeprreespernetseednbteydAb0yanAd1 Ba0n.dThBe1
01 10
01 A 01 ■ FiguRE 45-24
10 0 10
10 1 01 Four-bit parallel adder.
11 0 01
11 1 11 B3 A3 B2 A2 B1 A1 B0 A0
0
© 2014 Cengage Learning 1 C1 C1 C1 HA © 2014 Cengage Learning
0 FA FA FA C0
1 C0 C0 C0

S4 S3 S2 S1 S0

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

Combinational Logic Circuits CHAPTER 45 433

■ FiguRE 45-25 subtractor

truth table constructed using subtraction rules. A subtractor allows subtraction of two binary num-
bers. To understand how a subtractor works, it is nec-
Inputs A Outputs essary to review the rules for subtraction.
B 0 D B0
0 1 00 0 Borrow 1   0 1 1
0 0 10 20 21 20 21
1 1 11
1 00 0 000

© 2014 Cengage Learning Figure 45-25 shows a truth table based on these
rules. The letter D represents the difference column.
The borrow column is (rDep)reisse1ntoendlybywBh0e.nNtohtieceintphuatt
■ FiguRE 45-26 the difference output
variables are not equal. Therefore, the difference can
Logic circuit for a half subtractor. be expressed as the exclusive OR of the input variables.
The output borrow is generated only when A is 0 and
A D B is 1. Therefore, the borrow output is the complement
B

© 2014 Cengage Learning of A “AND”ed with B.
Figure 45-26 shows a logic diagram of a half sub-
tractor. It has two inputs and generates a difference
and a borrow output. The difference is generated by
B0 an XOR gate and the borrow output is generated by an
AND gate with A and B inputs. The A is achieved by
iSasn2d,caosnnodnoesnoc.toTendh.etNooouttthepetuhtcaasturtrmhyebicniatpsrruayrteooiufdtetphnuettifonifeedexatacshhSiag0dh, dSeer1-r, using an inverter on the variable A input.
order adder. The carry output of the final adder is the However, a half subtractor is identified as such be-
most significant bit of the answer. cause it does not have a borrow input. A full subtrac-
tor does. It has three inputs and generates a difference
and a borrow output. A logic diagram and truth
table for a full subtractor are shown in Figure 45-27.

■ FiguRE 45-27 Input A Output
BIN B 0 D B0
Logic circuit (A) and truth table (B) for a full subtractor. 00 1 00
00 0 10
BIN 01 1 11
D 01 0 00
10 1 11
B B0 10 0 00
11 1 01
A 11 11
(A)
(B)

© 2014 Cengage Learning

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.

434 sECTiON 6 DIgItAL ELEctronIc cIrcuIts

■ FiguRE 45-28 ■ FiguRE 45-30

Logic symbols for half subtractor (A) and full subtractor (B). truth table for a comparator.

© 2014 Cengage Learning

A D BI D Input A Output
B HS A FS B 0 Y
(A) 0 1 1
B0 B B0 0 0 0
(B) 1 1 0
1 1
■ FiguRE 45-29
© 2014 Cengage Learning A5B
Four-bit subtractor.

B3 A3 B2 A2 B1 A1 B0 A0 ■ FiguRE 45-31

BI BI BI HS comparing two 2-bit numbers.
FS FS FS B0
B0 B0 AB00
© 2014 Cengage Learning
© 2014 Cengage Learning
D3 D2 D1 D0 AB11

Figure 45-28 shows the symbols used to represent a a comparator for checking two 2-bit numbers. If the
half-subtractor and full subtractor. numbers are equal, a 1 is generated from the XNOR
gate. The 1 is applied to the AND gate as a qualifying
A half subtractor can handle only two 1-bit num- level. If both XNOR gates produce a 1 for the inputs to
bers. To subtract binary numbers with more than 1 bit, the AND gate, that identifies the numbers as equal and
additional full subtractors must be used. Keep in mind generates a 1 for the output of the AND gate. However,
that if a 1 is subtracted from a 0, a borrow must be if the inputs to the XNOR gate are different, the XNOR
made from the next higher-order column. The out- gate generates a 0, which disqualifies the AND gate.
put borrow of the lower-order subtractor becomes the The output of the AND gate is then a 0. Figure 45-32
input borrow of the next higher-order subtractor. shows a logic diagram of a comparator for checking
two 4-bit numbers. Figure 45-33 is the diagram used
Figure 45-29 shows a block diagram of a 4-bit sub- to represent a 4-bit comparator.
tractor. A half subtractor is used in the least significant
bit position because there is no input borrow. ■ FiguRE 45-32 A5B
comparator
A comparator is used to compare the magnitudes of comparing two 4-bit numbers. © 2014 Cengage Learning
two binary numbers. It is a circuit used simply to de-
termine whether two numbers are equal. The output A0
not only compares two binary numbers but also indi-
cates whether one is larger or smaller than the other. B0
A1
Figure 45-30 shows a truth table for a comparator.
The only time an output is desired is when both bits B1
being compared are the same. The output column rep- A2
resents an exclusive OR with an inverter, also known B2
as an exclusive NOR (XNOR) gate. An XNOR gate is A3
essentially a comparator, because its output is a 1 only B3
if the two inputs are the same. To compare numbers
containing 2 bits or more, additional XNOR gates
are necessary. Figure 45-31 shows a logic diagram of

Copyright 2013 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. Due to electronic rights, some third party content may be suppressed from the eBook and/or eChapter(s).
Editorial review has deemed that any suppressed content does not materially affect the overall learning experience. Cengage Learning reserves the right to remove additional content at any time if subsequent rights restrictions require it.