Digital Electronics Fundamentals: Sequential Logic

SEQUENTIAL LOGIC

Latch & Flip-flop

DFE 1013

PREPARED BY: MOHD RADZI BIN TARMIZI 1
Bachelor of Engineering (Honours)
Mechatronics Engineering (USM)

Learning Outcome

At the end of this class, students should be able
to:

- Explain the internal circuit operation of SR flip flop.

- Sketch the operation of D flip flops using timing
diagrams.

- Sketch the operation of JK flip-flop using timing
diagrams.

- use timing diagrams to illustrate the synchronous and
asynchronous operation of JK flip-flop.

Contents

• Introduction
• Memory Element
• Latch

• SR latch
• D latch

• Flip-flop
• SR flip-flop
• D flip-flop
• JK flip-flop
• T flip-flop

3

Introduction

• There are two types of sequential circuit
• Synchronous – output change at certain time
• Asynchronous – output change any time

• Multivibrator – sequential circuit category – can
be

• Bistable – consist of two stable condition
• Monostable – consist of one stable condition
• Astable - no stable condition
• Bistable logic device is latch and flip-flop
• Latch and flip-flop differ by the method used to
change stable condition

4

Introduction

Combinational Logic:
• Output depends only on current input.
• Do not have memory element that can keep the
previous output state.
• Able to perform useful operations
(add/subtract/multiply/encode/decode/
select[mux]/etc…)

Introduction

• Sequential circuit consists of feedback path and several
memory elements

• Output depends not only on current input but also on past
input values

• Sequential circuit = Combinational Logic + Memory Elements

6

Memory Element

• Memory element device that can remember a
value for a certain period, or change value based
on the input instruction

• Example: Latch and flip-flop

Commands for latches include set and reset
commands

7

Memory Element

• Flip-flop is a memory element which change its condition
based on clock signal

• Clock is a square waveform

8

Memory Element

• There are two types of trigger/activator

• Pulse triggered
• Edge triggered

• Pulse triggered

• Latch
• ON=1, OFF= 0

• Edge triggered

• Flip-flop
• Positive edge triggered (ON=when 0 to 1, OFF=other time)
• Negative edge triggered (ON=when 1 to 0, OFF=other time)

9

Level-sensitive vs Edge-triggered

• Latches are level-sensitive

• Flip-flops are edge-sensitive

SR Latch

• For all S’R’ with active LOW input (also known as
NAND gate latch)
• R = LOW (and S=HIGH) – RESET condition
• S = LOW (and R=HIGH) – SET condition
• Both HIGH – no condition change
• Both LOW - Q and Q’ becomes HIGH (invalid)

11

SR Latch

• Output has complement: Q and Q’
• When Q HIGH, latch in SET condition
• When Q LOW, latch in RESET condition
• For SR with active high input (also known as NOR gate

latch)

• R = HIGH (and S=LOW) – RESET condition
• S = HIGH (and R=LOW) – SET condition
• Both LOW – no condition change
• Both HIGH - Q and Q’ becomes LOW (invalid)

12

SR Latch ( Logic circuit)

• Active LOW input SR latch • Active HIGH input SR latch

SR Latch (Logic symbol)

• Active LOW input SR latch • Active HIGH input SR latch

SR Latch

• SR with active HIGH input

• S’R’ with active LOW input

15

Example

Example

Determine the output of an active HIGH input
SR latch if the waveforms in Figure 7-5 are
inverted and applied to the inputs

SR latch with gate

Example SR latch with gate

D Latch with Gate

• Make input R the same as S’ - D Latch with Gate
• D latch eliminate invalid condition in SR latch

20

D Latch with Gate

• When EN is HIGH

• D=HIGH – latch is in SET
• D=LOW – latch is in RESET

• Therefore, when EN is HIGH, Q will follow input D
• Criteria Table:

21

Example: D Latch with Gate

Flip Flop

23

•Flip-flop
• SR flip-flop
• D flip-flop
• JK flip-flop

24

Edge Triggered Flip-flop

• Flip-flop – bistable synchronous device
• Output change its condition at certain point on input

trigger named clock
• Condition change either at positive edge (up edge) or

at negative edge (down edge) of clock signal

clock signal

Positive Edge Negative Edge

25

Edge Triggered Flip-flop

• flip-flop SR, D and JK edge triggered is marked with
“>” symbol at clock input

Positive edge triggered flip-flop

Negative edge triggered flip-flop

26

SR Flip-flop

• SR flip-flop, at edge triggered clock pulse

• S=HIGH (and R=LOW) – SET condition
• R=HIGH (and S=LOW) – RESET condition
• Both input LOW – no change
• Both input HIGH – invalid

• Criteria table of edge triggered SR flip-flop

27

SR Flip-flop

• It consist of three parts
• NAND latch
• Pulse steering circuit
• Pulse transaction circuit detector (or edge
detector)

• Pulse transaction detector circuit will detect up
trigger (or down) and produce very short duration
spike

28

SR Flip-flop

• Pulse transaction detector

29

Example : SR FF

D Flip-flop

• D flip-flop: one input D (data) is to be stored

• D=HIGH – SET condition
• D=LOW – RESET condition

• Q will follow D at clock edge
• To change SR flip-flop to D flip-flop: add inverter

31

Example: D Flip-flop

D Flip-flop
Remember !!!!!

Q follows D at the active or
triggering clock edge

D Flip-flop

• Usage: Parallel data transaction
To transfer logical output circuit X,Y,Z to Q1, Q2, and Q3
to be stored

34

JK Flip-flop

• J-K FF is versatile and is widely used type of FF.

• The J-K designations for the inputs have no known

significance except they are adjacent letters in the

alphabet.

• The function of J-K FF is identical to the S-R FF in the

SET, RESET and NC conditions.

• The difference is J-K FF has no invalid state condition.

• There is toggle condition

• J=HIGH (and K=LOW) – SET condition

• K=HIGH (and J=LOW) – RESET condition

• Both input LOW – no change

• Both input HIGH – “toggle”

35

Edge Triggered JK Flip-flop

• flip-flop SR, D and JK edge triggered is marked with
“>” symbol at clock input

Positive edge triggered flip-flop

Negative edge triggered flip-flop

36

JK Flip-flop

• JK Flip-flop

• Criteria Table

37



Example : JK Flip flop

Example : JK Flip flop

Example : JK Flip flop

JK FF: Answer Figure 7.25

FLIP-FLOP

• D flip-flop and JK flip-flop are available in IC form and
more widely used than the S-R flip-flop.

• However, understanding the S-R flip-flop is important
because the D and JK flip-flops are derived from the S-R
flip-flop.

• S-R flip-flop differs from the gated S-R latch only in that
it has a pulse transition detector.

•What is the difference between
LATCH and FLIP FLOP ?

T Flip-flop

• T flip-flop single input version for JK flip-flop, formed
by combining JK input

• Criteria Table

44

T Flip-flop

• Usage: As frequency divider

45

Asynchronous Input

• SR input, D and JK is synchronous input. Where
data from input will be transferred to flip-flop
output only when edge triggered of clock pulse

• Asynchronous Input free change condition from
pulse clock. Example: preset (PRE) and clear
(CLR) [or direct set (SD) and direct reset (RD)]

• When PRE=HIGH, Q immediately HIGH
• When CLR=HIGH, Q immediately LOW
• Flip flop function as normal when both PRE and

CLR is LOW

46

Asynchronous Input

• JK flip-flop with active LOW preset and clear

47

Asynchronous Input

Q,D&A
Session

ありがとう
ございました

DFE 1013 MOHD RADZI