Digital Electronics Fundamentals: Sequential Logic

Unit 6: Sequential
Logic

6.5 Shift Registers

Learning Outcome

• Understand and evaluate
the function of shift register.

• Differentiate the types of
shift register.

Shift Register

 Shift registers are constructed using several flip-
flop, connected in such a way to STORE and
TRANSFER digital data.

 Basically, D flip-flop is used. The input data (either
‘0’ or ‘1’) is applied to the D terminal and the data
will be stored at Q during positive/negative-edge
transition of the clock pulse.

positive edge transition of CLK

1 DQ 1

CLK Q

What a shift register
do?

Data Storage Data
Movement

Shift Register

 One D FF is used to store 1-bit of data. Thus, the
number of flip-flops used is the same with the
number of bits stored.

 Shift register mean that the data in each FF can be
transferred/move to other FF upon edge triggering
of the clock signal.

 Four types of data movement in shift register are:-

 Serial In / Serial Out (SISO)

 Serial In / Parallel Out (SIPO)

 Parallel In / Serial Out (PISO)

 Parallel In / Parallel Out (PIPO)

Data Movement

Data Storage

• Each stage (FF) in

a shift register
represents one bit
of storage
capacity

• therefore, the

number of stages
in a register
determines its
storage capacity.

Shift Register

 Serial Data VS Parallel Data movement

Serial Parallel

•Movement of N-bit data •Require only one CLK pulse

require N number of CLK to transfer all N-bit of data.

pulses. Thus, the operation is Thus, operation is faster than

slow. serial.

•Only one FF is required to be •Required N number of

connected at the output connection to the output

terminal, thus only one wire is terminal, which is

required. proportional to the number of

bit. Thus, too many

connection is required.

Serial In / Serial Out
(SISO)

Serial FF0 FF1 FF2 FF3
data
input Q0 Q1 Q2 Q3

CLK Serial
data
output

Step by Step

Serial In / Serial Out

Register initially CLEAR

FF0 0 FF1 0 FF2 0 FF3 Q3

data 0
input

CLK

Data Input = 1 0 1 0

4th 3rd 2nd 1st

Step by Step

Serial In / Serial Out

After CLK1

1st data FF0 0 FF1 0 FF2 0 FF3 Q3
bit = 0
0

CLK1

Step by Step

Serial In / Serial Out

After CLK2

2nd data FF0 1 FF1 0 FF2 0 FF3 Q3
bit = 1
0

CLK2

Step by Step

Serial In / Serial Out

After CLK3

3rd data FF0 0 FF1 1 FF2 0 FF3 Q3
bit = 0
0

CLK3

Step by Step

Serial In / Serial Out

After CLK4

4th data FF0 1 FF1 0 FF2 1 FF3 Q3
bit = 1
0

CLK4

the 4-bit number is completely
stored in register

Step by Step

Serial In / Serial Out

After CLK4 1st
data
bit

FF0 1 FF1 0 FF2 1 FF3 0

0

Q3

CLK

register contains 1010

Step by Step

Serial In / Serial Out

After CLK5 2nd
data
bit

FF0 0 FF1 1 FF2 0 FF3 1

0

Q3

CLK5

Step by Step

Serial In / Serial Out

After CLK6 3rd
data
bit

FF0 0 FF1 0 FF2 1 FF3 0

0

Q3

CLK6

Step by Step

Serial In / Serial Out

After CLK7 4th
data
bit

FF0 0 FF1 0 FF2 0 FF3 1

0

Q3

CLK7

Step by Step

Serial In / Serial Out

After CLK8

FF0 0 FF1 0 FF2 0 FF3 0

0

Q3

CLK8

register is CLEAR

5-bit SISO register

5-bit SISO register

 Show the states of the register if

the data input is inverted. The
register is initially cleared (all 0’s).

Serial In / Parallel Out

Data bits are entered serially (right most bit

first) into the SIPO and same with SISO.

The difference is the way in which the data

bits are taken out of the register; in parallel
output register, the output of each stage is
available.

Once the data stored, each bit appears on its

respective output line and all bits are
available simultaneously rather than one by
one.

Serial In / Parallel Out

data input

CLK

Q0 Q1 Q2 Q3

data input 0 1 1 0

CLK

Q0
Q1
Q2
Q3

Serial In / Parallel Out

If the data input remains 0 after the fourth

clock pulse, what is the state of the register
after three additional clock pulse?

Parallel In / Serial Out

When SHIFT/LOAD is HIGH, data are shifted right
one bit per clock pulse.

When SHIFT/LOAD is LOW, the data on the
parallel inputs are loaded into the register.

Parallel In / Serial Out

Parallel In / Serial Out

Parallel In / Parallel
Out

Student’s Activity

- Please form four group and discuss the
answer for the question given in five (5)
minutes.

- Assign one of the group member to write
down the answer on the whiteboard.

Bidirectional Shift
Registers

Bidirectional Shift
Registers



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