Digital Electronic

Right DIGITAL ELECTRONIC
BOOLEAN OPERATION

Wrong

Example:

2 - variables

X  AB X BA

3 - variables X 1
X  AB

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BOOLEAN OPERATION

4 - variables

X  AB  BD  BD X BD

Karnaugh Map (K-Map) with Don’t Care Condition

Don’t cares in a Karnaugh map, or truth table, may be either 1s or 0s, as long as we don’t care
what the output is for an input condition we never expect to see. We plot these cells with an
asterisk, *, among the normal 1s and 0s.

When forming groups of cells, treat the don’t care cell as either a 1 or a 0, or ignore the don’t
cares. This is helpful if it allows us to form a larger group than would otherwise be possible
without the don’t cares. There is no requirement to group all or any of the don’t cares. Only use
them in a group if it simplifies the logic.

3 variables with output “don’t care condition (X)

Example: 46
Determine the minimal SOP using K-Map:

FA, B,C, D  M 0,2,6,8,9,10D5,12,13,14,15

Z  BC  CD  AD

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DIGITAL ELECTRONIC
BOOLEAN OPERATION

EXERCISE 2

1. The universal gate is __________________.

A. NAND gate C. OR gate

B. NOT gate D. None of the above

2. The inverter is _________________.

A. NOT gate C. OR gate

B. AND gate D. None of the above

3. The inputs of a NAND gate are connected together. The resulting circuit is _______________.

A. OR gate C. AND gate

B. NOT gate D. None of the above

4. The NOR gate is OR gate followed by __________________.

A. AND gate C. NAND gate

B. NOT gate D. None of the above

5. The NAND gate is AND gate followed by ___________________.

A. NOT gate C. OR gate

B. AND gate D. None of the above

6. Digital circuit can be made by the repeated use of ___________________.

A. OR gate C. NOT gate

B. NAND gate D. None of the above

7. The only function of NOT gate is to __________________.
A. Stop a signal
B. Invert input signal
C. Act as a universal gate
D. None of the above

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BOOLEAN OPERATION

8. When an input signal 1 is applied to a NOT gate, the output is ________________.
A. 0
B. 1
C. Either 0 or 1
D. None of the above

9. In Boolean algebra, the bar sign (-) indicates _________________.
A. AND operation
B. OR operation
C. NOT operation
D. None of the above

10. In Boolean algebra, the plus sign (+) indicates ___________________.
A. AND operation
B. OR operation
C. NOT operation
D. None of the above

11. Determine the output equation for the logic circuit shown below.

A. AB  AB
B. AB  AB

 C. AB  A  B

D. AB  AB

12. Identify which of the following expression is the Product of Sum (POS) form. [CLO 2]
A. AB  CD

B. ABCD
C. A  BC  D

D. AB  CD

13. Simplify the following problem using the Karnough maps method.
Z  ABC  ABC  ABC  ABC  ABC  ABC

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14. Simplify the logic circuit below.

15. For each the following expression, construct the corresponding logic circuit using AND
and OR gates and INVERTER.

 a. Z  A  B  CDE  BCD

b. Y  ABC  ABC  ABC

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DIGITAL ELECTRONIC
DATA PROCESSING CICUITS

CHAPTER 3

DATA PROCESSING CIRCUITS

OUTCOMES:
Upon completion of this topic, students should be able to:

1. Describe and understand design of encoders, decoders, multiplexers and demultiplexers

3.1 Data Processing Circuits

The combinational logic circuit obtain binary data and information that are continuously
being operated in some manner. Some of the operations include decoding and encoding,
multiplexing and demultiplexing and arithmetic algorithms.

Figure 3.1 Basic Digital System

3.2 Encoder

An encoder is an electronic device used to convert an analogue signal to a digital signal
such as a BCD code. It has a number of input lines, but only one of the inputs is activated at a
given time and produces an N-bit output code that depends on the activated input. The
encoders and decoders are used in many electronics projects to compress the multiple number
of inputs into smaller number of outputs. The encoder allows 2 power N inputs and generates
N-number of outputs.

Figure 3.2 2n inputs with n-outputs encoder 50
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DATA PROCESSING CICUITS

3.2.1 Encoder with 4-line input to 2-line output

An encoder with 4-line input to 2-line output accepts four input bits and produces two
output bits. Only one input line will be active at a time.

Figure 3.3 4-line input to 2-line output

Table 3.1 Truth table of 4-line input to 2-line output

Input Output
I3 I2 I1 I0 AB
0001 00
0010 01
0100 10
1000 11

Figure 3.4 Logic circuit of 4-line input to 2-line output

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3.2.2 Decimal – to – BCD Encoder

The decimal – to – binary encoder accepts 10 inputs and provides 4 outputs. Applied same
principle as before, where only one input line will be active at a time.

Figure 3.5 Decimal - to - BCD encoder

Decimal Table 3.2 Truth table of Decimal – to - BCD encoder A Output D
Input 0 BC 0
0 0 00 1
1 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 0 00 0
2 0 0 0 0 0 0 0 0 01 0 01 1
3 0 0 0 0 0 0 0 0 10 0 01 0
4 0 0 0 0 0 0 0 1 00 0 10 1
5 0 0 0 0 0 0 1 0 00 0 10 0
6 0 0 0 0 0 1 0 0 00 0 11 1
7 0 0 0 0 1 0 0 0 00 1 11 0
8 0 0 0 1 0 0 0 0 00 1 00 1
9 0 0 1 0 0 0 0 0 00 00
0 1 0 0 0 0 0 0 00
1 0 0 0 0 0 0 0 00

Figure 3.6 Logic circuit of Decimal - to - BCD encoder 52
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DATA PROCESSING CICUITS

Example:

Draw the truth table and logic circuit for 8 to 3 line encoder.

Answer:

Truth table:

Input Output

I7 I6 I5 I4 I3 I2 I1 I0 A B C

00000001000

00000010001

00000100010

00001000011

00010000100

00100000101

01000000110

10000000111

Logic circuit:

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3.3 Decoder

A decoder is a logic circuit with a multiple inputs and outputs that converts coded inputs
into coded outputs, where the input and outputs codes are different. Commonly, a decoder
circuit looks at its input and actives the output that corresponds to the binary input, while other
outputs remain inactive. Only one of the n-outputs will be active at once. Some of the decoder
circuits have an ‘enable’ input to control the operation of the decoder.

Figure 3.7 n-inputs with 2n-outputs decoder

3.3.1 Decoder with 2-line inputs to 4-line outputs

The decoder with 2-line inputs to 4-line outputs accepts 2 inputs and provides 4 outputs.
Only one output will be activated at a time.

Figure 3.8 2-line inputs with 4-line outputs decoder

Table 3.3 Truth table of 2-line inputs with 4-line outputs decoder

Input Output

I1 I0 D C B A

000001

010010

100100

111000

Figure 3.9 Logic circuit of 2-line inputs with 4-line outputs decoder 54
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DATA PROCESSING CICUITS

3.3.2 Decoder with 3-line inputs to 8-line outputs

The decoder with 3-line inputs to 8-line outputs accepts 3 inputs and provides 8 outputs.
Same principle as previous, only one output will be activated at a time.

Figure 3.10 3-line inputs with 8-line outputs decoder

Table 3.4 Truth table of 3-line inputs with 8-line outputs decoder

Input Output

I2 I1 I0 H G F E D C B A

0 00 0 0 0 0 0 0 01

0 01 0 0 0 0 0 0 10

0 10 0 0 0 0 0 1 00

0 11 0 0 0 0 1 0 00

1 00 0 0 0 1 0 0 00

1 01 0 0 1 0 0 0 00

1 10 0 1 0 0 0 0 00

1 11 1 0 0 0 0 0 00

Figure 3.11 Logic circuit of 3-line inputs with 8-line outputs decoder

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3.3.3 Decoder 7-Segment Display

Digital display devices such as digital clock, calculator and mobile phone use multi-
segment display (7–segment display). It uses a decoder for decoding the binary data to the
multi-segment display.

The 74LS47 is an example of an IC device that accepts a BCD code on its inputs and provides
outputs to drive 7 segment displays devices to produce a decimal readout. Here, the decoder
utilized only certain input codes, and not all of the 2 possible input codes.

Figure 3.12 Internal connection of 74LS74 to set of LED display

Table 3.5 Truth table for 7 - Segment Display

Decimal Input Output

0 D CBAab c d e f g
1 0 on on off
2 0 0 0 0 on on on on off off off
3 0 on off on
4 0 0 0 1 off on on off off off on
5 0 off on on
6 0 0 1 0 on on off on off on on
7 0 on on on
8 0 0 1 1 on on on on off off off
9 1 on on on
1 1 0 0 off on on off off on on

1 0 1 on off on on

1 1 0 on off on on

1 1 1 on on on off

0 0 0 on on on on

0 0 1 on on on off

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DATA PROCESSING CICUITS

3.4 Multiplexer

A modern home stereo system may have a switch that selects music from one of four
sources: a cassette tape, a compact disc (CD), a radio tuner, or an auxiliary input such as audio
from a VCR or DVD. The switch selects one of the electronic signals from one of these four
sources and sends it to the power amplifier and speakers. In simple terms, this is what a
multiplexer (MUX) does: it selects one of several input signals and passes it on to the output.

A digital multiplexer or data selector is a logic circuit that accepts several digital data inputs and
selects one of them at any given time to pass on to the output. The routing of the desired data
input to the output is controlled by SELECT input.

Figure 3.13 Functional diagram of a digital multiplexer (MUX)

The inputs and outputs are drawn as wide arrows rather than lines; this indicates that they may
actually be more than one signal line. The multiplexer acts like a digitally controlled multi-
position switch where the digital code applied to the SELECT inputs controls which data inputs
will be switched to the output. For example, output Z will equal data input for some particular
SELECT input code, Z will equal for another particular SELECT input code, and so on. Stated
another way, a multiplexer selects 1 out of N input data sources and transmits the selected data
to a single output channel. This is called multiplexing.

Figure 3.14 Basic block diagram of the Multiplexer 57
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DATA PROCESSING CICUITS

3.4.1 Multiplexer with 4-line input to 1-line output

A multiplexer with four inputs and one selector line, used to select which input line to
send to the output.

Figure 3.15 4-line inputs to 1-line output Multiplexer

Table 3.6 Truth table for 4-to-1 Multiplexer

Input Selector
S1 S0
D0 00
D1 01
D2 10
D3 11

Figure 3.16 Logic circuit of 4-to-1 Multiplexer

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Example:

Draw the truth table and logic circuit for 8 to 1 line multiplexer.

Answer:

Truth table: S2 Selector S0
0 S1 0
Input 0 0 1
0 0 0
D0 0 1 1
D1 1 1 0
D2 1 0 1
D3 1 0 0
D4 1 1 1
D5 1
D6
D7

Logic Circuit:

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DATA PROCESSING CICUITS

3.5 Demultiplexer

A multiplexer takes several inputs and transmits one of them to the output. A
demultiplexer (DEMUX) performs the reverse operation: it takes a single input and distributes
it over several outputs. The large arrows for inputs and outputs can represent one or more
lines. The select input code determines to which output the DATA input will be transmitted. In
other words, the demultiplexer takes one input data source and selectively distributes it to 1 of
N output channels just like a multi-position switch.

Figure 3.17 General Demultiplexer

Figure 3.18 1-line input to 4-line outputs Demultiplexer

Table 3.7 Truth table for 1-to-4 Demultiplexer

Selector Output
S1 S0
00 D0
01 D1
10 D2
11 D3

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Figure 3.19 Logic circuit of 1-line input to 4-line outputs Demultiplexer

Example:

Construct a demultiplexer circuit 1 line to 8 line along with the truth table.

Answer:

Truth table:

Selector Output

S2 S1 S0 D0
00 0 D1
D2
00 1 D3
D4
01 0 D5
D6
01 1 D7

10 0

10 1

11 0

11 1

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DATA PROCESSING CICUITS

Logic circuit:

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EXERCISE 3

1. All the statement given are true EXCEPT

A. Encoder is used to generate a coded input (such as BCD or binary) from a singular
active numeric input line

B. Decoder is the process of converting some code (such as binary, BCD or HEX)
into a singular active output representing its numeric value.

C. Multiplexer is known as a data distributor that allows digital information from
several sources to be routed onto a single line for transmission.

D. Demultiplexer takes a single input data value and routes it to one several output.

2. State the function of encoder

3. Draw the truth table and logic circuit for 2 to 4 line decoder.

4. State two examples where a binary to decimal decoder can be used

5. Draw the logic circuit for:

a. 2 to 4-line multiplexer
b. 1-line to 4-line demultiplexer

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DIGITAL ELECTRONIC
FLIP FLOPS

CHAPTER 4

FLIP FLOPS

OUTCOMES:
Upon completion of this topic, students should be able to:

1. Know types of flip-flops.
2. Understand the operation of each types of flip-flop.
3. Apply JK flip-flops to construct T flip-flop and D flip-flop.

4.0 Introduction

General digital system consists of both combinational circuits and memory elements as
shown in Figure 4.1.

Figure 4.1 General digital system diagram

The memory elements are devices capable of storing binary data (either bit 1 or bit 0) and will
be discussed in this chapter. This memory element contain of flip-flops which are made up of an
assembly of logic gates. The arrangements of the logic gates are used to produce these types of
flip-flops that permit data to be stored.

4.1 Latches

Latches and flip-flops are the basic elements for storing data. The main difference
between them, is that for latches output is constantly affected by the input. On the other hand,
flip-flops output will only change when the clock signal is changed. The most basic latches can
be constructed using two NAND gates or two NOR gates, which also known as SR flip-flop
(without clock pin).

i. SR flip-flop active LOW = 2 NAND gates
ii. SR flip-flop active HIGH = 2 NOR gates

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Generally, latch is a basic SR flip-flop, which the outputs is immediately changed anytime
one or more of the inputs change just as in combinational logic circuits and does not
operate in step with clock or timing signal.

4.1.1 NAND Gate Latch

Figure 4.2 shows a NAND latch that are cross-coupled, the feedback mechanism is
required to form a sequential circuit by connecting the output of first NAND gate to the input of
second NAND gate and vice versa.

This circuit has two inputs, SET and RESET. The SET input is the input that set the output Q to 1
state, while the RESET input is the input that reset Q output to 0 state. The gate output Q and
are the output which will always be inverse if each other under a normal condition.

Figure 4.2 NAND Latch (Active LOW)

The operation of NAND latch can be summarized in truth table in Table 4.1.

Table 4.1 Truth table for NAND latch

SET RESET Output Description

0 0 Invalid This condition tries to set and reset the NAND latch ate the
condition same time, which produces Q = = 1. This unexpected

condition is INVALID since the two outputs should be inverses
of each other.

01 1 This condition will always cause the output Q = 1 state and will
remain even after the SET return to HIGH. This is called as SET

mode operation.

10 0 This condition will always cause the output Q = 0 state and will

remain after RESET returns to HIGH. This is called as RESET
mode operation

11 No This condition is the normal resting state, and I has no effect of
change the output states. This is called as HOLD mode operation.

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4.1.1 NOR Gate Latch

Figure 4.3 shows a NOR latch that are cross-coupled, the gate arrangement is similar to
NAND latch but constructed using NOR gates. However, the normal output Q and inverted
output have reversed position.

Figure 4.3 NOR Latch (Active HIGH)

The operation of NOR latch can be summarized in truth table in Table 4.2.

Table 4.2 Truth table for NOR latch

SET RESET Output Description

00 No This condition is the normal resting state, and I has no effect of

change the output states. This is called as HOLD mode operation.

01 0 This condition will always cause the output Q = 0 state and will
remain after RESET returns to HIGH. This is called as RESET

mode operation

10 1 This condition will always cause the output Q = 1 state and will

remain even after the SET return to HIGH. This is called as SET
mode operation.

1 1 Invalid This condition tries to set and reset the NAND latch ate the
condition same time, which produces Q = = 1. This unexpected

condition is INVALID since the two outputs should be inverses

of each other.

4.2 Flip-flop

In digital circuit, flip-flop is a kind of bistable multivibrator and also can be known as
sequential circuit. However, flip-flop can be defined as an electronic circuit which has two stable
states and thereby is capable of serving as one bit of memory ( can store data either bit 1 or bit
0).

These stable condition usually called the states of circuit, either bit 1 = HIGH, or bit 0 = LOW.
The state of flip-flop can refer to the state of its normal output (Q).

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Figure 4.4 Block Diagram for flip-flop

Basically, flip-flops are the basic elements of storing data / information (either bit 1 or bit 0).
One flip-flop can store one bit of data and the content data will only change either at the rising
or falling edge of the clock signal.

Other than that, flip-flop also can also be served as memory circuits, logic control devices,
counter devices and register devices.

There are four main types of flip-flops: SR, JK, T and D. The major differences in these flip-flops
are the number of inputs they have and how they change state. For each type, there are also
different variations that enhance their operation.

4.3 Clock Signal

The exact time at which output can change their state are determined by a timing signal
commonly called as clock. The clock signal applied to flip-flop is generally in a square wave.
Most of the outputs can change state only when the clock signal is either positive edge transition
or negative edge transition.

Positive edge transition (PGT) is the transition from LOW state to a HIGH state. While, negative
edge transition (NGT) is the transition from HIGH state to LOW state. The time taken to
accomplish one cycle is called period (T).

T 67
(b) Positive edge transition (PGT)

T
(b) Negative edge transition (NGT)
Figure 4.5 Clock signal with PGT and NGT

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FLIP FLOPS

The difference of between PGT and NGT on the clocked flip-flop can be differentiate by the use
of a bubble. The control input will have no effect on Q until the active clock transition occurs.

4.4 Clocked Flip-flops

The principle ideas of clocked flip-flop are common to all flip-flops, which shows in Figure
4.6.

1. The clocked flip-flops must have a clock input (labelled as CLK, CK or E).
2. The clock input is triggered, which means that it is activated by signal transition.
3. The use of a bubble on clock input indicates that transition is NGT, otherwise

transition is PGT.
4. The control input can only control the outcome of output, but the clock input

determine when it will occur.

PGT NGT

Figure 4.6 Basic features of clocked flip-flop

4.5 SR Flip-flop

Figure 4.7 shows the circuit for SR flip-flop with clock signal, labelled as CLK is triggered
by PGT. Its means that the flip-flop can change the output state only when the clock signal
makes a transition from LOW to HIGH (PGT).

Figure 4.7 Clocked SR flip-flop

The operation of SR flip-flop with PGT can be summarized in truth table in Table 4.3 while the
waveform that illustrate the operation of SR flip-flop is given in Figure 4.8.

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CLK S R Q Table 4.3 Truth table for SR flip-flop with PGT
1 00Q
Description
1 010
The input S = R = 0, resulting the output of Q remaining unchanged,
1 101 HOLD mode.
1 The input S = 0 and R = 1, resulting the output Q = 0. The flip-flop is
1 110 in RESET mode.
0 The input S = 1 and R = 0, resulting the output Q = 1. The flip-flop is
in SET mode
0 The input S = R = 0, resulting the output Q and trying to become
1, which is impossible.

Given that, initially the output Q = 1.

Figure 4.8 SR flip-flop with PGT waveform
PGT NGT

Figure 4.9 Symbol of SR flip-flop

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Example:
Determine the output of PGT clocked SR flip-flop which Q initially 0 for the given input
waveform. What if the NGT is applied to clock SR flip-flop? Draw the waveform.

Answer:
PGT waveform:

NGT waveform:

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4.6 JK Flip-flop

The operational of JK flip-flop is similar to SR flip-flop, except there is one major
difference, when J=K=1, the flip-flop will go to its opposite state instead of becoming invalid
state. Figure 4.10 shows JK flip-flop logic circuit and its corresponding truth table is listed in
Table 4.4.

Figure 4.10 JK flip-flop

Table 4.4 Truth table for JK flip-flop with PGT

CLK J K Q Description

1 00 Q The input J = K = 0, resulting the output of Q remaining unchanged,

HOLD mode.

1 0 1 0 1 The input J = 0 and K = 1, resulting the output Q = 0. The flip-flop is

in RESET mode.

1 1 0 1 0 The input J = 1 and K = 0, resulting the output Q = 1. The flip-flop is

in SET mode.

1 1 1 Toggle The input J = K = 1, resulting the output Q become toggle.

Given that, initially the output Q = 1.

Figure 4.11 JK flip-flop with PGT waveform 71
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PGT NGT

Figure 4.12 Symbol of JK flip-flop
Example:
Determine the output of PGT clocked JK flip flop for the given input waveforms which the output
Q initially 0.

Answer:

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4.7 Flip-flop with Asynchronous Input

In previous discussion of the flip-flop triggering edge, all the inputs S, R, J and K will
impact the flip-flop simultaneously with the firing time. Therefore, all the inputs are refer as
feedback control or synchronous input.

In some applications, the initial output of the flip-flop should be fixed, either 0 or 1. However,
this application cannot been done by using the flip-flop with the firing time. Thus, there is a
need of using an additional input to reset or set the output.

This additional input is an asynchronous input as preset (PRE) and clear (CLR) inputs is more
dominant compared with synchronous and clock input. Where it can change the state of the flip-
flop without relying on synchronous and clock input.

Figure 4.13 Symbol of SR flip-flop and JK flip-flop with PRE and CLR

Table 4.5 shows the JK flip-flop operational with PRE and CLR.

Table 4.5 Truth table for JK flip-flop with PRE and CLR

JK Q PRE CLR Q

00 No change 00 Disallowed
01 01 01 10
10 10 10 01
11 11
Toggle Clocked

Clocked JK Flip-flop Direct JK Flip-flop (with PRE and CLR)

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The output of clocked JK flip flop which output initially 0 for the given input waveforms.

Figure 4.14 JK flip-flop with PRE and CLR waveform
Example:
The output of clocked JK flip flop which output initially 0 for the given input waveforms.

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Answer:

4.8 D Flip-flop

D flip-flop is also known as data flip-flop because of its ability to store data for a single
binary digit (Bit). The D flip-flop has only one input in addition to the clock input; which means
that the flip-flop output can change when the clock is triggered.

Figure 4.15 D flip-flop

The operation of D flip-flop with PGT can be summarized in truth table in Table 4.6 while the
waveform that illustrate the operation of D flip-flop is given in Figure 4.16.

CLK D Q Table 4.6 Truth table for D flip-flop with PGT
1 00
Description
1 11
1 The input D = 0, resulting the output Q = 0. The flip-flop is in RESET
mode.

0 The input D = 1, resulting the output Q = 1. The flip-flop is in SET
mode.

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Given that, initially the output Q = 1.

Figure 4.16 D flip-flop with PGT waveform
PGT NGT

Figure 4.17 Symbol of D flip-flop
D flip-flop can also be constructed by using SR and JK flip-flop by addition of an inverter.
Inverter is connected so that the R input is always the inverse of S (or J input is always
complementary of K).

Figure 4.18 Construction of D flip-flop by using SR flip-flop

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FLIP FLOPS

Example:
Determine the output of NGT clocked D flip-flop which Q initially 0 for the given input
waveform.

Answer:
NGT waveform:

4.9 T Flip-flop

T flip-flop often used in counter circuit design and the operation of T flip-flop is different
than D flip-flop. The T flip flop has only the Toggle and Hold Operation. If Toggle mode
operation. The output will toggle from 1 to 0 or vice versa.

Figure 4.19 T flip-flop 77
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FLIP FLOPS

The operation of D flip-flop with PGT can be summarized in truth table in Table 4.7 while the
waveform that illustrate the operation of D flip-flop is given in Figure 4.20.

Table 4.7 Truth table for T flip-flop with PGT

CLK T Q Description

1 0Q The input T = 0, resulting the output of Q remaining unchanged,
HOLD mode.

11 Q The input T = 0, resulting the output of Q will becoming opposite
state, TOGGLE mode.

Given that, initially the output Q = 1.

Figure 4.20 T flip-flop with PGT waveform
PGT NGT

Figure 4.21 Symbol of T flip-flop
T flip-flop can also be constructed by using SR and JK flip-flop by shorted the two inputs.

Figure 4.22 Construction of T flip-flop by using SR flip-flop 78
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DIGITAL ELECTRONIC
FLIP FLOPS

Example:
Determine the output of NGT clocked T flip-flop which Q initially 1 for the given input
waveform.

Answer:
NGT waveform:

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FLIP FLOPS

Summary of flip-flops Truth Table

Name/ Symbol

CLK S R Q

1 0 0 No change

10101

11010

111 Invalid

CLK J KQ

1 0 0 No change

10101

11010

111 Toggle

CLK D Q

1001

1110

CLK D Q

10 No change
11 Toggle

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FLIP FLOPS

EXERCISE 4

1. Determine the output Q of PGT clocked SR flip flop which Q initially 1 for the given input
waveform.

Figure A1
2. Draw the output waveform, Q and for JK flip-flop positive edge trigger in Figure A2.

Assume Qinitial = 0.

Figure A2
3. Draw the output Q of clocked JK flip flop which output initially 0 for the given input

waveforms.

Figure A3 81
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FLIP FLOPS

4. Determine the output of PGT T flip flop for the given input waveforms which the Q
initially 0.

Figure A4
5. Determine the output of NGT D flip flop for the given input waveforms which the Q

initially 0.

Figure A5

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COUNTERS

CHAPTER 5

COUNTERS

OUTCOMES:
Upon completion of this topic, students should be able to:

1. Understand the basic concept of asynchronous and synchronous counters and the
difference between them.

2. Apply the principles of asynchronous and synchronous counter design.
3. Design asynchronous and synchronous counter.

5.0 Introduction

Digital counter is important to the subsystem in the digital system. It has triggering clock
which occur at interval that are known. Therefore, the counter can be used for measuring of
time and frequency. It is also used in computer, digital clock, digital to analog converter,
frequency divider and other digital system.

5.1 Counters

A counter is a sequential logic circuit consisting of a set of flip-flops which can go through
a sequence of states. Counters are formed by connecting several flip-flops together such as by
using JK and T flip-flop. The number of flip-flop used and the way they connected can determine
the number of states and the sequence of the states that the counter will go through in each
complete cycle.

Counter can be broadly divided into synchronous and asynchronous types.
i. Asynchronous counter: is also known as ripple counter. The first flip-flop is driven
by clock pulse while the successive flip-flops by the output of preceding flip-flop.
ii. Synchronous counter: All flip-flops are simultaneously driven by common clock
pulse.

5.1.1 Modulus (MOD)

Modulus can be defined as to the number of states that the counter goes through in each
complete cycle before it recycles back to its starting state. The number of states or MOD number
can be increase by simply adding more flip-flops to the counter. Means that, the number of flip-
flop used is depend on MOD of counter.

MOD  2N

N = number of bits or number of flip-flop used

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5.2 Asynchronous Counter

As mentioned previously, asynchronous counter is also referred as ripple counter. Ripple
counters are the simplest type of binary counters because they require the fewest components
to produce a given counting operation.

Clock pulse is only applied to the first flip-flop and the output of one flip-flop drives the clocked
of the next flip-flop. Hence, the changing states of the flip-flops within the counter are at
different time since their do not have a common clock pulse. Figure 5.1 shows a 2-bit
asynchronous up and down counter with PGT.

FF0 FF1

FF0 FF0
FF1 FF1

UP COUNTER

FF0 FF1

FF0 FF0
FF1 FF1

DOWN COUNTER

Figure 5.1 A 2-bit asynchronous counter with PGT

In Figure 5.1, the external clock pulse is connected to the clock input of the first flip-flop (FF0)
only. FF0 changes state at the rising edge of each clock pulse. However, FF1 can only changes
state when triggered by rising edge of the output Q of FF0.

Due to inherent propagation delay, the transition of clock pulse and the transition of the output
Q of FF0 will never occur at exactly the same time. Therefore, the flip-flops cannot be triggered
simultaneously; resulting an asynchronous operation.

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Figure 5.2 A timing diagram of a 2-bit asynchronous up counter with PGT
As shown in Figure 5.2, FF1 must wait for FF0 to change state before it can toggle, and so on.
Although, an asynchronous counter is known as the simplest binary counter, it’s still have a few
weaknesses such as:

i. Propagation delay is severe for larger MOD of counters especially at the MSB.

Figure 5.3 A propagation delay (tPLH)

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COUNTERS

ii. Existence of glitch is inevitable for MOD≠2N.

Glitch will affected the
next flip-flop

Figure 5.4 Existence of glitch
iii. Asynchronous counter are not useful at a very high frequencies, especially for counter

with larger number of bits
iv. Cannot design random counters (random number sequences i.e. 23417).

5.2.1 Design an Asynchronous Counter (MOD = 2N)

Design an asynchronous up counter of MOD – 8 by using JK flip-flop with negative edge
triggered.
1. Determine number of FF used:

2. Draw state diagram: 0 1
9 2
7
6

53
4

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3. Construct state table:

Qn (Present state) Qn+1 (Next State)
Q2 Q1 Q0 Q2 Q1 Q0
000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000

4. Draw the counter circuit and timing diagram:

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5.2.2 Design an Asynchronous Counter (MOD ≠ 2N)

Design an asynchronous up counter of MOD – 6 by using JK flip-flop with positive edge
triggered.

1. Determine number of FF used:

 Must use 3FF

2. Draw state diagram: 0 1
9
6

5 2
4 3

3. Construct state table:

Qn (Present state) Qn+1 (Next State) Note: Reset the state to
Q2 Q1 Q0 Q2 Q1 Q0 000 after 110 is detected
000 001
001 010
010 011
011 100
100 101
101 110
110 000

The HIGH state can be reset to LOW
state by connecting it to NAND gate

Q2 & Q1 is connected to NAND gate and the output of NAND gate is connected to all CLR pin of
flip-flops.

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4. Draw the counter circuit and timing diagram:

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5.2.3 Asynchronous Up-Down Counter

In certain application, a counter must be able to count both up and down. Figure 5.5
shows the circuit of 3 bit asynchronous counter that counts up or down depending on the given
control signals of either UP or DOWN.

Figure 5.5 3 bit asynchronous up-down counter

When the control input of UP = 1 and the DOWN = 0, the NAND network between FF0 and FF1
will gate the non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, the output Q of
FF1 will be gated through the other NAND network into the clock input of FF2. Thus the counter
will count up.
Next, when the control input of UP = 0 and DOWN = 1, the inverted outputs of FF0 and FF1 are
gated into the clock inputs of FF1 and FF2 respectively. Thus the counter will count down. If the
flip-flops are initially reset to 0's, then the counter will go through the following sequence as
input pulses are applied.
Note that, this counter is slower than conventional asynchronous counter because of the
additional propagation delay introduced by the NAND gate networks

5.2.4 Asynchronous Counter as Frequency Divider

Asynchronous counter can also act as frequency divider to reduce a high clock frequency
for use in timing applications. For counters, the output signal from the last flip-flop will be
having a frequency that equal to the input clock frequency divided by the MOD number of the
counter.

fout  f in  f in
MOD 2N

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Figure 5.6 shows MOD 2 JK flip-flop as frequency divider device that divides the input frequency
by 2.

TT

T
Figure 5.6 JK flip-flop as frequency divider

Example:
Calculate the output frequency for 5 bits asynchronous counter if the input frequency is 15 kHz.

Answer:

fout  fin
2N

fout  15 103  468.75Hz
25

Example:
Determine the MOD number of the counter in below figure. Also determine the frequency at the
D output.

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Answer: DIGITAL ELECTRONIC
COUNTERS

1110

MOD number: Frequency at output D:

11102  decimal 1410 fout  fin  30k  2.143kHz
MOD  14 MOD  number 14

5.3 Synchronous Counter

Synchronous counter is also known as parallel counter because the clock inputs of all flip-
flops are connected together and are triggered by the same common input pulse. Thus, all the
flip-flops changes their state simultaneously with no ripple.

Synchronous counter can overcome the problem that exist in asynchronous counter. It able to
eliminate the propagation delay problem because all the clock inputs (CLK) are tied to a
common clock. Besides that, synchronous counter can operate at higher clock frequencies and
design random sequence counter. However, synchronous counter requires more circuitry than
the asynchronous counterpart.

UP COUNTER 92
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DOWN COUNTER
Figure 5.7 A 2-bit synchronous counter with PGT

5.3.1 Design a Synchronous Counter

Design a MOD-8 synchronous up-counter, using JK flip-flop with positive edge triggered.
1. Determine number of FF used:

2. Draw state diagram: 1
2
0
79 3

6

5
4

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3. Construct state table by using excitation table:

Excitation table:

Present state Next state
S R J KDT

Qn Qn+1
0 0 0X0X00
0 1 101X11
1 0 01X101
1 1 X0X010

State table:

Present State Next State Flip-flop Inputs
Qn Qn+1

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 00 0X 0X 1X
0 01 00 1 0X 1X X1
0 10 0X X0 1X
0 11 01 0 1X X1 X1
1 00 X0 0X 1X
1 01 01 1 X0 1X X1
1 10 X0 X0 1X
1 11 10 0 X1 X1 X1

10 1

11 0

11 1

00 0

4. Simplified K-Map and obtain the equation:

J 2  Q1Q0 J1  Q0 J0 1

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