Digital Electronic

DIGITAL ELECTRONIC
COUNTERS

K2  Q1Q0 K1  Q0 K0 1

5. Draw the counter circuit:

5.3.2 Design a Random Synchronous Counter

Design a random synchronous counter to count 4,7,3,0 and 2 respectively using JK flip-
flop negative edge triggered.

1. Determine number of FF used:

 Sequence: 0, 1, 2, 3, 4, 5, 6, 7

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2. Draw state diagram:

4 7
0 1
29
4

03
32

3. Construct state table by using excitation table:

Excitation table:

Present state Next state
SRJ KDT

Qn Qn+1
0 0 0X0X00
0 1 101X11
1 0 01X1 01
1 1 X0X0 10

State table:

Present State Next State Flip-flop Inputs
Qn Qn+1

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
1 00 X0 1X 1X
11 1 X1 X0 X0
1 11 0X X1 X1
01 1 0X 1X 0X
0 11 1X X1 0X
00 0
0 00
01 0
0 10
10 0

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4. Simplified K-Map and obtain the equation:

J 2  Q0Q1 J1  1 J 0  Q2

K2  Q1 K1  Q2 K0  Q2

5. Draw the counter circuit:

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5.4 Asynchronous Cascade Counter

Cascade counter can be built by connecting counter in cascade to achieve higher
modulus operation where the last output of counter drives the input of next counter.

Figure 5.8 shows two asynchronous counters connected in cascade for a 2 bit and a 3 bit ripple
counter. The overall modulus of the two cascaded counters is 4 x 8 = 32; that is they act as a
divide-by-32 counter. Note that the MOD number is raised by 2 to the number of output: 25 = 32.

23

CLK MOD-4 MOD-8

MOD 4 Counter MOD 8 Counter

Figure 5.8 MOD 32 counter

5.5 Synchronous Cascade Counter

Cascade synchronous counter is also possible in order to achieve a higher modulus
counter. In synchronous cascaded counter, it is necessary to use the count enable (CTEN) and
the terminal count (TC) functions to achieve higher modulus operation. Terminal count (TC) is
analogous to ripple clock or ripple carry out (RCO) on some IC counters.

Figure 5.9 2 decade counter connected in cascade 98
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The terminal count (TC) output of counter 1 is connected to the count enable (CTEN) input of
counter 2. Counter 2 is in disabled state until counter 1 is reaches its last terminal count output
of HIGH state, which then enables counter 2.

Since both counters is decade counter, counter 1 must perform 10 complete cycles before
counter 2 can complete its first cycle. In other word, for every 10 cycles of counter 1, counter 2
goes through 1 cycle. Thus, the overall modulus of two cascade counters is 10 x 10 = 100

5.6 Application of Counter in Digital Clock

The most popular application of counter, especially cascade counter is implementation as
a digital clock. Figure 5.10 shows a logic diagram of a digital clock that.

The system is supplied with 60Hz pulse as a clock input, which later will be divided to 1Hz pulse
by 60 counter divider. This 1 Hz will becomes clock input for both second and minutes counters
because both counter must be reset after 60 count (0-59).

After 60 seconds count of seconds counter, it will enable minutes counter. For each 60 second
count, minutes counter can complete it 1 minutes until it reaches 60 minutes count to reset back
and enable hours counter. The hours counter uses the same procedure to immediately reset
after reaching the value of 24 hours counts.

Figure 5.10 Logic diagram of digital clock 99
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Example:
The figure below shows a mod-10 counter and mod-8 counter connected in cascade. What is the
overall modulus of these two cascaded counter? Determine the frequency at B if fin is 20 kHz.

AB

Answer: Frequency at B:
Overall modulus:
fB  fin  20k  250Hz
MOD  108  80 MOD 80

Example:
How many decade counters are required to convert a clock of 1 MHz to 1 Hz? Draw the circuit.

Answer:

Total decade counter:

fout  f in
10n

110 6
10n
1 

n  log(1106 )  6
log10

Circuit:

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EXERCISE 5

1. Calculate the number of flip-flop for MOD 10 counter.

2. Design an asynchronous up counter of MOD 5 by using JK flip-flop with negative edge
triggered.

3. From Figure A, develop the truth table, state diagram and then state the modulus (MOD)
of the counter. Next, determine output frequency of each flip flop if the input frequency is
100 kHz.

Figure A

4. Design a random counter to count in the following sequence: 6, 4, 2, 3, 1 using T flip-flop
with positive edge triggered.

5. A MOD-12 and a MOD-10 counter are cascade. Determine the output frequency if the
input clock frequency is 60 MHz.

6. Determine the overall modulus of the two cascaded counter for (a) and (b):

Figure B 101
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DIGITAL ELECTRONIC
REGISTERS

CHAPTER 6

REGISTERS

OUTCOMES:
Upon completion of this topic, students should be able to:

1. Describe the register and shift register
2. Describe the applications of shift register
3. Interpret the operation and circuit of shift registers
4. Interpret the operation and application of an integrated circuits shift registers
5. Explain the application of shift registers as arithmetic circuits
6. Explain the operations and application of shift registers counter.

6.0 Introduction

Shift registers are widely used in data transmission systems. Similarly, in the system of
data transmission, the shift registers are used as temporary memory before the data is sent
elsewhere at any destination. It also serves to convert parallel data to serial form or vice versa
according to the needs of our system.

Figure 6.1 Data Transmission System

Data processed by the computer in the form of parallel. When data is to be transmitted over a
telephone line it will be delivered in the series. Likewise, if the data from the phone line is sent
to the computer, the data you enter in this series should be converted in parallel before being
read by a computer. To convert parallel data to serial form or vice versa, the interface circuit is
required. This interface circuit is built from the registers.

6.1 Shift Register

The Shift Register is another type of sequential logic circuit that is used for the storage or
transfer of data in the form of binary numbers. This sequential device loads the data present on
its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name “shift
register”.

Shift Register can be defined as a device or group of flip-flops are used to store and shift the
data. Shift register are often used as temporary memory before the arithmetic operation
performed.

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The shift register is a device that can store and shift the data, so the suitable flip-flop that can be
used is the D flip-flop. As we have learned previously a D flip-flop can store one bit of data either
bit 0 or 1 depending on input given.

Figure 6.2 D Flip-flop used as a storage elements

Refer to Figure 6.2, we find that when the first bit of the input, after the clock pulse provided the
first data will be stored, as well as bit 0 of the input, then the 0 data will be stored.

A shift register basically consists of several single bit “D-Type Data Latches”, one for each data
bit, either a logic “0″ or a “1″, connected together in a serial so that the output from one data
latch becomes the input of the next latch and so on.

The data bits may be fed in or out of a shift register serially, that is one after the other from
either the left or the right direction, or all together at the same time in parallel. The number of
individual data latches required to make up a single Shift Register device is usually determined
by the number of bits to be stored with the most common being 8-bits (one byte) wide
constructed from eight individual data latches.

The Shift Register is used for data storage or data movement and are used in calculators or
computers to store data such as two binary numbers before they are added together, or to
convert the data from either a serial to parallel or parallel to serial format. The individual data
latches that make up a single shift register are all driven by a common clock signal making them
synchronous devices.

Figure 6.3 Directional movement of the data through a shift register

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Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four the basic
movement of data are:

Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a
time, with the stored data being available in parallel form.

Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the register,
one bit at a time in either a left or right direction under clock control.

Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.

Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.

Figure 6.4 Four basic data movement in shift register

6.2 Types of Shift Registers

6.2.1 Serial In / Serial Out (SISO)

A basic four-bit shift register can be constructed using four D flip-flops, as shown below.
The operation of the circuit is shown in Table 6.1. The register is first cleared, forcing all four
outputs to zero. The input data is then applied sequentially to the D input of the first flip-flop on
the left (FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data
word to be 1001. The least significant bit of the data has to be shifted through the register from
FF0 to FF3.

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Figure 6.5 4-bit SISO shift register

Assume data input: 1001

Table 6.1 Operation of 4-bit SISO (non-destructive)

Q0 Q1 Q2 Q3

CLEAR 0 0 0 0

Shift #1 1 0 0 0 0

Shift #2 0 1 0 0 00

Shift #3 0 0 1 0 00

Shift #4 1 0 0 1 0000

In order to get the data out of the register, they must be shifted out serially. This can be done
destructively or non-destructively. For destructive readout as shown in Table 6.2, the original
data is lost and at the end of the read cycle, all flip-flops are reset to zero.

Table 6.2 Operation of 4-bit SISO (destructive)

Q0 Q1 Q2 Q3

DATA 1 0 0 1

Shift #1 0 1 0 0 1
01
Shift #2 0 0 1 0
001
Shift #3 0 0 0 1 1001

Shift #4 0 0 0 0

6.2.2 Serial In / Parallel Out (SIPO)

For this kind of register, data bits are entered serially in the same manner as discussed in
the last section. The difference is the way in which the data bits are taken out of the register.
Once the data are stored, each bit appears on its respective output line, and all bits are available
simultaneously. A construction of a four-bit serial in - parallel out register is shown below.

Figure 6.6 4-bit SIPO shift register 105
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In the Table 6.3, we can see how the four-bit binary number 1001 is shifted to the Q outputs of
the register.

Table 6.3 Operation of 4-bit SIPO

Q0 Q1 Q2 Q3
0
CLEAR 0 0 0 0
0
Shift #1 1 0 0
0
Shift #2 0 1 0 1

Shift #3 0 0 1 0

Shift #4 1 0 0

Shift #5 0 0 0 1001

6.2.3 Parallel In / Serial Out (PISO)

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-
flops, AND gates and OR gates for entering data to the register.

Figure 6.7 4-bit PISO shift register

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least
significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in.
The data can be shifted when the mode control line is HIGH as SHIFT is active high. The register
performs right shift operation on the application of a clock pulse, as shown in the table below.

Example: Shift 1001 into 4-bit PISO shift register

Table 6.4 Operation of 4-bit PISO

Q0 Q1 Q2 Q3
0
CLEAR 0 0 0 1

LOAD 1 0 0 0
0
Shift #1 1 1 0 1 1
1 01
Shift #2 1 1 1
001
Shift #3 1 1 1 1001

Shift #4 1 1 1

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6.2.4 Parallel In / Parallel Out (PIPO)

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits. The following circuit is a four-bit
parallel in - parallel out shift register constructed by D flip-flops.

Figure 6.8 4-bit PIPO shift register
The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked,
all the data at the D inputs appear at the corresponding Q outputs simultaneously.

6.3 Application of Shift Register

One of the applications of the shift register is used for carrying out arithmetic operations
such as multiplication and division. To perform this function, two shift registers that will be
used is the register shift register shift to the right and to the left.

6.3.1 Shift Right Registers as Divider Circuits

Check shift to the right serves as a divider-2. The trick is to shift the number MSB (most
significant bit) to the LSB (least significant bit), which is shifted from left to right. Bit 0 is
inserted into the MSB.
Example:

Table 6.5 Shift register as divider

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6.3.2 Shift Left Register As Multiplier Circuits

The trick is to shift the LSB to the MSB number, which is shifted to the left. Bit 0 will be
inserted in the LSB.
Example:

Table 6.6 Shift register as multiplier

6.4 Shift Register Counter

One popular application of shift registers is as sequencer, the circuit will produce a
continuous wave conditions. Products do not count in the actual binary but the sequence
number of the special issue. Thus it can be used to control a sequence of events that occur in
digital systems.

This circuit is called by the name of counter for producing a number of special numbers. Two
counter shift register that uses a ring counter and Johnson counter. Now we will try to discuss
the operations of the two counter this shift register.

6.4.1 Ring Counter

A ring counter is basically a circulating shift register in which the output of the most
significant stage is fed back to the input of the least significant stage. Figure 6.9 is a 4-bit ring
counter constructed from D flip-flops. The output of each stage is shifted into the next stage on
the positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one
FF0 are reset to 0. FF0 is preset to 1 instead.

Figure 6.9 Ring counter 108
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Since the count sequence has 4 distinct states, the counter can be considered as a mod-4
counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in
terms of state usage. But the major advantage of a ring counter over a binary counter is that it is
self-decoding. No extra decoding circuit is needed to determine what state the counter is in.

Table 6.7 Operation of Ring counter

6.4.2 Johnson Counter

Johnson counters are a variation of standard ring counters, with the inverted output of the
last stage fed back to the input of the first stage. They are also known as twisted ring counters.
An n-stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a
mod-2n counter. The circuit above shows a 4-bit Johnson counter. The state sequence for the
counter is given in the table as well as the animation on the left.

Figure 6.10 Johnson counter
Table 6.8 Operation of Johnson counter

Beware that for both the Ring and the Johnson counter must initially be forced into a valid state
in the count sequence because they operate on a subset of the available number of states.
Otherwise, the ideal sequence will not be followed.

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EXERCISE 6

1. What type of register can have data entered into it simultaneously and also has all data
bits available as outputs?
A. SISO shift register
B. SIPO shift register
C. PISO shift register
D. PIPO shift register

2. A helpful analogy for a shift register is a conveyor belt. Examine this illustration showing a
single conveyor belt at four different times, and determine which of the following shift
register operations the sequence represents:

A. Parallel-in, serial-out
B. Parallel-in, parallel-out
C. Serial-in, serial-out
D. Serial-in, parallel-out
3. A helpful analogy for a shift register is a conveyor belt. Examine this illustration showing a
single conveyor belt at four different times, and determine which of the following shift
register operations the sequence represents:

A. Parallel-in, serial-out
B. Parallel-in, parallel-out
C. Serial-in, serial-out
D. Serial-in, parallel-out

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4. A helpful analogy for a shift register is a conveyor belt. Examine this illustration showing a
single conveyor belt at four different times, and determine which of the following shift
register operations the sequence represents:

A. Parallel-in, serial-out
B. Parallel-in, parallel-out
C. Serial-in, serial-out
D. Serial-in, parallel-out

5. Shift register can be used to perform the arithmetic applications by shifting a binary number
to the appropriate direction. Determine the method perform below:-

7 6 5 432 1 0

Original number 0 0 0 1 0 1 1 1

Shift 1# 0 0 1 011 1 0

A. Additional
B. Multiplication
C. Division
D. Subtraction

6. Identify the data when the register performs right shift operation (three times shift) on the
application of a clock pulses. The data is 01011000

Original number Binary number Decimal number
Shift #3 01011000 88

A. Binary = 00101100 Decimal = 44
B. Binary = 00010110 Decimal = 22
C. Binary = 00100000 Decimal = 32
D. Binary = 00001011 Decimal = 11

7. List the application of shift register as arithmetic circuits.

i. ________________________________________________________________________
ii. ________________________________________________________________________

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8. Draw the schematic diagram for a five-bit serial-in/serial-out shift register circuit.

9. Draw a 3 bit Ring Counter circuit. Show a truth table until 8 clock pulse and draw the output
waveform.

10. Sketch a logic circuit for 2-bit Serial in Parallel out (SIPO) shift register negative edge
trigger.

11. Draw the 4-bit Serial Input Serial Output (SISO) shift register positive edge trigger.

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REFERENCES

1. Salina Muhamad & Muhammad Nazir Mohammed Khalid. (2013). Digital Electronics.
Oxford Fajar Sdn. Bhd.

2. Ronald J. Tocci & Neal s. Widmer. (Aug 16, 1994). Digital Systems: Principles and
Application 6th Edition. Pearson.

3. P.W Chandana Prasad, Lau Siong Hoe, Dr. Ashutosh Kumar Singh, & Muhammad
Suryanata. (2002). Digital Systems: Fundamentals. Prentice Hall.

4. A. Anand Kumar. (2009). Fundamentals of Digital Circuits 2nd Edition. Phi Learning