Microprocessor Fundamental Assembly Language Processing Data

KEMENTERIAN PENGAJIAN TINGGI i='CLiTEl-<nil-<
MALAYSIA
�ABATAN PENDIDIKAN POLITEKNIK DAN KOLEJ KOMUNITI SEBEllANG PERJ\I

MICROPROCESSOR FUNDAMENTAL

ASSEMBLY LANGUAGE- PROCESSING DATA

AZURA BINTI HARON@ MAKHTAR

ARM

Ill?

MICROPROCESSOR FUNDAMENTAL
ASSEMBLY LANGUAGE - PROCESSING DATA

AZURA BINTI HARON @ MAKHTAR
2022

JABATAN KEJURUTERAAN ELEKTRIK

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ii eBook PSP | 2022

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Azura Haron @ Makhtar, 1977-

MICROPROCESSOR FUNDAMENTAL: ASSEMBLY LANGUAGE: PROCESSING DATA /

AZURA BINTI HARON @ MAKHTAR.

Mode of access: Internet

eISBN 978-967-2774-20-4

1. Microprocessors.

2. ARM microprocessors.

3. Government publications--Malaysia.

4. Electronic books.

I. Title.
004.16

eBook PSP | 2022 iii

Acknowledgement

In the name of Allah, the Most Gracious and the Most Merciful.

All praises to Allah and His blessing for the completion of this e-Book. I thank God for all the
opportunities, trials and strength that

have been showered on me to finish writing this e-Book. I experienced so much during this
process, not only from the academic aspect but also from the aspect of personality. My
humblest gratitude to the Holy Prophet Muhammad (Peace be upon him) whose way of life has
been continuous guidance for me. Thank you to everyone who supported me in preparing this e-
book. All of the conversations and advisory services have been used to improve the writing of
this book.

AZURA BINTI HARON @ MAKHTAR

iv eBook PSP | 2022

Preface

The subject of Microprocessor Fundamental covers the basic processor architecture and
application of ARM processor. Student will learn the fundamental concept and techniques to
apply ARM Development Tools using inline assembler in C language. This course also provides
the skills to control external peripherals using digital input and output peripherals.

eBook PSP | 2022 v

Table of Content

01 FLOW CHART FOR A PROCESSING DATA PROBLEM

Flow Chart
• What is a Flow Chart?

Basic Shapes
• Terminator
• Process
• Input/output
• Decision
• Connectors

Flags in ARM Processors- program stats register (PSR)

APPLY ASSEMBLY LANGUAGE INSTRUCTION TO WRITE PROGRAM

02 Arithmetic Operation
Logical Operation
Shift and Rotate Operation
Reverse Data byte and Register

ASSEMBLY PROGRAM TO PERFORM THE ARITHMETIC TASK ARITHMETIC

03 OPERATION
Arithmetic Operation
• ADD Operation
• ADD carry operation
• Subtract Operation
• Subtract with borrow Operation
• Multiply Operation
• Divide Operation
Logical Operation
• AND Operation
• OR Operation
• CLEAR Operation
• OR NOT Operation
• EKCLUSIVE OR Operation
Shift and Rotate Operation
• Arithmetic Shift Right Operation
• Logical shift Left Operation
• Logical Shift Right Operation
• Rotate Right Operation
Reverse Data Byte Operation

04EXERCISE & REFERENCES



eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 1

01

FLOWCHART FOR A
PROCESSING DATA
PROBLEM

2 eBook PSP | Flowchart for A Processing Data Problem

FLOW CHART
What is a Flow Chart?

Graphical method to plan flow of our programs.
Shown program’s step-by-step operation
Easy to understand and analyse.
Can be use to write organized programs.

BASIC SHAPES
Terminator

 Indicates beginning and end of flowchart
 Once at beginning, once at end
 Examples:

Process
 Describes action to be done.
 Represented as rectangles. Short description of process in rectangle.
 Examples:

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 3

Input/output
 Shows the process of inputting or outputting data.
 Represented using rhombus.
 Examples:

Decision
 Shows alternative program flow based on condition.
 Represented as diamond shape.
 Should have 2 arrows, representing TRUE and FALSE program flows.
 Can be used in “if…else’, ‘while”, and ‘for” situations.
 Examples:

Connectors
 Used to link large process flows together.
 Represented using circles, with numbers inside.
 Number indicate connection.
 Can be used in “if…else’, ‘while”, and ‘for” situations.
 Examples:

4 eBook PSP | Flowchart for A Processing Data Problem

Example: Connector

Flags In Arm Processors – Program Status Register (PSR)

The ARM processor normally contains at least the Z, N, C and V flags, which are updated
by execution of data processing instructions.

Z Zero flag

• This flag is set when the result of an instruction has a zero value or when a
comparison of two data returns an equal result

N Negative flag

• This flag is set when result of an instruction has a negative value (bit 31 is 1)

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 5

C Carry flag

• This flag is for unsigned data processing – for example, in add (ADD) it is set when an
overflow occurs; in subtract (SUB) it is set when a borrow did not occur (borrow) is
the invert of carry).

V Overflow flag

• This flag is for signed data processing; for example, in an add (ADD), when two
positive values added together produce a negative value, or when two negative
values added together produce a positive value.

V – Overflow Bit
Set during arithmetic/divide overflow. For ADD, SUB & CMP

6 eBook PSP | Apply Assembly Language Instruction to Write Program

02

APPLY ASSEMBLY
LANGUAGE
INSTRUCTION TO WRITE
PROGRAM

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 7

ARITHMETIC OPERATION

Arithmetic: Only processor and register involved with the purposes;
• compute the sum (or difference) of two registers, store the result in a register
• move the contents of one register to another

Syntax:

• <Operation>{<cond>}{S} Rd, Rn, Operand2

where:

• <Operation> instruction by name
• Rd operand getting result (“destination”)
• Rn 1st operand for operation (“source1”)
• 2nd operand for operation (“source2”)

Examples: ADD r1, r2, r3; r1=r2+r3
ADD r3, r0, #7; r3=r0+7
ADC r1, r2, r3; r1=r2+r3+ (Carry Flag)
SUB r1, r2,r3; r1=r2-r3
SUBC r1, r2, r3; r1=r2-r3 +C -1
RSB r1, r2, r3; r1= r3-r2
RSC r1, r2, r3; r1=r3-r2 +C -1
MUL r0, r1, r2 ; r0=r1 * r2

<Operation> ADD operand1 + operand2 ; Add
are: ADC operand1 + operand2 + carry ; Add with carry
SUB operand1 ‐ operand2 ; Subtract
SBC operand1 ‐ operand2 + carry ‐ 1 ; Subtract with carry
RSB operand2 ‐ operand1 ; Reverse subtract
RSC operand2 ‐ operand1 + carry ‐ 1 ; Reverse subtract with carry
MUL operand1 * operand2 ; Multiplication

8 eBook PSP | Apply Assembly Language Instruction to Write Program

LOGICAL OPERATION

Logical instructions

• Perform the boolean operation on the pair of operands, and useful for bit
masking purpose.

• e.g, clear status bit or change interupt masks in CPSR

Syntax:

• <Operation>{<cond>}{S} Rd, Rn, Operand2

where:

• <Operation> instruction by name
• Rd operand getting result (“destination”)
• Rn 1st operand for operation (“source1”)
• 2nd operand for operation (“source2”)

Examples: AND r0, r1, #0xff ; r0 <- lowest byte of r1
BIC r0, r1, #0x10 ; clear bit 5, result in r0
BIC r0, r1, #0x5 ; clear bits 0 and 2
AND r0,r1,r2

<Operation> AND operand1 AND operand2
are: EOR operand1 EOR operand2
ORR operand1 OR operand2
ORN operand1 NOR operand2
BIC operand1 AND NOT operand2 [ie bit clear]

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 9

SHIFT AND ROTATE OPERATION

A shift operation moves the bits in a register to the left or right and filling the vacant
holes with zeros or ones

If the S suffix is used, these rotate and shift instructions also update the Carry flag in the
APSR. If the shift or rotate operation shifts the register position by multiple bits, the
value of the carry flag C will be the last bit that shifts out of the register.

a shift operation moves the bits in a register to the left or right and filling the vacant
holes with zeros or ones

Left Shift Arithmetic
Right Shift

Right Shift Rotate
Right Shift

Left Shift

• Left Shifts effectively multiply the contents of a register by 2s where s is
the shift amount

• Shifts can also be applied to the second operand of any data processing
instruction

10 eBook PSP | Apply Assembly Language Instruction to Write Program

Right Shift
• Right Shifts behave like dividing the contents of a register by 2s

where s is the shift amount, if you assume the contents of the
register are unsigned

Arithmetic Shift
• Arithmetic right Shifts behave like dividing the contents of a register

by 2s where s is the shift amount, if you assume the contents of the
register are signed.

Rotate Right Shift
• Rotating shifts have no arithmetic analogy. However, they don’t

lose bits like both logical and arithmetic shifts. We saw rotate right
shift used for the I-type “immediate” value earlier.

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 11

REVERSE DATA BYTE IN THE REGISTER

 Another group of data processing instruction is used for reversing data bytes in a
register. These instructions are usually used for conversion between little endian
(LSB) and big endian (MSB) data.

Reverse bytes in word
• REV Rd, Rn ; Rd = rev(Rn)

Reverse bytes in each half word
• REV16 Rd, Rn ; Rd = rev16(Rn)
Reverse bytes in bottom half word and
sign extend the result
• REVSH Rd, Rn ; Rd =revsh (Rn)

Example REV r3,r7

REV16 r0,r0

REVSH r0,r5; Reverse signed Halfword

REVHS r3,r7 ; Reverse with Higher or same
condition

12 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

03

ASSEMBLY PROGRAMS
TO PERFORMS THE
ARITHMETIC TASKS

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 13

ARITHMETIC OPERATION

Arithmetic ADD operation
operation ADD carry operation
SUBTRACT operation
SUBTRACT with borrow operation
MULTIPLY operation

DIVIDE operation

ADD Operation

The ADD instruction adds the values in Rn and Operand2 or imm12.

In certain circumstances, the assembler can substitute one instruction for
another.

ADD instruction can operate between two registers or between one
register and an immediate data value

14 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

Syntax:

• ADD{S}{cond} {Rd}, Rn, Operand2
• ADD{cond} {Rd}, Rn, #imm12 ; Thumb, 32-bit encoding only

where:

• S is an optional suffix. If S is specified, the condition flags are updated on
the result of the operation.

• cond is an optional condition code.

• Rd is the destination register.

• Rn is the register holding the first operand.

• Operand2 is a flexible second operand.

• Imm12 is any value in the range 0-4095.

Flag Condition:

• If S is specified, the AND instruction:
• Updates the N and Z flags according to the result.
• Can update the C flag during the calculation of Operand2.
• Does not affect the V flag.

Examples

• ADD Rd,Rn,Rm ; Rd = Rn + Rm
• ADD Rd,Rd,Rm ; Rd = Rd + Rm
• ADD Rd,#immed ; Rd = Rd + #immed
• ADD Rd,Rn,#immed ; Rd = Rn + #immed

Examples:

• ADD R0, R0, R1 ; R0 = R0 + R1
R0 = R0 + 0x12 with APSR (flags)
• ADDS R0, R0, #0x12 ;
update

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 15

Example 1

If R2 and R3 contain 0X22446688 and 0X77553311, respectively, what are the result of ADDS,
R1,R2,R3?

Instruction Data

•ADDS R1,R2,R3 •R2 =
0x22446688
•R3 =
0x77553311

Calculation Answer

•22446688 + •R1 =
77553311 = 0x99999999
99999999 in
Hex

Z • 1 (MSB = C • 1 (P + P =
1) N)
• 0 (result • 0 (No
non zero) N carry) V

APSR

16 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

Example 2

What are the result of ADDS R1, R1, R3, if R1 and R3 contain 0x1A2B3C4D
and 0x03000030?

Instruction Data

• ADDS R1,R1,R3 • R2 =
0x1A2B3C4D

• R3 =
0x03000030

Calculation Answer

• 1A2B3C4D + • R1 =
03000030 = 0x1D2B3C4D
1D2B3C4D in
Hex

ZC
•? •? •? •?
APSR N V

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 17

Example 3

What are the difference of ADDS R1,#0xFF and ADDS R2,#100 when R1 and
R2 contain 0xFFFFFF01 and 0x7FFFFFAA

Example 4

What are the result of ADDS R1,R2, #99, if R2 contains 0XEEFFEEFF?

18 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

ADD Carry Operation

The ADC (Add with Carry) instruction adds the values in Rn and Operand2,
together with the carry flag.

ADC is the same as ADD but adds an extra 1 if processor's carry flag is set.

Syntax:

• ADC{S}{cond} {Rd}, Rn, Operand2

Where

• S is an optional suffix. If S is specified, the condition flags are

• updated on the result of the operation.

• cond is an optional condition code.

• Rd is the destination register.

• Rn is the register holding the first operand.

• Operand2 is a flexible second operand.

Flag Condition:

• If S is specified, the ADC instruction updates the N, Z, C and V flags
according to the result.

Examples:

• ADC Rd, Rn, Rm ; Rd = Rn + Rm + carry
• ADC R1, R2, R3; R1= R2+R3+ Carry Flag
• ADC R0, R1, R2 ; R0 = R1 + R2 + carry

Examples:

•ADC Rd,Rn,Rm ; Rd = Rn + Rm + carry
•ADC Rd,Rd,Rm ; Rd = Rd + Rm + carry
•ADC Rd,#immed ; Rd = Rd + #immed + carry

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 19

Additional notes: WHAT IS CARRY

•What happens if we run out of digits?
•Adding two numbers each stored in 1 byte (8 bits) may produce a 9- bit result
•Added 15610 + 16710 and expected to get 32310
•8-bit result was 010000112 or 6710
•Largest number we can represent in 8-bits is 255
•The ‘missing’ or ‘left-over’ 1 is called a carry (or carry-out)

Example 5

What are the results of :

•LDR R1, =0xFFFFFF01
•LDR R2, =0xEEFFEEFF
•MOVS R3, #0x11
•ADDS R1, R1, R2
•ADCS R2, R2, R3

20 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

SUBTRACT Operation

The SUB instruction subtracts the value of Operand2 from the value in Rn
In certain circumstances, the assembler can substitute one instruction for
another.

Syntax:

•SUB{S}{cond} {Rd}, Rn, Operand2
•SUB{cond} {Rd}, Rn, #imm12 ; Thumb, 32-bit encoding only

where:

•S is an optional suffix. If S is specified, the condition flags are updated

•on the result of the operation.

•cond is an optional condition code.

•Rd is the destination register.

•Rn is the register holding the first operand.

•Operand2 is a flexible second operand.

•Imm12 is any value in the range 0-4095.

Flag Condition:

•If S is specified, the SUB instruction updates the N, Z, C and V flags according to the result.

Examples:

•SUB r1, r2,r3 ; r1=r2-r3
•SUBS r8, r6, #240 ; sets the flags on the result

Example :

• SUB Rd,Rn,Rm ; Rd = Rn – Rm
• SUB Rd,#immed ; Rd = Rd - #immed
• SUB Rd,Rn,#immed ; Rd = Rn - #immed

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 21

Example 6
If R2 and R3 contain 0x82059910 and 0x78048909, respectively, what are the
results of SUBS R1, R2, R3?

Example 7
What are the results of SUBS R3,#136 if R3 contain 0x80000056?

Example 8
What are the results of SUBS R5, R6, # 255 , if R6 contains 0xAABBCCDD?

22 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

SUBSTRACT With Borrow Operation

The SBC (Subtract with Carry) instruction subtracts the value of Operand2
from the value in Rn.

If the carry flag is clear, the result is reduced by one.

You can use SBC to synthesize multiword arithmetic.
In certain circumstances, the assembler can substitute one instruction for
another

Syntax:

•SBC{S}{cond} {Rd}, Rn, Operand2

where:

•S is an optional suffix. If S is specified, the condition flags are updated on the result of
the operation.

•cond is an optional condition code.

•Rd is the destination register.

•Rn is the register holding the first operand.

•Operand2 is a flexible second operand.

Flag Condition:

•If S is specified, the SBC instruction updates the N, Z, C and V flags according to the result

Examples:

•SBCS r4,r7,r1 ; subtract the middle words with carry
•SBCS r9,r2,r1 ; subtract the middle words with carry

Examples:

•SBC Rd,Rm ; Rd = Rd – Rm – borrow
•SBC.W Rd,Rn,#immed ; Rd = Rn - #immed – borrow
•SBC.W Rd,Rn,Rm ; Rd = Rn – Rm – borrow

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 23

MULTIPLY Operation

The MUL instruction multiplies the values from Rn and Rm, and places the least
significant 32 bits of the result in Rd.

Syntax:

• MUL{S}{cond} {Rd}, Rn, Rm

where:

• cond is an optional condition code.

• S is an optional suffix. If S is specified, the condition

• flags are updated on the result of the operation.

• Rd is the destination register.

• Rn, Rm are registers holding the values to be multiplied.

Flag Condition:

• If S is specified, the MUL instruction:
• Updates the N and Z flags according to the result.
• Corrupts the C and V flag in ARMv4.
• Does not affect the C or V flag in ARMv5T and above

Examples:

•MUL r10, r2, r5 ;r10 = r2 * r10
•MULS r0, r2, r2 ; r0 = r2 * r2
•MUL R1, R4, R5 ; R1 = R4 * 10

Examples:

• MUL Rd,Rm ; Rd = Rd * Rm
• MUL.W Rd,Rn,Rm ; Rd = Rn * Rm

24 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

Example 9

MULS R4, R5, R4 ;

• R4 = 0xFFFFFFF0 (-16) , R5 = 0xFFFFFFF6 (-10)
• R4 = R5*R5 = (-10)*(-16) =160 = 0x000000A0

Example 10

MULS R4, R5, R4;

•R4=0x0000000A, R5=0x00000064 ;
•R5=R5*R4=10*100=1000=0x000003E8

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 25

DIVIDE Operation

SDIV instruction performs a singed integer division of the number in the
register Rn by the value contained in the register Rm.

UDIV instruction is similar to SDIV but performs as unsinged integer
division of the number in Rn by the value in Rm.

These instructions do not effect the condition code flags in the application
program status register

Syntax:

• SDIV{cond} {Rd}, Rn, Rm
• UDIV{cond} {Rd}, Rn, Rm

where:

• cond is an optional condition code.
• Rd is the destination register.
• Rn is the register holding the value to be divided.
• Rm is a register holding the divisor.

Register Restriction:

• PC or SP cannot be used for Rd, Rn or Rm.

Examples: ; singed divide, R1 = R2/R4
; unsinged divide, R1 = R8/R2
• SDIV R1, R2, R4
• UDIV R1, R8, R2

Examples:

• UDIV Rd,Rn,Rm ; Rd = Rn/Rm
• UDIV Rd,Rn,Rm ; Rd = Rn/Rm

26 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

LOGICAL OPERATION

Logical AND operation
operation OR operation
CLEAR operation
OR NOT operation

EXCLUSIVE OR operation

AND Operation

The AND instruction performs bitwise AND operations on the values in Rn
and Operand2.

In certain circumstances, the assembler can substitute BIC for AND, or AND
for BIC

Syntax:

•AND{S}{cond} Rd, Rn, Operand2

where:

•S is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
•cond is an optional condition code.
•Rd is the destination register.
•Rn is the register holding the first operand.
•Operand2 is a flexible second operand.

Flag Condition:

If S is specified, the AND instruction:

•Updates the N and Z flags according to the result.
•Can update the C flag during the calculation of Operand2.
•Does not affect the V flag.

Examples:

•AND r9,r2,#0xFF00
•ANDS r9, r8, #0x19

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 27

Examples:

• AND Rd,Rn ; Rd = Rd & Rn
• AND.W Rd,Rn,#immed ; Rd = Rn & #immed
• AND.W Rd,Rn,Rm ; Rd = Rn & Rd

Example 11

Based on the instructions below, determine the results
LDRR1, =0x3795AC5F
LDR R2, =0xB6D34B9D
LDRR3, =0x456789AB
LDR R4, =0xCDEF1234
ANDS R1, R1, R2
ORRS R2, R2, R3
BICS R3, R3, R4
MVNS R4, R4
EORS R1, R1, R3

AND INSTRUCTION

•R1 = 0x3795AC5F (0011 0111 1001 0101 1010 1100 0101 1111)
•R2 = 0xB6D34B9D (1011 0110 1101 0011 0100 1011 1001 1101)

ANDS R1, R1, R2 ; ANS= R1=0x3691081D

28 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

OR Operation

The ORR instruction performs bitwise OR operations on the values in Rn
and Operand2.

In certain circumstances, the assembler can substitute ORN for ORR, or
ORR for ORN.

Syntax:

•ORR{S}{cond} Rd, Rn, Operand2

where:

•S is an optional suffix. If S is specified, the condition flags are updated on the result of the
operation.
is an optional condition code.
•cond is the destination register.
•Rd is the register holding the first operand.
is a flexible second operand.
•Rn

•Operand2

Flag Condition:

•If S is specified, the ORR instruction:
•Updates the N and Z flags according to the result.
•Can update the C flag during the calculation of Operand2.
•Does not affect the V flag.

Example:

•ORRS R2,R2,R5
•ORR R0, R0, #3 ; Set bits zero and one of R0.

Example:

• ORR Rd,Rn ; Rd = Rd / Rn
• ORR.W Rd,Rn,#immed ; Rd = Rn / #immed
• ORR.W Rd,Rn,Rm ; Rd = Rn / Rd

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 29

Example 12

OR INSTRUCTION

•R2 = 0xB6D34B9D (1011 0110 1101 0011 0100 1011 1001 1101)
•R3 = 0x456789AB(0100 0101 0110 0111 1000 1001 1010 1011)

ORRS R2, R2, R3 ; ANS= R1=0xF7F7CBBF

CLEAR Operation

Use the CLREX instruction to clear the local record of the executing processor that
an address has had a request for an exclusive access.

CLREX returns a closely-coupled exclusive access monitor to its open-access state.
This removes the requirement for a dummy store to memory.

It is implementation defined whether CLREX also clears the global record of the
executing processor that an address has had a request for an exclusive access

Syntax:

•CLREX{cond}

where: is an optional condition code.

•cond

Flag Condition:

•These instructions do not change the flags.

Example:

•CLREX

30 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

Example:

•BIC Rd,Rn ; Rd = Rd & (~Rn)
•BIC.W Rd,Rn,#immed ; Rd = Rn & (~#immed)
•BIC.W Rd,Rn,Rm ; Rd = Rn & (~Rd)

Example 13

BIT CLEAR INSTRUCTION (Rd = Rd & (~Rn))

•R3 = 0x456789AB(0100 0101 0110 0111 1000 1001 1010 1011)
•R4 = 0xCDEF1234 (1100 1101 1110 1111 0001 0010 0011 0100)

BICS R3, R3, R4; ANS= R1=0x0000898B0x456789AB

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 31

OR NOT Operation

The ORN instruction performs an OR operation on the bits in Rn with the
complements of the corresponding bits in the value of Operand2.

Syntax:

•ORN{S}{cond} Rd, Rn, Operand2

where:

•S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.

•cond is an optional condition code.

•Rd is the destination register.

•Rn is the register holding the first operand.

•Operand2 is a flexible second operand.

Flag Condition:

•If S is specified, the ORN instruction:
•Updates the N and Z flags according to the result.
•Can update the C flag during the calculation of Operand2.
•Does not affect the V flag.

Example:

•ORN R7, R11, R14, ROR #4
•ORNS R7, R11, R14, ASR #32

Example:

• ORN.W Rd,Rn,#immed ; Rd = Rn / (~#immed)
• ORN.W Rd,Rn,Rm ; Rd = Rn / (~Rd)

32 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

EXCLUSIVE OR Operation

The EOR instruction performs bitwise Exclusive OR operations on the
values in Rn and Operand2.

Syntax:

• EOR{S}{cond} Rd, Rn, Operand2

where:

• S is an optional suffix. If S is specified, the condition flags are updated
on the result of the operation.

• cond is an optional condition code.

• Rd is the destination register.

• Rn is the register holding the first operand.

• Operand2 is a flexible second operand.

Flag Condition:

• If S is specified, the EOR instruction:
• Updates the N and Z flags according to the result.
• Can update the C flag during the calculation of Operand2.
• Does not affect the V flag.

Example:

• EORS r0,r0,r3,ROR r6
• EORS r7, r11, #0x18181818

Example:

• EOR Rd,Rn ; Rd = Rd ^ Rn
• EOR.W Rd,Rn,#immed ; Rd = Rn ^ #immed
• EOR.W Rd,Rn,Rm ; Rd = Rn ^ Rd

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 33

Example 14

EOR INSTRUCTION
• R1 = 0x3691081D (0011 0110 1001 0001 0000 1000 0001 1101)
• R3 = 0x0000898B(0000 0000 0000 0000 1000 1001 1000 1011)

EORS R1, R1, R3 ; ANS= R1=0x36918196

SHIFT AND ROTATE Operation

Shift and ARITHMATIC shift right operation
Rotate LOGICAL SHIFT LEFT operation
operation LOGICAL SHIFT RIGHT operation
ROTATE RIGHT operation

34 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

ARITHMETIC Shift Right operation

ASR provides the signed value of the contents of a register divided by a power of
two. It copies the sign bit into vacated bit positions on the left.

Syntax:

•ASR{S}{cond} Rd, Rm, Rs
•ASR{S}{cond} Rd, Rm, #sh

where:

•S is an optional suffix. If S is specified, the condition flags are updated on the result of the
operation.
•Rd is the destination register.
•Rm is the register holding the first operand. This operand is shifted right.
•Rs is a register holding a shift value to apply to the value in Rm. Only the least significant byte is
used.
•sh is a constant shift. The range of values permitted is 1-32.

Flag Condition:

•If S is specified, the ASR instruction updates the N and Z flags according to the result.
•The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.

Example:

• ASR r7,r8,r9
• ASR Rd,Rn,#immed ; Rd = Rn >> immed
• ASR Rd,Rn ; Rn >> Rn
• ASR.W Rd, Rn, Rm ; Rd = Rn >> Rm

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 35

Example 15

ARITHMETIC SHIFT RIGHT

• ASRS R1, R0, #1/ ASRS R2, R0, #2
• R0=0x8375A2B7

Solution :

• Before R0=0x8375A2B4
• After R1 = 0xC1BAD15B / After R2 = 0xE0DD68AD

36 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

LOGICAL Shift Left operation

LSL provides the value of a register multiplied by a power of two, inserting zeros into
the vacated bit positions.

Syntax:

•LSL{S}{cond} Rd, Rm, Rs
•LSL{S}{cond} Rd, Rm, #sh

where:

•S is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
•Rd is the destination register.
•Rm is the register holding the first operand. This operand is shifted right.
•Rs is a register holding a shift value to apply to the value in Rm. Only the least significant byte is used.
•sh is a constant shift. The range of values permitted is 1-32

Flag Condition:

•If S is specified, the LSL instruction updates the N and Z flags according to the result.
•The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.

Example:

•LSL r7,r8,r9
•LSL Rd,Rn,#immed ; Rd = Rn >> immed
•LSL Rd,Rn ; Rn << Rn
•LSL.W Rd, Rn, Rm ; Rd = Rn << Rm

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 37

Example 16

LOGICAL SHIFT LEFT

•LSLS R1, R0, #1/ LSLS R2, R0, #2
•R0=0x2375A2B4

Solution :

•Before R0=0x2375A2B4
•After R1 = 0x86EB4568 / After R2 = 0x0DD68AD0

38 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

LOGICAL Shift Right operation

Logical Shift Right. This instruction is a preferred synonym for MOV instructions with
shifted register operands.

Syntax:

•LSR{S}{cond} Rd, Rm, Rs
•LSR{S}{cond} Rd, Rm, #sh

where:

•S is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.
•Rd is the destination register.
•Rm is the register holding the first operand. This operand is shifted right.
•Rs is a register holding a shift value to apply to the value in Rm. Only the least significant byte is used.
•sh is a constant shift. The range of values permitted is 1-32.

Flag Condition:

•If S is specified, the instruction updates the N and Z flags according to the result.
•The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.

Example:

•LSR r4,r5,r6
•LSR Rd,Rn,#immed ; Rd = Rn >> immed
•LSR Rd,Rn ; Rn >> Rn
•LSR.W Rd, Rn, Rm ; Rd = Rn >> Rm

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 39

Example 17

LOGICAL SHIFT RIGHT

• LSRS R1, R0, #1/ LSRS R2, R0, #2
• R0=0x8375A2B7

Solution :

• Before R0=0x8375A2B4
• After R1 = 0x41BAD15B / After R2 = 0x20DD68AD

40 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

ROTATE Right operation

Syntax:

• ROR{S}{cond} Rd, Rm, Rs
• ROR{S}{cond} Rd, Rm, #sh

where:

• S is an optional suffix. If S is specified, the condition flags are updated on the
result of the operation.

• Rd is the destination register.
• Rm is the register holding the first operand. This operand is shifted right.
• Rs is a register holding a shift value to apply to the value in Rm. Only the least

significant byte is used.
• sh is a constant shift. The range of values permitted is 1-32.

Flag Condition:

• If S is specified, the instruction updates the N and Z flags according to the result.
• The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the

last bit shifted out.

Example:

• ROR.W Rd,Rn,#immed ; Rd = Rn ROT by immed
• ROR Rd,Rn ; Rn ROT Rn
• ROR.W Rd, Rn, Rm ; Rd = Rn ROT by Rm

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 41

Example 18

ROTATE RIGHT

•LDRR0, =0x8375A2B7
•MOVS R1, #1
•RORS R0, R0, R1
•RORS R0, R0, R1

Solution :

•Before R0=0x8375A2B4
•After R0 = 0xC1BAD15B / After R0 = 0xE0DD68AD

42 eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data

REVERSE DATA BYTE Operation

These instructions are usually used for conversion between little endian and big endian data

Example 19

R1 = 0x3795AC5F

• REV R0, R1;
• ANS= R0=5FAC9537

Example 20

R2 = 0xB6D34B9D

•REV16 R4, R2;
•ANS= R4= 0xD3B69D4B

eBook PSP | MICROPROCESSOR FUNDAMENTAL – Assembly Language: Processing Data 43

Example 21

R3 = 0x456789AB / R3 = 0xA0A0AA55

• REVSH R5, R3; ANS= R5= 0xFFFFAB89
• ; ANS= R3= 0x000055AA