IEEE Electron Device Society Colloquium March 20, 2012 ...

The World Leader in High Performance Signal Processing Solutions

“SPICE Compatible
Models for Circuit
Simulation of ESD

Events”

Jean-Jacques (J-J) Hajjar,
Srivatsan Parthasarathy

& Paul Zhou

IEEE Electron Device Society Colloquium
University of Central Florida, Orlando, FL

March 20, 2012

Everywhere

MOTIVATION

Key Drivers: the 3 “S”

 Simulation: Predicting robustness of a particular
design to ESD prior to manufacture.

 Synergy: Synthesize the physical concepts that
describes the ESD event into a self-contained
solution.

 Simplicity: Automate and integrate simulation
flow in a standard circuit simulation
environment.

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OUTLINE

1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks

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OUTLINE

1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks

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Definition: What is ESD?

Electro-Static Discharge

Relevance: - Damages IC

- Key “product quality” metric

Customer Return Pareto:

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What is ESD?

Designing for ESD Robustness: Common Practice
Design cycle:

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What is ESD?

Designing for ESD Robustness: The benefit of
Simulation
Design cycle:

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OUTLINE

1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks

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Modeling Objectives & Approach

A. Verification

– Pass or Fail Robustness test
– Interaction with Core (or Protected) Circuitry

B. Optimization

– Redundant or insufficient protection?

C. Design Cycle Reduction

– First pass success

D. Simplicity

– Adopted by end-user

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Modeling Objectives & Approach

Quantify Charge dissipation and Failure

RR R1 R1
Q4 Q5
Q1 Q2
V1 Q3 Q6 VOUT
V2 R4 R3
Everywhere
10 R5 R6

Modeling Objectives & Approach

Device Model Development Characteristics:
ASIIC

● Accurate
● Simple
● Incremental

– Leverage standard device models.

● Integrated

– Compatible with circuit design environment.

● Comprehensive

– Protection as well as protected devices modeled.

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Modeling Objectives & Approach

ESD Characteristics

A. Electrical:

– Large currents & large voltages
– Short duration: 1-200 ns.

B. Physical Failure:

– Junction damage
– Dielectric/Gate-oxide damage

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Modeling Objectives & Approach

ESD Characteristics
C. Limited applied stimulus:

– Two common models: HBM & CDM

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Modeling Objectives & Approach

What to model?

● Focus on region beyond normal operation.
● Determine failure point.

IV DC
(VMAX, IMAX)
STRESS

DEVICE
FAILURE

NORMAL
OPERATION

VOLTAGE →

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Modeling Objectives & Approach

What to model?

● Focus on region beyond normal operation.
● Determine failure point.

IV DEVICE ESD
FAILURE
AVALANCHE STRESS
CURRENT (VMAX, IMAX)

NORMAL
OPERATION

VOLTAGE →

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Modeling Objectives & Approach

Measuring DUT Transient Characteristics

Characteristics obtained using a TLP (transmission line pulse)
measurement technique.

_

v

_

i

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CURRENT →
AVERAGEI →

OUTLINE

1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Examples
5) Concluding Remarks

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Model Development

What to model?
SiGe Complementary Bipolar Process

Proprietary high performance fully dielectrically isolated
complementary bipolar process with SiGe NPN.

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Model Development

Incentive for Device Model Development

RR R1 R1

Q4 Q5

V1 Q1 Q2 VOUT

V2 Q6
R3

Q3

R5 R6
R4

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Model Development

What Devices to Model?
A. Core Devices:

 Bipolar transistors: PNP & NPN
 Diodes
 Passive Devices

B. Protection Devices:

 ESD Diodes

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Model Development Everywhere

Physical Mechanisms to Model
● Junction Breakdown
● Avalanche Current
● Velocity Saturation
● Kirk Effect
● Resistivity Modulation
● Failure

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Model Development

Non-Physical Diode-Switch Model

● Verilog-A Implementation: 1.0 Current (A)

– Variable “turn-on” Voltage: Von
– Variable series Resistance: R

0.5 R

Von

01 2 3

Voltage (V)

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Model Development

ESD Diode Model Current (A)

Current (A) 1.0

0.1 0.5

0.05 `

-1 -0.5 0 0.5 1 -4 -3 -2 -1 0 1
0.05
Voltage (V) Voltage (V)

0.5

Standard operation Operation during
ESD event

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Model Development

ESD Diode Model

● Sub-circuit consisting of Ideal and Standard diodes.

NON-PHYSICAL STANDARD DIODE
DIODE-SWITCH

I
on V

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Model Development

Bipolar Breakdown Models

• BVEBO: Emitter-Base junction breakdown with Collector floating.
• BVCBO: Collector-Base junction breakdown with Emitter floating.
• BVCEO: Collector-Emitter breakdown with Base floating.

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Model Development

Leverage and Integrate with Standard SPICE Model

C

● Start with MEXTRAM model B MEXTRAM

● Add necessary elements to Ci
model high-current/voltage Bi
transient.
Ei

E

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Model Development

NPN Emitter-Base Breakdown Model

● NPN BVEBO is modeled using: NPN AE=0.35 5.2 m

– Ideal diode: D1 Device Failure
(VM,IM)
– Series resistance: R1
SIMULATION
– DC source: VEBO=BVEBO DATA

● Diode turns on at VEBO

R1 BVEB0
VEBO
D1 Everywhere

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Model Development

PNP Emitter-Base Breakdown

TLP I-V Characteristics

PNP AE=4 1 10 m POLYSILICON E

200

Device Failure EXT-BASE B
C
150 (VM,IM)
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100 r

50

BVEB0

0
0 4 8 12
VOLTAGE (V)

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Model Development

PNP Emitter-Base Breakdown Model

● A parallel breakdown is PNP AE=4 1 10 m
observed at V>BVEBO
Device Failure PARALLEL
● This breakdown is modeled (VM,IM) (R2)
using:
SIMULATION r
– Ideal diode: D2 DATA

– Series resistance: R2

– DC source: VEBO1=BVEBO1

PRIMARY
(R1)

BVEB0

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Model Development

NPN Collector-Base Breakdown Model

● BVCBO is modeled using:

– Ideal diode: D2
– Series resistance: R2
– DC source: VCBO=BVCBO

● Diode turns at VCBO

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CURRENT (mA) Model Development

PNP Collector-Base Breakdown

Pulsed I-V Characteristics

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Model Development

PNP Collector-Base Breakdown Model

● A Parallel breakdown path is
observed due to the reach-
through between extrinsic-
base/collector.

● Current flows laterally instead of
vertically.

R4 R3

VCBO1 VCBO

D4
D3

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Model Development

Collector-Emitter Breakdown

● Impact ionization in the base collector depletion region.
● Electron-hole pairs swept into the base and collector respectively.
● Results in forward-biasing the base-emitter base junction.
● Current flow from emitter to collector sustains the avalanching in the

depletion region

NP N

33 EB C Everywhere

Model Development

Collector-Emitter Breakdown Model

● The collector-emitter breakdown characterized by several physical
mechanisms.

● Primary breakdown is due to avalanche.
● Carrier velocity saturation and conductivity modulation are also

observed.

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Model Development

Using MEXTRAM to Model C B E
Collector-Emitter Breakdown:

CBCO CBEO RE
E1
● Weak avalanche is modelled in RCC QBE IN
MEXTRAM. ISUB RBV IB

● The resulting current will turn-on RBC
the Emitter-Base diode.
B1 B2
● This is sufficient to initiate and IAVL
sustain the breakdown. IBC QBC
C2
● The collector resistance will be RCV
optimized to model the conductivity
modulation. C1

● Velocity saturation is also modelled QSUB
in MEXTRAM.

S

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Model Development

Collector-Emitter Breakdown Model

NPN PNP

80 NPN AE=1 10 m 80 PNP AE=1 10 m
60
SIMULATION Device Failure Device Failure
DATA (VM,IM)
60 (VM,IM)
CURRENT (mA)
CURRENT (mA)
40 40 r
20 BVCEO 20 BVCEO

0 4 8 12 0
0 VOLTAGE (V) 0 10 20
VOLTAGE (V)
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Model Development

Bipolar Model for ESD Event Simulations

Ci Ci
D2 CBO
R4 R3 CBO
Model Model

VCBO1 VCBO

VCBO MEXTRAM
MEXTRAM
D3 C
R2 C D4 B
Bi B Bi E
R1 E
D1 D2

VEBO

VEBO VEBO1
R1
D1 EBO R2 EBO
Model Model

Ei Ei
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Model Development

Failure Metric

● Difficult to Model IV DEVICE
● Empirical formulation FAILURE
AVALANCHE
– Current density CURRENT (VMAX, IMAX)
– Energy dissipation
NORMAL
OPERATION

VOLTAGE →

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Model Development

● Difficult to Model Failure Metric
● Empirical formulation
MAXIMUM CURRENT (mA) — 100 NS. PULSE
– Current density 300
– Energy dissipation
200
12
100

0
048
EMITTER AREA ( m2)

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OUTLINE

1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Example
5) Concluding Remarks

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Circuit Simulation Example

Full-Chip ESD Simulation

● High frequency RF quadrature modulator
● Required to pass 2,000V HBM
● ESD simulation mimics actual HBM testing

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Circuit Simulation Example

Full-Chip ESD Simulation

The design failed 1,000V HBM when stressed between supply VCC and
the I/O pin (VOUT).

FAILED NPN (Q9: AE=0.35 5.2 m)

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VOLTAGE (V)Circuit Simulation Example

CURRENT (mA)● The simulation identified NPN Q9 to go into BVCEO and conduct current
before the ESD protection turns on.

VOLTAGE TRANSIENT DURING
HBM STRESS

TLP CHARACTERISTICS OF INDIVIDUAL
NPN TRANSISTOR Q9

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CURRENT (mA) VOLTAGE (V)Circuit Simulation Example

● Current and Voltage transient of NPN transistor Q9 during HBM stress with
failure region highlighted.

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Circuit Simulation Example

● XIVA (eXternally-Induced Voltage Alteration) micrograph
● The failure location identified was the output NPN transistor flagged by the

ESD simulator.

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Circuit Simulation Example

● Fix consists of adding resistor in series with transistor Q9
● Resulting current through transistor Q9 decreases to below failure level.

CURRENT TRANSIENT DURING HBM
STRESS ACROSS TRANSISTOR Q9

Q9: NPN AE=0.35 5.2 m

RR R1 Q9 R CURRENT (mA) 60 ORIGINAL FAILURE
Q1 Q2 Q4 DESIGN
Q3
40

VOUT 20 REVISED
DESIGN

R3

0 1
0 0.2 0.4 0.6 0.8
TIME (10-6 sec.)

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OUTLINE

1) What is ESD?
2) Modeling Objectives & Approach
3) Model Development
4) Circuit Simulation Example
5) Concluding Remarks

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SUMMARY

● An enhanced compact bipolar breakdown model was developed for a
SiGe bipolar process.

● The model was built around the industry-standard MEXTRAM compact
bipolar model, enabling SPICE-like circuit simulation.

● The model developed is integrated as part of the standard SPICE-type
circuit simulation environment.

● Simulation accuracy was confirmed using circuit simulation example and
the relevant Failure Analysis techniques.

● Predictive ESD simulation methodology used successfully on over four
dozen designs, over four bipolar process technologies and on various
design complexities.

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The World Leader in High Performance Signal Processing Solutions

“SPICE Compatible
Models for Circuit
Simulation of ESD

Events”

Jean-Jacques (J-J) Hajjar,
Srivatsan Parthasarathy

& Paul Zhou

IEEE Electron Device Society Colloquium
University of Central Florida, Orlando, FL

March 20, 2012

Everywhere