Bevel Edge Treatment for Reduction of Defect Density by ...

ECS Transactions, 35 (20) 7-15 (2011)
10.1149/1.3646495 © The Electrochemical Society

Bevel Edge Treatment for Reduction of Defect Density by Plasma Etch Processes
Applied in Silicon Trench Technologies

G. Ehrentraut
Infineon Austria
Siemensstr. 2, A-9500 Villach, Austria
email: [email protected]

Plasma etch processes in combination with additional process
steps in the standard process flow have been developed and
implemented in the manufacturing process for semiconductor
products utilizing trench technology for successful defect
density reduction. The developed methods have resulted in a
sustainable reduction of defect density patterns mainly resulting
from the formation of Si needles at the wafer edge during single
crystal silicon trench etching.

Introduction

With decreasing CDs of semiconductor products and the progressing demand for
decreasing edge exclusion for yielding chips defect density has become more and
more a yield detractor. In addition to scribe lines the wafer edge exhibits the largest
contingent area where silicon is exposed to plasma etch processes. In trench
technologies requiring single crystal silicon etching the wafer edge has always been
prone to build-up of so-called “black silicon” /1/. The latter, an acronym for the
formation of silicon needles as a result of the concurrence of micromasking and
highly selective etch processes exhibits a source of defects /2/ seriously impacting
product yield.

Experimental

For pattern definition in the SiO2 hard mask used for plasma etching of single crystal
silicon, i-line lithography was utilized. Pattern transfer into the hard mask was done
with an MERIE type dielectric etcher (AMAT Centura) followed by resist ashing in a
downstreamer. For defect density reduction resulting from resist particles typically
2mm of edge bead removal (EBR) was done to keep the backside and the bevel of the
wafer free from resist. Plasma etching of single crystal silicon was done in various
etchers (including tools from AMAT and Lam). Etch systems processing 8-inch
diameter wafer substrates have been using electrostatic chucks (ESC) to fix the wafer
during plasma processing, Thus the wafer bevel is exposed to the plasma which may
lead to defect density.

Results and Discussion

Due to the fact that defects from the wafer bevel (Fig. 1) may result in substantial
yield loss, different methods have been evaluated to demonstrate the effectiveness of
defect reduction. Those particles consist of silicon and are generated typically during
the single crystal silicon etch or during hardmask removal. The silicon particles stick
very good on the wafer and can even be found after several process steps, such as
after filling of the trenches and after several etchback process steps (Fig. 2). The etch
attack at the wafer bevel is not uniform and can also generate structures which are
prone to particle generation (Fig. 3).

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ECS Transactions, 35 (20) 7-15 (2011)

Fig. 1: SEM images of typical defects observed at the EBR region of wafers after deep single crystal
silicon trench etching. Typical lateral dimensions of the hole and trench structures are 1µm and below

Fig. 2: SEM images of a defect observed after hardmask removal and several filling and etchback
steps

Fig. 3: SEM images of structures generated on the wafer bevel

In general there are three methods to reduce particle issues. One method is to try to
clean processed wafers in a more efficient way. Wafer cleaning is generally an
efficient way to reduce the defect level. Another method is to remove the defects
directly after the single crystal silicon trench etch process by use of wafer edge
treatment (e.g. bevel treatment). There are commercially available tools exclusively
designed for post-plasma etch wafer bevel treatment in addition to methods which can
be used on standard plasma etch equipment. A further method is to avoid the etching
of the wafer bevel during single crystal silicon etching. This method is very efficient,
but needs further investigation in processes prior to patterning of the SiO2 hard mask.
The latter method often requires serious increase of process flow complexity. All
three methods have been evaluated in detail and exhibit different advantages and draw
backs which will be discussed in-depth.

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ECS Transactions, 35 (20) 7-15 (2011)

Wafer cleaning
Wet chemical wafer cleaning can be done on different tools with different methods.
Four different tools have been tested during evaluation and showed a strong
difference in cleaning efficiency. Wafer cleaning by assistance of ultrasonic sound
leads to an increase of particles due to breakage of the thin needles. A clean by use of
a nanonozzle reduces the particles as the flow of the medium is from center of the
wafer to the edge. The defects on the wafer bevel are thus removed in flow direction
over the wafer edge.
Further cleaning tools are wet benches and so called cleaners. The cleaning efficiency
of these tools differs significantly (Fig. 4). A wet bench process is able to remove
more than 90 percent of the particles and only a small amount of particles is
redistributed on the wafer. The cleaning tools have a cleaning efficiency of only about
60 percent and about 25 percent of the particles are only redistributed on the wafer
surface. The cleaning time has only a small effect on the cleaning efficiency, a longer
clean does not necessarily reduce the particle count.

Fig. 4: Results of wafercleaning after wet chemical hardmask removal. Color code: green: particles
removed, yellow: particles redistributed, red: particles still in place

As shown the cleaning efficiency is strongly depending on the cleaning tool used
and/or method applied. Wafer cleaning is a way to reduce particles, but is not able to
completly remove all defects from the wafer.
Defect removal directly after single crystal silicon etch
The second method tries to remove the defects directly after the single crystal silicon
etch process by use of additional process steps. It is an integrative approach to remove
damaged silicon at the wafer bevel before doing a wet chemical hardmask removal.
Two different concepts have been tested. The first method is done by use of an
additional resist coating of the wafer and isotropic etch processes which only etch the
unprotected wafer bevel (Fig. 5). The resist coating protects the etched trench
structures and the edge bead removal opens the wafer bevel for the isotropic wet or
isotropic plasma processes removing oxide, silicon and defects there (Fig. 6).

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ECS Transactions, 35 (20) 7-15 (2011)

Fig. 5: Schematics of process flow with resist coating as protection for the trenches during bevel
etching

Fig. 6: Results of bevel treatment by use of resist coating of the wafer

A drawback of this method is that particles on the wafer or within the resist during the
coating process may lead to cracks in the resist and may therefore lead to undesired
etching of the structures in the resist coated area of the wafer (Fig. 7).

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ECS Transactions, 35 (20) 7-15 (2011)

Fig. 7: Defects caused by resist defects before and after resist removal

A similar approach can be done by use of commercially available bevel etch systems.
Those tools do not need a protective coating. In these tools only the wafer bevel is
exposed to the plasma. The efficiency of this method has been demonstrated
extensively (Fig. 8). Etching is only obtained at the outermost part of the wafer within
2mm from the wafer edge.

Fig. 8: Results of commercial bevel etch tool, left side: bevel itself, right side: etch bead removal area

Defect avoidance by wafer edge protection
There are different methods to avoid the defects on the wafer bevel. The first method
shown only addresses the problem caused by the edge bead removal. The edge bead
removal is done to make sure that no resist is on the wafer backside and consists of
two steps. The first step is a wet chemical removing of the resist by a rinsing process.
In a second step resist is removed on the frontside of the wafer from the bevel area
exclusively by a mechanical method or by lithography. If the second step is omitted,
resist is still in place on the frontside of the wafer even at the bevel area, without well
defined changeover to the resistless backside. The result (Fig. 9) show the reduction
of the defective area on the wafer bevel. The frontside of the wafer has no defective
areas at the wafer edge and only on the rounding of the bevel, “black silicon” is
observed.

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ECS Transactions, 35 (20) 7-15 (2011)

Fig. 9: SEM micrographs of wafer bevels after standard edge bead removal (left) and after wafer
backside rinsing only (right)

The positive effect of this method is, that due to the fact that the wafer bevel is
rounded, lithography out of focus there and therefore the resist patterns are not fully
developed at the extreme edge of the wafer. This implies that the hardmask used for
single crystal silicon etching will not be opened properly, which in turn prevents
trench etching in this area at the wafer edge (Fig. 10). Thus defect density can be
reduced very efficiently with this method.

Fig. 10: Structures with lithography out of focus at the wafer bevel

Another approach to protect single crystal silicon at the wafer edge from exposure to
the plasma used for silicon trench etching is local oxidation of silicon (LOCOS) at the
wafer edge prior to single crystal silicon etching. By use of the LOCOS technique
silicon at the wafer bevel and the wafer backside is completely protected with oxide.
When the hardmask open process for the silicon trench etching process is done the
wafer bevel is still protected by LOCOS oxide. The single crystal silicon etch is not
able to remove the oxide (LOCOS) on the wafer bevel. The results on the topside of
the wafer look similar to the result shown above in Fig. 10 and there is no damage on
the bevel.
A more complex solution is using a mechanical clamp or so called bottom shadow
ring to protect silicon at the wafer bevel during trench etching. This ring can be
introduced on almost every commercially available tool. The drawback for standard
trench etch processes is, that the passivation behavior near the bevel is changing
(Fig. 11). A solution for that issue was not found. For Bosch processes a high process
performance could, however, be demonstrated with this concept.

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ECS Transactions, 35 (20) 7-15 (2011)

Fig. 11: SEM micrographs showing results from single crystal silicon etching with shadow ring (as
etched samples, extreme edge is near to the edge of the ring)

Since the silicon trench etching process is very sensitive with regard to build-up of
passivation, an alternative utilizes an approach with a polysilicon layer on top of the
oxide mask, which can also be patterned with this approach. The polysilicon
patterning process is not as sensitive with regard to polymerization effects as the
single crystal silicon etching process. This finally leads to the success of this
approach. In the nearfield of the ring there is a small tilt effect regarding profiles,
which finally results in an increased edge exclusion (Fig. 12). Reduced etch rates of
polysilicon are a negative side effect associated with the use of a bottom shadow ring.

Fig. 12: Effect of bottom shadow ring (BSR) on poly-Silicon hardmaskopen process (SEM
micrographs taken from about 2mm to 3mm from edge, mask stack: remaining resist, poly-silicon,
oxide, nitride, oxide)

The drawback of a patterned poly silicon etch, the increase of edge exclusion on the
wafer (2mm Æ 5mm) is, however, not acceptable in many cases.
An approach avoiding this loss of useable wafer area is to deposit polysilicon onto the
wafer followed by a blanket polysilicon etching process with this ring in place as
(shadow) mask. It can be demonstrated that after an isotropic polysilicon etch process
the wafer bevel remains covered with polysilicon (Fig. 13) and that isotropic thinning
of polysilicon occurs only in a very narrow area below the ring close to the ring edge.
It was demonstrated that in combination with a reduced edge bead removal the wafer
bevel can be protected during the single crystal silicon etch. The hardmask open
process is not able to remove the polysilicon completely. The remaining polysilicon is
removed during the single crystal etch process and is still remaining on the wafer
backside (Fig.14).

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ECS Transactions, 35 (20) 7-15 (2011)

Fig. 13: Optical top down images of remaining polysilicon after blanket isotropic poly silicon etch by
use of a shadow ring

Fig. 14: SEM micrographs of a wafer bevel (a) upper part, b) lower part) after single crystal silicon
etching performed with a ring of patterned polysilicon around the wafer in the bevel area of the wafer.
c) For reference a wafer bevel (upper part) after silicon etching without polysilicon protection layer is
shown

Summary
Various methods to protect single crystal silicon at the wafer bevel from exposure to
the plasma during single crystal silicon trench etching have been investigated. This
kind of wafer bevel protection is mandatory for trench technologies to avoid so-called
“black silicon” at the wafer edge which exhibits a detrimental source of defect density
which may impact product performance or even product yield.
The methods investigated have their advantages and drawbacks. Wafer cleaning is the
cheapest method, but it does not remove all defects from the wafer and if not done
properly, generates more particles than were present before. The introduction of

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ECS Transactions, 35 (20) 7-15 (2011)

additional processes for etching the bevel directly after single crystal silicon etching
work fine, but in the case of the resist coating approach the risk for resist cracks and
associated damaged structures is always given. The commercial bevel edge tools are a
good solution, requiring an additional invest with the risk that wafer handling prior to
the treatment may cause defects.
A good solution is the approach with a LOCOS process prior to the silicon trench etch
module which requires additional process steps, if LOCOS will not be needed anyway
in the process flow.
The bottom shadow ring approach is also an expensive way of bevel protection, when
using a polysilicon layer to protect the bevel, but for very deep trench etching in
single crystal silicon in combination with wafer thinning, this approach will be
needed. For MEMS applications using Bosch etch tools the use of a shadow ring
during single crystal silicon etch is a cheap solution to minimize defectivity as there
are no additional layers needed for wafer edge protection.

Acknowledgement
Thanks are due to the process engineers and the SEM group of Infineon Technologies
Austria AG for process support, defect density evaluation, and for the SEM work.

References
/1/ I. W. Rangelow, P. Thoren, K. Masseli, R. Kassing, M. Engelhardt, S. Schwarzl,
Microelectronic Engineering, 5, pp. 387-394 (1986)
/2/ G. Ehrentraut, GMM Workshop, Erlangen, Germany, Nov. 26th, 2009

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