Counters and NUUR MAISYA BINTI MAZNI HAFIZA BINTI NYAK HARUN in Digital Electronics REGISTERS
COUNTERS AND REGISTERS IN DIGITAL ELECTRONICS I POLITEKNIK SULTAN HAJI AHMAD SHAH NUUR MAISYA BINTI MAZNI HAFIZA BINTI NYAK HARUN
Copyright ©2023, by Politeknik Sultan Haji Ahmad Shah Materials published in this book under the copyright of Politeknik Sultan Haji Ahmad Shah. All rights reserved. No part of this publication may be reproduced or distributed in any form or by means, electronic, mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without the prior written permission of the publishers. II NUUR MAISYA BINTI MAZNI HAFIZA BINTI NYAK HARUN Published by POLITEKNIK SULTAN HAJI AHMAD SHAH SEMAMBU 25350 KUANTAN eISBN: 978-967-2766-69-8
III Welcome to the world of counters and registers in digital electronics! We will explore the basics of digital counters and registers and their importance in the field. The contents of this ebook is written specifically for students at the diploma level. Digital counters and registers are essential components in electronic systems that help with counting, timing and control tasks. They work with binary numbers, using flip flops and logic gates to perform their function. We will learn about different types of counters and registers and how they operate synchronously or asynchronously. Let’s dive in and explore the fascinating world of digital counters and registers! Preface
Contents 01 17 31 03 30 29 Introduction of Counters Asynchronous Counters Synchronous Counters Counters Application Introduction of Registers Types of Shift Registers 38 Application of Shift Registers
01 1.0 What is Counter MOD (N) = 2 n where n = total of flipflop 3 flip flops modulus 8 8 states 6 flipflops modulus 64 64 states For examples: Two types of counter: A counter is a device that counts the number of the clock cycles. The counter also can be used as an instrument for measuring time, period or frequency. 1 The counters are contain of flipflop that wired in series to perform the type of counting. 2 The Modulus (MOD) of the counter is the total number of states through which the counter can progress. 3 Asynchronous Counter 2 Synchronous Counter 1 Count Direction: Up Counters Down Counters Up/Down Counters
No. Asynchronous Counter Synchronous Counter 1. Each flip flop in an asynchronous counter has its own individual clock signal. The clock signals for different flip flops are not necessarily synchronized All flip flops share a common clock signal. The clock signal is applied simultaneously to each flip flop, ensuring synchronous operation 2. Have propagation delay. No propagation delay. 3. Count in sequence. Count in random. 4. The logic circuit is simple. The logic circuit is more complex 02 Difference between Synchronous and Asynchronous Counter:
A ripple counter is a cascaded arrangement of flip flops where the output of one flip flop drives the clock input of the following flip flop. 1 In a ripple counter, also called an asynchronous counter or a serial counter, the clock input is applied only to the first flip flop, also called the input flip flop. For instance, the output of the first flip flop acts as the clock input to the second flip flop, the output of the second flip flop feeds the clock input of the third flip flop and so on. 2 00 01 10 11 11 10 01 00 03 1.1 Asynchronous Counter For examples: Mod 4 Up Counter : 00, 01, 10, 11 Mod 4 Down Counter : 11, 10, 01, 00 Figure 1: Positive Going Trigger (PGT) Asynchronous Up Counters Figure 2: Positive Going Trigger (PGT) Asynchronous Down Counters Figure 3: State Diagram of Mod 4 Up Counter Figure 4: State Diagram of Mod 4 Down Counter
n 5 Steps to Build Asynchronous Up Counter Count in sequence from minimum number to maximum number. 04 1.1.1 Asynchronous Up Counter Figure 5: Positive Going Trigger (PGT) Asynchronous Up Counters Figure 6: Negative Going Trigger (NGT) Asynchronous Up Counters Find the total number of flipflop. n = Log N / Log 2 N = modulo = 2 n Find the maximum decimal number. N-1 Draw the state transition diagram. Construct the logic circuit. Draw timing diagram. 1 2 3 4 5
Example 1.0 Solution Circuit connection Construct a mod 8 asynchronous up counter using T Flipflop with negative edge trigger. 05 No of FF n = Log N / Log 2 = Log 8 / Log 2 = 3 FF State transition diagram Timing diagram. 1 Maximum Decimal Number N-1 8-1 = 7 2 3 4 5
Example 1.1 Solution 5 Timing diagram. No of FF n = Log N / Log 2 = Log 4 / Log 2 = 2 FF Maximum Decimal Number N-1 4-1 = 3 Using JK FF positive edge triggered, draw the circuit and timing diagram of mod 4 asynchronous up counter. 06 n State transition diagram Circuit connection 1 2 3 4
Example 1.2 Solution No of FF n = Log N / Log 2 = Log 8 / Log 2 = 3 FF Count in sequence from maximum number to minimum number. 07 1.1.2 Asynchronous Down Counter Figure 7: Positive Going Trigger (PGT) Asynchronous Down Counters Figure 8: Negative Going Trigger (NGT) Asynchronous Down Counters Using JK FF positive edge triggered, draw the circuit and timing diagram of mod 8 asynchronous down counter. Maximum Decimal Number N-1 8-1 = 7 1 2 3 State transition diagram
08 4 Circuit connection 5 Timing diagram. Pop Quiz How many flip flops are required to construct a mod 128 counter? What is the largest decimal number that can be count by this counter? How many ffs are required for a counter that count 0 to 255? 1. 2. Answer: 7 flip flops, 127 Answer: 8 flip flops
Example 1.3 Solution Using T FF negative edge triggered, draw the circuit and state the transition diagram of mod 16 asynchronous down counter. 09 n No of FF n = Log N / Log 2 = Log 16 / Log 2 = 4 FF 1 Maximum Decimal Number N-1 16-1 = 15 2 3 State transition diagram 4 Circuit connection
f (out) = f (in) / 2 where n = total of ff n 1 Each flip flop divides the frequency of its input by: 2 Example 1.4 All the Asynchronous Counter also can be called as a Frequency Divider. Suppose that the clock signal is 16 KHz for the mod 4 up counter.The waveform at output A is an 8 KHz square wave and at output B is reduce to 4KHz. 10 1.1.3 Asynchronous as a Frequency Divider n Formula on How to Find Frequency Output Find the frequency output for the counter which has eight flipflop when the input clock frequency is 512KHz. Figure 9: The Output Waveform of a Frequency Divider Circuit Solution fout= f(in) / 2 = 512kHz / 2 = 2kHz n 8 Using n ff would produce an output frequency from last ff, which is equal f / 2 or f / N where N is equal to number of Mod. in in n
Example 1.5 Solution Given an input frequency (fin) = 15kHz, calculate output frequency f(out) for asynchronous counter as below. 11 n a. 6 bits b. 5 bits c. mod 10 a. f = f / 2 n = 15 kHz / 26 = 234.375 Hz b. = 15 kHz / 2 = 468.75 Hz f = f / 2 n 5 b. = 15 kHz / 10 = 1.5 kHz f = f / N out in out in out in
n Example 1.6 A modulus given by 2 , where n indicates the number of flip flops. Such counter are said to have a Natural Count on 2 . For examples: Two flip flops, 2 = Mod 4 Three flip flops, 2 = Mod 8 Four flip flops, 2 = Mod 16 1 It is often desirable to construct counters having a modulus other than, 2, 4, 8 an so on, such as mod 3, mod 12 or mod 6. 2 A smaller modulus counter can always be constructed from a larger modulus counter by Skipping States (modified count). The correct number of flip flops is determined by choosing the lowest natural count that is greater than modified count. 3 Solution No of FF n = Log N / Log 2 = Log 5 / Log 2 = 2.32 ~ 4 FF 12 1.1.4 Asynchronous Counters MOD < 2 Draw the logic circuit and waveform for the Mod 5 Asynchronous Up Counter using JK Flip Flop with Negative Edge Triggered (NGT). n 1 Maximum Decimal Number N-1 6-1 = 5 2 3 State transition diagram 2 3 4 n n
n 4 Circuit connection 5 Timing diagram. 13
Example 1.7 Solution 4 Circuit connection n 14 Draw the logic circuit and waveform for the Mod 11 Asynchronous Down Counter using T flip flop with Positive Edge Triggered (PGT). No of FF n = Log N / Log 2 = Log 11 / Log 2 = 3.46 ~ 4 FF 1 Maximum Decimal Number N-1 6-1 = 5 2 3 State transition diagram
Asynchronous Up Counter mod 16 can be modified with additional logic gates to give a decade (Mod 10) counter use in standard decimal counting. 1 Count sequence number from binary, ranging from 0000 to 1001. 2 Decade counters are used in digital clock, digital meter and frequency divider. 3 15 1.1.5 Asynchronous Decade Counters Figure 10: Asynchronous Decade Counter
Figure 2.1 shows Asynchronous Counter Mod 8 which can count up or down by using AND-OR gate and controlled by Up/Down control input. 1 When Up/Down control input high then AND gate altogether motteled will be active and will connect Q output to clock input Clk, then counter would count up. 2 When Up/Down control low, AND gate altogether motteled inactive and will connect Q output to clock input Clk, then the counter start to counter down. 3 16 1.1.6 Asynchronous Up/Down Counters Figure 11: Asynchronous Decade Counter Clock Input UP/DOWN Control
Each flip flop is triggered synchronously with the clock. 1 In an Asynchronous Counter, delays add up with each flip flop. To address this, using a Synchronous or Parallel Counter helps overcome these problems. 2 17 1.2 Synchronous Counter Examples of Synchronous Counter: Figure 12: Synchronous Up Counter Mod 4 Figure 13: Synchronous Down Counter Mod 4 6 Steps to Build Synchronous Up Counter Construct the truth table by consulting Table 1 for the JK flip-flop and Table 2 for the T flip-flop, referring to the Excitation Table. Determine the Boolean equation from Karnaugh Map. Draw the logic circuit. 1 2 3 4 5 Find the total number of flipflop. n = Log N / Log 2 N = modulo = 2 Draw the state transition diagram. 6 Draw the timing diagram. n
n n Exchange Input States Qn Qn+1 J K 0 0 0 X 0 1 1 X 1 0 X 1 1 1 X 0 Exchange Input States Qn Qn+1 T 0 0 0 0 1 1 1 0 1 1 1 0 Example 1.8 Solution 18 Table 1: Truth Table for JK flip flop Table 2: Truth Table for T flip flop Design a synchronous up counter Mod 8 using JK flip flop with negative edge trigerred. No of FF n = Log N / Log 2 = Log 8 / Log 2 = 3 FF 1 2 State transition diagram
n Exchange Input States Qn Qn+1 A B C A B C Ja Ka Jb Kb Jc Kc 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 1 0 0 X 1 X X 1 0 1 0 0 1 1 0 X X 0 1 X 0 1 1 1 0 0 1 X X 1 X 1 1 0 0 1 0 1 X 0 0 X 1 X 1 0 1 1 1 0 X 0 1 X X 1 1 1 0 1 1 1 X 0 X 0 1 X 1 1 1 0 0 0 X 1 X 1 X 1 AB AB AB AB C 0 0 X X C 0 1 X X AB AB AB AB C 0 X X 0 C 1 X X 1 AB AB AB AB C 1 1 1 1 C X X X X AB AB AB AB C X X 0 0 C X X 1 0 AB AB AB AB C X 0 0 X C X 1 1 X AB AB AB AB C X X X X C 1 1 1 1 19 3 Truth Table 4 Boolean equation from Karnaugh Map Ja = BC Jb = C Jc = 1 Ka = BC Kb = C Kc = 1
n 5 Circuit connection Example 1.9 Solution No of FF n = Log N / Log 2 = Log 10 / Log 2 = 3.46 ~ 4 FF 20 Design a synchronous up counter Mod 10 using T flip flop with negative edge trigerred. 1 2 State transition diagram
n n Exchange Input States Qn Qn+1 A B C D A B C D Ta Tb Tc Td 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 1 AB AB AB AB CD 0 0 X 0 CD 0 0 X 1 CD 0 1 X X CD 0 0 X X AB AB AB AB CD 0 0 X 0 CD 0 0 X 0 CD 1 1 X X CD 0 0 X X 21 3 Truth Table 4 Boolean equation from Karnaugh Map Ta = AD + BCD Tb = CD
n n AB AB AB AB CD 0 0 X 0 CD 1 1 X 0 CD 1 1 X X CD 0 0 X X AB AB AB AB CD 1 1 X 1 CD 1 1 X 1 CD 1 1 X X CD 1 1 X X Tc = AD Td = 1 5 Circuit connection 22
n Example 2.0 Solution 23 Design a synchronous counter using JK flip flop with negative edge trigerred clock that has the following sequence: 0, 7, 9, 13 and repeat. No of FF n = Log N / Log 2 = Log 13 / Log 2 = 3.7 ~ 4 FF 1 2 State transition diagram 3 Truth Table Exchange Input States Qn Qn+1 A B C D A B C D Ja Ka Jb Kb Jc Kc Jd Kd 0 0 0 0 0 1 1 1 0 X 1 X 1 X 1 X 0 1 1 1 1 0 0 1 1 X X 1 X 1 X 0 1 0 0 1 1 1 0 1 X 0 1 X 0 X X 0 1 1 0 1 0 0 0 0 X 1 X 1 0 X X 1
n n 24 4 Boolean equation from Karnaugh Map AB AB AB AB CD 0 X X X CD X X X X CD X 1 X X CD X X X X Ja = D AB AB AB AB CD 1 X X X CD X X X 1 CD X X X X CD X X X X Jb = 1 AB AB AB AB CD 1 X X X CD X X 0 0 CD X X X X CD X X X X Jc = A AB AB AB AB CD 1 X X X CD X X X X CD X X X X CD X X X X Jd = 1 AB AB AB AB CD X X X X CD X X 1 0 CD X X X X CD X X X X Ka = B AB AB AB AB CD X X X X CD X X 1 X CD X 1 X X CD X X X X Kb = 1 AB AB AB AB CD X X X X CD X X X X CD X 1 X X CD X X X X Kc = 1 AB AB AB AB CD X X X X CD X X 1 0 CD X 0 X X CD X X X X Kd = BC
n 25 5 Circuit connection
Counter can be connected in cascade to produced the bigger modulus (Mod). For example: Mod 32 - Connect Mod 4 and Mod 8 in cascade. 1 Connect the output from the last flip flop (Mod 4) to the clock input at the first flip flop (Mod 8) 2 Example 2.1 Solution 26 1.2.1 Cascade Connection Figure 14: Cascade connection Mod 16 and Mod 2 counter are connected in a cascade connection. Calculate the total Mod. Mod 16 x Mod 2 = Mod 32 Cascade connection
n Exercise With the aid of diagram, explain the difference between positive edge triggered and negative edge triggered clock. 1. Draw the Mod 9 Asynchronous Counter circuit using T flip flops with negative-edge triggering. 2. Mod 8 and Mod 16 counter are connected in a cascade connection. Calculate the total of Mod. 3. Design a synchronous counter using T flip flop with negative edge triggered clock that has the following sequence: 0, 5, 10, 15 and repeat. 4. 27
n n Answer 28 Positive edge flip-flops will allow its outputs to change its inputs only at the positive spikes. The negative edge only responds to the negative-going edge of the clock. 1. 2. 3. Mod 8 x Mod 16 = Mod 128 State transition diagram 4. No of FF n = Log N / Log 2 = Log 15 / Log 2 = 3.9 ~ 4 FF 1. 2. 3. Truth Table AB AB AB AB CD 0 X X X CD X 1 X X CD X X 1 X CD X X X 0 Ta = B A B C D A B C D Ta Tb Tc Td 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 4. Karnaugh Map AB AB AB AB CD 1 X X X CD X 1 X X CD X X 1 X CD X X X 1 AB AB AB AB CD 0 X X X CD X 1 X X CD X X 1 X CD X X X 0 AB AB AB AB CD 1 X X X CD X 1 X X CD X X 1 X CD X X X 1 Tb = 1 Tc = B Td = 1 5. State transition diagram
A common application of counters is seen in timekeeping systems. Counters are often used in digital clocks to show the time in hours, minutes, and seconds. 1 In Figure 5-27, a logic diagram of a digital clock is displayed, showcasing the tracking of seconds, minutes, and hours. The process begins by converting a 60Hz alternating current (a.c.) voltage to a 60Hz square wave, which is then divided by mod 50 counters (mod 10 cascaded with mod 5) to achieve a frequency of 1Hz. Subsequently, the frequencies for seconds and minutes are divided by counters with 60 divisors (mod 10 cascaded with mod 6). Similarly, for the hour digits, 10 divisor counters and JK flip flops are connected to generate 9 decoders and 12 decoders. 2 n 29 1.2.1 Counters Application chegg.com Figure 15: Logic Diagram for 12-Hours Digital Clock
n A register is a data storage element in digital circuits. It can store a group of binary bits and is used to hold data temporarily during processing. Registers are commonly used for various purposes, such as holding the operands in arithmetic operations or storing data temporarily between different stages of a digital system. 1 On the other hand, a shift register is a specific type of register that allows the bits stored in it to be shifted from one position to another. It has a shift input that moves the bits along the register, either to the left or to the right. Shift registers are often employed for tasks such as serial-to-parallel or parallel-to-serial conversion, data storage, and signal processing. 2 In summary, a register is a more general term for a data storage element, while a shift register specifically refers to a register with the capability to shift its stored bits. 3 30 What is Register and Shift Register? 2.0 A register is a semiconductor device that is used for storing several bits of digital data. Can be defined as a device or group of flip flops that are used to store and shift the data. Register Shift Register
2.1 Types of Shift Registers 1 D-type flip flops are commonly used in constructing shift registers because their output follows the input data. 4 31 1 2 3 4 Serial In Serial Out (SISO) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Parallel In Parallel Out (PISO) 0 1 0 1 stored and appears on output 0 stored and appears on output Figure 16: D flip flop’s as memory tool
Circuit Diagram 1 0 0 1 0 1 1 0 Example 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 32 2.1.1 Serial In Serial Out (SISO) Data are shifted in and out one at a time through the input and output lines. Definition Block Diagram Input Output First Shift Second Shift Third Shift Fourth Shift Fifth Shift Sixth Shift Seventh Shift Eighth Shift
1.1.4 Asynchronous Counters MOD < 2 n n n A modulus given by 2 , where n indicates the number of flip flops. Such counter are said to have a Natural Count on 2 . For examples: Two flip flops, 2 = Mod 4 Three flip flops, 2 = Mod 8 Four flip flops, 2 = Mod 16 1 n 2 3 4 2 Draw the timing diagram Data Clock QA QB QC QD t 0 0 0 0 1 t 1 0 0 0 0 t 0 1 0 0 1 t 1 0 1 0 1 t 1 1 0 1 t 0 1 1 0 t 0 0 1 1 t 0 0 0 1 t 0 0 0 0 Example 2.2 Solution Build the truth table D Draw the waveform /timing diagram to shift the number 1101 into the SR SISO. Assume initial Q =0000. 1 0 0 1 2 3 4 5 6 7 8 LSB MSB 33
1.1.4 Asynchronous Counters MOD < 2 n n n A modulus given by 2 , where n indicates the number of flip flops. Such counter are said to have a Natural Count on 2 . For examples: Two flip flops, 2 = Mod 4 Three flip flops, 2 = Mod 8 Four flip flops, 2 = Mod 16 1 n 2 3 4 34 Solution Example 2.3 Draw a SISO 5 bits SR using JK flip flop. Determine the number of ff needed to construct a SR capable of storing: i. 6 bit binary number ii. Decimal number up to 32 - 100000 iii. Hexadecimal number up to flip flop Pop Quiz Answer: 6 flip flops Answer: 6 flip flops Answer: 8 flip flops
Circuit Diagram Example 1 0 0 1 0 1 1 0 35 2.1.2 Serial In Parallel Out (SIPO) Data are shifted in one at a time, and once all bits are included, they are shifted out simultaneously. Definition Block Diagram Input Output 1 0 0 1 0 1 1 0 Serial In 10010110 Parallel Out
Circuit Diagram Example 1 0 0 1 0 1 1 0 36 2.1.3 Parallel In Serial Out (PISO) Each bit of data shifted in simultaneously, shifting out one bit at a time. Definition Block Diagram Input Output 1 0 0 1 0 1 1 0 Serial Out Parallel In 0
Circuit Diagram Example 1 0 0 1 0 1 1 0 37 2.1.4 Parallel In Parallel Out (PIPO) All bits of data shifted in at once, and they shift out simultaneously. Definition Block Diagram Input Output 1 0 0 1 0 1 1 0 Parallel In 1 0 0 1 0 1 1 0 Parallel Out Parallel Input Parallel Output
Binary Decimal Original Number 01011000 88 First Shift 00101100 44 Second Shift 00010110 22 2 Use shift right register. Data is shifted from left to right. 38 2.2 Application of Shift Registers Arithmetic Circuits Counter Data Converter 2.2.1 Arithmetic Circuit For example: Division by 2 Multiplication by 2 Ring Counter Johnson Counter
2 Use shift left register. Binary Decimal Original Number 00010110 22 First Shift 00101100 44 Second Shift 01011000 88 Data is shifted from right to left. 39 For example:
Ring Counter Johnson Counter Shift Register Counter A Ring Counter is a digital circuit comprised of interconnected flip flops arranged in a feedback configuration 1 2 The last flip flop shifts its value to the first flip flop. A “mod - n” ring counter will require “n” number of flip flops. 3 40 2.2.2 Counter 2.2.2.1 Ring Counter Figure 17: How bits move through a shift register
Circuit Diagram 41 Timing Diagram
The inverted output Q of the last flip-flop is now connected back to the input D of the first flip-flop. 1 Circuit Diagram Clock Pulse FFA FFB FFC FFD 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1 42 2.2.2.2 Johnson Counter Example
43 2.2.2.3 The difference between ring counter and Johnson counter A ring counter is a shift register (a cascade connection of flip-flops) with the output of the last one connected to the input of the first, that is, in a ring. Typically a pattern consisting of a single 1 bit is circulated, so the state repeats every N clock cycles if N flip-flops are used. It can be used as a cycle counter of N states. A Johnson counter (or switchtail ring counter, twisted-ring counter, walking-ring counter, or Moebius counter) is a modified ring counter, where the output from the last stage is inverted and fed back as input to the first stage. A pattern of bits equal in length to twice the length of the shift register thus circulates indefinitely. These counters find specialist applications, including those similar to the decade counter, digital to analog conversion, etc. Ring Counter Johnson Counter
L ASCII code CPU Monitor n 44 2.2.2.4 Data Converter Press the ‘L’ key Computer system will process the data in parallel, so the data need to be changed from serial to parallel. 1 2 3