24 – 26 November 2025Everly Putrajaya, Malaysia
2025 5th IEEE International Circuit and System Symposium2 PUBLISHED IN NOVEMBER 2025ALL RIGHT RESERVED NO PART OF THIS PUBLICATION MAY BE REPRODUCED, STORED IN A RETRIEVAL SYSTEM OR TRANSMITTED, IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL, PHOTOCOPYING, RECORDING OF OTHERWISE, WITHOUT THE PRIOR PERMISSION OF THE COPYRIGHT OWNER. PUBLISHED BY IEEE CASS MALAYSIA EDITOR: MD AMZARI MD ZHAHIRERMIRA JUNITA ABDULLAHDESIGNER: MD AMZARI MD ZHAHIRERMIRA JUNITA ABDULLAH
2025 5th IEEE International Circuit and System Symposium3ORGANISING COMMITTEECHAIR:Dr. Mohd Amrallah Mustafa (UPM)CO- CHAIR:Assoc. Prof. Dr. Asral Bahari Jambek (UNIMAP)SECRETARY:Ts. Dr. Julie Roslita Rusli (UNIKL)TREASURER:1. Prof. Ir. Dr. Suhaidi Shafie (UPM)2. Ts. Dr. Luthffi Idzhar Ismail (UPM)LOCAL ARRANGEMENT:1. Prof. Dr. Wan Zuha Wan Hasan (UPM)2. Ts. Dr. Norhayati Sabani (UNIMAP)PUBLICATION:1. Assoc. Prof. Dr. Maryam Mohd Isa (UPM)2. Assoc. Prof. Dr. Lini Lee (MMU)3. Ts. Dr. Julie Roslita Rusli (UNIKL)TUTORIAL/SPECIAL SESSION:1. Ts. Dr. Muhammad Idzdihar Idris (UTEM)2. Assoc. Prof. Dr. Fakhrul Zaman Rokhani (UPM)REGISTRATION CHAIR:1. Assoc. Prof. Dr. Jagadheswaran Rajendran (USM)2. Dr. Selvakumar Mariappan (USM)PROGRAM CHAIR:1. Assoc. Prof. Dr. Ermira Junita Abdullah (UPM)2. Dr. Md. Amzari Md Zhahir (UPM)TECHNICAL CHAIR:1. Ts. Dr. Haslina Jaafar (UPM)2. Assoc. Prof. Ir. Dr. Noor Hazrin Hany Mohamad Hanif (IIUM)PUBLICITY & WEBMASTER:1. Assoc. Prof. Dr. Fauzan Ahmad (UTM)2. Assoc. Prof. Dr. Jasronita Jasni (UPM)3. Assoc. Prof. Dr. Norhafiz Azis (UPM)INDUSTRIAL & SPONSORSHIP:1. Prof. Dr. Harikrishnan Ramiah (UM)2. Ir. Dr. Hazian Mamat (MIMOS)
2025 5th IEEE International Circuit and System Symposium4FOREWORD BY CHAIRMANICSyS 2025 ORGANISING COMMITTEEAssalamu'alaikum wrt. wbt.In the name of Allah, the Most Gracious and Most Merciful.Welcome to the Symposium 2025 5th IEEE International Circuit and System Symposium (ICSyS 2025)! This year, we are pleased to hold such conference at the heart of Putrajaya. The ICSyS conference series has now entered into its fifth edition since its inception in Year XXXX. It is a platform for academia, government agencies and industries to share current status in circuit and system technologies, expand professional networking, and also offer possible collaborations for technology advancement.The theme this year, “Embracing AI Chips: Shaping the Future of Modern Living” emphasizes the embarkation of innovative and creative advances, frontiers and applications of engineering and technology towards readily sustainable and maintainable future. As one of the engineering fields with the highest technological density, electrical and electronics engineering always the spearhead of technological breakthrough. Its continual progression nourishes other engineering fields and society. ICSyS 2025 also promoting industry led research and technology activities among the academia and industry players.Dr. Mohd Amrallah Mustafa
2025 5th IEEE International Circuit and System Symposium5KEYNOTE SPEAKER 1Prof. Dr. Alex James, Digital University KeralaXXX
2025 5th IEEE International Circuit and System Symposium6KEYNOTE SPEAKER 2Dr. Roberto La Rosa, ST Microelectronic, CataniaStrategies, Techniques and Systems for Powering Low-Maintenance and Maintenance-Free Wireless Sensor NodesIn the swiftly evolving Internet of Things (IoT), wireless sensor network integration is pivotal to realizing a connected ecosystem. Market analysts forecast a monumental milestone of one trillion IoT devices by 2035. This growth is mirrored in the smart sensor market, which is projected to expand from $36.6 billion in 2020 to $87.6 billion by 2025, at a Compound Annual Growth Rate (CAGR) of 19.0%. Simultaneously, the energy harvesting systems market is expected to grow from $440.39 million in 2019 to $817.2
2025 5th IEEE International Circuit and System Symposium7million by 2025, with a CAGR of 10.91%.The challenge of powering such a vast array of IoT devices is daunting, considering the reliance on batteries and the associated maintenance and environmental costs. To illustrate, powering a trillion-node network would necessitate the daily replacement of 274 million batteries, even under the assumption of a ten-year battery lifespan.This lecture delves into the forefront of research and development in energy-autonomous systems, presenting innovative strategies and techniques that eliminate the need for batteries in electronic devices. The focus will be on the latest advancements in circuits and systems for wireless sensor nodes, aiming for sustainability with minimal or no maintenance requirements. The discussion will highlight the transformative potential of these technologies in achieving a self-sustaining IoT infrastructure, aligning with the goals of environmental sustainability and operational efficiency, and charting a course for the future of smart sensor applications.Join us as we explore the intersection of innovation and practicality, paving the way for the next generation of energy-independent IoT devices within the IEEE CASS community.-----Dr. Roberto La Rosa is an esteemed electrical engineer with a Master’s degree from the University of Palermo and a Ph.D. from the École Polytechnique Fédérale de Lau sanne. His doctoral thesis, which merited the prestigious Thomas Gessner Award in 2023, concentrated on pioneering strategies and techniques for the autonomous operation of wireless sensor nodes via energy harvesting and wireless power transfer.Since joining STMicroelectronics in 1997, Dr. La Rosa has played a key role in various projects. His expertise encompasses the design of high-frequency Phase-Locked Loops (PLLs) for clock generation and signal recovery, fiber-optic transceiver systems, power management integrated circuits, and the development of analog, digital, and mixed-signal bipolar and CMOS circuits. His proficiency in IC mixed-signal design and ultra-low power applications has been pivotal in advancing these technological areas.Currently, as a Research Senior Staff Member at STMicroelectronics in Catania, Italy, Dr. La Rosa’s research focuses on Ultra-Low Power applications, Wireless Power Transfer, Energy Harvesting, and high-frequency power conversion. He has authored several influential papers and holds multiple patents in these fields, underscoring his leadershipin energy autonomy for wireless sensor networks.In addition to his research activities, Dr. La Rosa serves as an Associate Editor for the IEEE Transactions on Agrifood Electronics and the IEEE Sensors Magazine, where he contributes his expertise to advance the field of electrical engineering and support the growth of these vital areas of study.
2025 5th IEEE International Circuit and System Symposium8KEYNOTE SPEAKER 3Assoc. Prof.Dr. Asral Bahari Jambek, Universiti Malaysia Perlis, MalaysiaEnergy-Efficient Algorithm for DNA Microarray Image Processing on Portable Diagnostic DevicesDNA microarrays are powerful tools, like tiny laboratories on a chip, used to understand which genes are active at any given time. This is crucial for areas like disease diagnosis and discovering new medicines. The process involves putting thousands of unique DNA probes onto a slide, adding a sample (such as from a patient), and
2025 5th IEEE International Circuit and System Symposium9scanning it with a laser to see where the sample DNA binds and glows. The brighter the spot, the more of that specific gene is present.Getting this genetic information from the scanned image requires complex computer analysis, particularly image processing, which involves finding each spot (gridding), separating it from the background (segmentation), and measuring its glow (intensity extraction). However, standard image processing methods can be computationally demanding, making them slow and difficult to use on portable electronic devices.This keynote presents our research focused on creating an automatic DNA microarray image processing algorithm that is both accurate and requires low computational power. We explored various techniques to perform accurate DNA microarray image processing. Our experiments show that our new methods achieve good reduction in computational load while keeping high accuracy. This breakthrough makes it possible to bring this powerful analysis to portable devices, leading to more accessible and potentially faster disease diagnosis.-----Associate Professor Dr. Asral Bahari Jambek is the head of the Universiti Malaysia Perlis Centre of Excellence for Micro System Technology (MiCTEC). He is also a member of the Faculty of Electronic Engineering Technology at Universiti Malaysia Perlis (UniMAP), where he served as the Program Chairperson for the Electronics Engineering Degree Programme. Dr Asral has an electronic engineering background, holding a PhD from the University of Edinburgh, United Kingdom in 2008. He also earned an MSc from the University of Putra Malaysia (UPM) and a BEng from the University of Southampton, both in Electronic Engineering, in 2002 and 1998 respectively. He has over 20 years of experience in both industry and academia in the design of very large-scale integration (VLSI) circuits and systems. Before joining academia, he was a senior engineer at a primer semiconductor research centre in Malaysia. He has spent a total of 13 months at Intel Malaysia and MIMOS Berhad as a Visiting Fellow and Visiting Academic. He is an active member of the IEEE Circuit and System Society (CAS), and currently serving as Chair of the Malaysia Chapter. His research interests include the development of low-energy algorithms and architecture for ultra-portable devices. This includes circuits and systems for Internet of Things (IoT) devices, system-on-chip, signal/image/video processing, and artificial intelligence.
2025 5th IEEE International Circuit and System Symposium10KEYNOTE SPEAKER 4Assoc. Prof. Dr. Cui Suhan, University of Science and Technology BeijingResearch on EEG Feature Extraction and Classification Methods for Cognitive AssessmentElectroencephalography (EEG), as a non-invasive neural monitoring modality with high temporal resolution, has been playing an increasingly important role in domains such as cognitive impairment screening, spatial cognition training, and emotion recognition. However, due to substantial inter-individual variability and the complex nature of EEG signals, traditional feature extraction and classification methods face significant limitations in terms of generalization and discriminative performance. To address these challenges, our research focuses on the question: How can we more effectively extract informative features from EEG signals and achieve stable classification performance?To this end, we have proposed a series of novel strategies aimed at coupled feature extraction. Notably, we developed spatial filtering algorithms based on Permuted Conditional Mutual Information (PCMI), including PCMICSP, WPCMI, and MPCMIMSI. These methods are capable of capturing inter-regional interactions in the brain, thereby enhancing the detection of task-relevant coupling characteristics. In parallel, we explored multiband combinations and the image-based transformation of temporal-frequency domain features, converting them
2025 5th IEEE International Circuit and System Symposium11into multi-spectral image inputs to provide deep learning models with richer and more structured representations.In terms of classification, we introduced innovations to the CNN architecture from multiple perspectives. These include the Multi-scale High-density Convolutional Neural Network (MHCNN), Single-Scale Multi-Input CNN (SSMICNN), Dual-Input EEG CNN (DIE-CNN), and the Uncertainty-Aware Transformer (DU-Former). These models are designed to exploit differences across frequency bands, preserve the independence of input channels, and model sample-wise distribution uncertainty, thereby enabling accurate classification of spatial cognitive states, emotional categories, and mild cognitive impairment (MCI), particularly among patients with comorbid type 2 diabetes mellitus (T2DM).Collectively, our work establishes a closed-loop framework from coupled feature extraction to multimodal deep classification, substantially enhancing the utility of EEG signals for evaluating spatial cognition and MCI. Looking ahead, we aim to integrate these models into a unified virtual reality–brain–computer interface (VR–BCI) assessment system, extending their potential applications to home-based and wearable platforms. This integration holds promise for achieving intelligent monitoring and intervention for cognitive health.-----Dr. Cui Suhan is an interdisciplinary researcher dedicated to the integration of artificial intelligence and healthcare. His research focuses on machine learning, data mining, large language models, brain–computer interfaces (BCI), and electronic health record (EHR) modeling. He has published over ten high-impact papers in leading AI and biomedical venues, including NeurIPS, The Web Conference (WWW), and Journal of Biomedical Informatics, as first author.Dr. Cui has extensive experience in intelligent medical research and system development, having previously conducted research at Microsoft Research Asia and IQVIA.From a research and innovation perspective, Dr. Cui aims to advance next-generation intelligent healthcare systems through the synergy of large-scale models, multimodal medical data, and human–machine interaction. His work contributes to the development of AI-driven diagnostic, predictive, and decision-support technologies, fostering the translation of computational intelligence into real-world medical applications.
2025 5th IEEE International Circuit and System Symposium12TENTATIVE PROGRAMPre-conference eventDay 1 - 24th November 2025Time Event 8.00 amRegistration Briefing for Session Chairs 9.00 am Conference Opening Day 1 Welcome Remarks by ICSys 2025 Chair 9.10 am Keynote Speech 1 9.55 am Invited Speakers10.15 am Group Photo & Coffee Break10.45 am Keynote Speech 211.30 amTechnical Session 1 \"Nanoelectronic Hybrid System Integration, Advanced IC Packaging, Sensory Circuits & Systems \" 1.00 pm Lunch 2.30 pmTechnical Session 2 \"Digital Integrated Circuits & Systems, Digital Signal, Nonlinear System & Circuits Theory \"Technical Session 3 \"Artificial Intelligent Circuits & Systems\" 4.30 pm Networking & RefreshmentsDay 2 - 25 November 2025Time Event 8.00 amRegistration Briefing for Session Chair 9.00 am Keynote Speech 3 9.45 am Keynote Speech 410.30 am Coffee Break11.00 amTechnical Session 4 \"Analog & Mixed Signals Circuits & Systems\"Technical Session 5 “Power and Energy Circuits & Systems”12.45 pm Conference Closing 1.00 pm LunchPost-conference event
2025 5th IEEE International Circuit and System Symposium13TECHNICAL SESSIONSTechnical Session 1Time Paper ID Title11.30 am 1571186573Optimizing NiO Properties for Enhanced Perovskite Solar Cell EfficiencyNurbahirah Norddin, Suhaidi Shafie, Muhammad Idzdihar Idris, Xinzhi Liu and Ismail Lawal11.45 am 1571197751Comparative Analysis of Noise Figure in AlGaN\\GaN HEMTs with AlGaN and AlInN Back-BarriersHusna Hamza, Julie Roslita Rusli, Wan Maziyah Ab. Halim, Izanoordina Ahmad, Balqis Budiman and Anwar Jarndal12.00 pm 1571199101Effect of off-Centre Ball on Lead Frame Plating and Wire Properties(Author name not provided.)12.15 pm 1571174019Battery-Free and Sensor-Free Water Turbidity Sensing Using STM32 BLEJewahra Ademosman Saleh, Samsuzana Abd Aziz, Norulhuda Mohamed Ramli, Khairudin Nurulhuda, Roberto La Rosa, Orazio Aiello and Fakhrul Zaman Rokhani12.30 pm 1571192247Design and Implementation of a Multi-Sensor MEMS-Based Flight Data Monitoring and Tracking System Using Hybrid Communication NetworksMohamed Tarmizi Ahmad, Michael Lam, Amzari Zhahir, Razali Abidin and Baizura Bohari12.45 pm 1571192677Development of a Self-Diagnostic IoT-Based Aquaculture Monitoring System Using Raspberry PiDanny Chang Jun Wei, Asral Bahari Jambek, Mohd Yusri Azli Mohd Yusof and Mazlan AbbasTechnical Session 2Time Paper ID Title2.30 pm 1571186043Self Heating Aware Temperature Analysis of Hetero Dielectric Vertically Stacked FeFinFET for Digital Circuit ApplicationsKajal Verma and Rishu Chaujar2.45 pm 1571189403Evaluation of 6T SRAM Bit Cells Using Mono3D Integration with Optimized MIV ConfigurationsYap Jia Jun, Noor Ain Kamsani, Roslina Mohd Sidek and Fakhrul Zaman Rokhani3.00 pm 1571169218Robust Equivalent Transmit Beamforming Under Random Element Failures: A Stochastic Geometry ApproachAdil Farooq, Hasan Mir and Lutfi Albasha
2025 5th IEEE International Circuit and System Symposium143.15 pm 1571187813A Robust Hybrid Image Watermarking Scheme Using DWT, DCT, and QR Decomposition Based on Spread SpectrumMuhammad Farhan Attila, Gelar Budiman and Ledya Novamizanti3.30 pm 1571176510Low-Voltage Reference with Enhanced CLM Immunity in 130 nm CMOS for IoT Edge NodesKhang Yian Ng, Harikrishnan Ramiah, Kai Song Tan, YeeChyan Tan and Gabriel Chong3.45 pm 1571197845Piezoelectric and Electromagnetic Hybrid Micro-Energy Harvester for Wireless Electronic DevicesMohammad Alif Akhirudin Hablee, Noor Hazrin Hany Mohamad Hanif and Mohd Ismifaizul bin Mohd Ismail4.00 pm 1571223244Performance Analysis of Horizontal Single-Axis Tracker Versus Fixed Tilted Photovoltaic SystemsMuhamad Khairol Ab Rani, Mohd Zubir Khalid, Noor Shelida Salleh, Raja Mohd Fuad Tengku Aziz and Muhamaad Fikrii ZahariTechnical Session 3Time Paper ID Title2.30 pm 1571185608A LoRa-Enabled Battery-Less Node for AI-Driven Smart AgricultureMario Costanza, Mike Hayes, Francesca Volti, Orazio Aielloand Roberto La Rosa2.45 pm 1571189384Truncated Adder Integration in a Convolutional Neural Network Approximate AcceleratorLim Qi Yang, Lim Yang Wei, Fakhrul Zaman Rokhani and Noor Ain Kamsani3.00 pm 1571189644Development of an Artificial Intelligence (AI)-Based Automated Crayfish Measurement SystemMuhamad Irwan Hakim Ahmad, Asral Bahari Jambek, Chakradhar Cheekati, Hilal A. Fadhil, Mohd Yusri Azli Mohd Yusof and Mohammad Firdaus Othman3.15 pm 1571191742Integration of Aerial Object Detection System with Flight ControllerHilam Prasath Swami Vivekananda, Ray Anselm Hai Seng Lim, Ermira Junita Abdullah and Mohd Faisal Abdul Hamid3.30 pm 1571197749Introducing IEEE P7014.1: Recommended Practices for Ethical Emulated Empathy in General-Purpose AI SystemsAndrew McStay, Karen Bennet and Boon Chong Ang3.45 pm 1571200000 Printed Circuit Board Defect Detection System Using Deep Learning on FPGA
2025 5th IEEE International Circuit and System Symposium15Lee Jia Qian and Nasri Sulaiman4.00 pm 1571200620Evaluating YOLOv8-Pose Model Variants for Accurate Pose Estimation in Oil Palm Ripe Fresh Fruit Bunches (FFB) DetectionRozilawati Mohd Nor, Wan Zuha Wan Hasan, Hafiz Rashidi Ramli, Muhamad Saufi Mohd Kassim, Nazmi bin Mat Nawi and Nor Mohd Haziq Norsahperi4.15 pm 1571200634Dynamic Experience Management for Mobile Robot Navigation in Dynamic EnvironmentsYingjie Zhu, Wan Zuha Wan Hasan, Hafiz Rashidi Ramli, Nor Mohd Haziq Norsahperi, and Muhamad Saufi Mohd KassimTechnical Session 4Time Paper ID Title11.00 am 1571178849A Natively Flexible 8-Bit Differential Resistive Ladder SARADCMohsen Padash, Leon Brindley, Adam Rearden, Thom Smith and Brian Cobb11.15 am 1571179208Comparison Between Gate-Driven CMFBs on Inverter-Based OTAs in Multiple SpecificationsNgo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran and Orazio Aiello11.30 am 1571184684Low-Power Inverter-Based Fully Differential OTA in Flexible Integrated Circuit TechnologyNoor Ul Amin, Orazio Aiello, Fakhrul Zaman Rokhani and Roslina Mohd Sidek11.45 am 1571186795Ultra-Low-Power Multi-Level Voltage Reference Circuit in TFTs-Based Flexible Circuit TechnologyNoor Ul Amin, Roslina Mohd Sidek and Fakhrul Zaman Rokhani12.00 pm 1571192457Low-Latency 1.5-Bit Quantizer for a 400 Mbps ContinuousTime Sigma-Delta Modulator in 65 nm CMOS for Biomedical InstrumentationWang Shengquan, Jagadheswaran Rajendran, Selvakumar Mariappan, Norhamizah Idros, Asrulnizam Abd Manaf, Narendra Aridas, Arokia Nathan and Binboga S. Yarman12.15 pm 1571197450A 14 Bit 1 GS/s Segmented CMOS DAC with Glitch-Free Switching for 5G New Radio Sub-6 GHz TransmittersNorhamizah Idros, Jagadheswaran Rajendran, Selvakumar Mariappan, Sofiyah Sal Hamid, Asrulnizam Abd Manaf, Narendra Aridas, Arokia Nathan and Binboga S. Yarman12.30 pm 1571198286 23.7 fJ/Conv. Double-Tail Dynamic Comparator Design Using 180nm CMOS Technology
2025 5th IEEE International Circuit and System Symposium16Julie Roslita Rusli, Suhaidi Shafie, Wan Maziyah Ab Halim, Izanoordina Ahmad, Balqis Budiman and Roslina Mohd Sidek12.45 pm 1571201848A Half-Rate Speculative Switched-Capacitor Decision Feedback EqualizerM. M. Isa and C.K. WongTechnical Session 5Time Paper ID Title11.00 am 1571153127Design of Rapid-Response Fail-Safe Protection Circuit for 200 V p-GaN HEMTs in LLC Half-Bridge ConvertersXinzhi Liu, Suhaidi Shafie, Mohd Amran Mohd Radzi, Norhafiz Azis, Abdul Hafiz Abdul Karim and Nurbahirah Norddin11.15 am 1571168732A 762.48 Ppm/V Line Sensitivity Current Reference Circuit in 130nm CMOS TechnologyPei Jie Chan, Harikrishnan Ramiah, Ying Yin Teo, Yee-Chyan Tan and Gabriel Chong11.30 am 1571176451Design of a BTRO-Driven Differential Low Voltage Charge Pump with Enhanced Clock Swing and Reduced CP Stages for Energy HarvestingHaresh Haridas and Harikrishnan Ramiah11.45 am 1571176477Quad-Band CMOS Rectifier for Ambient RFEH Using Stage Isolation for Impedance CompensationJamie How Peng Yong, Harikrishnan Ramiah, Yi Chen Lee and Wen Xun Lian12.00 pm 1571176537A Wide-PDR CMOS Rectifier Employing Dual Mode Technique for Ambient RF Energy HarvestingZe Xun Lee, Yan Joe Cheong, Harikrishnan Ramiah and Yi Chen Lee12.15 pm 1571176552A CMOS Rectifier with 0.9V/ 1.8V Selectable Bounded Output Voltage for IoT SensorsYan Joe Cheong, Harikrishnan Ramiah, Yi Chen Lee and Wen Xun Lian12.30 pm 1571215165A Self-Tuning Magnetically Coupled Vibration Energy Harvester with a Sliding Proof MassMohammad Farhan and Asan G.A Muthalif
2025 5th IEEE International Circuit and System Symposium17LIST OF ABSTRACTSTechnical Session 1Full paper: 1571186573Optimizing NiO Properties for Enhanced Perovskite Solar Cell EfficiencyNurbahirah Norddin, Suhaidi Shafie, Muhammad Idzdihar Idris, Xinzhi Liu and Ismail LawalPerovskite solar cell efficiency is influenced by numerous factors, particularly the materials used in its layered structure. In this study, the performance of a solar cell with the configuration NiO/Perovskite/ZnO/FTO is investigated, focusing on NiO as the hole transport layer (HTL). The research examines how variations in NiO's bandgap, interface defect density at the NiO/Perovskite interface, doping acceptor density in NiO, and NiO's carrier mobility impact critical performance metrics such as short-circuit current density (Jsc), fill factor (FF), power conversion efficiency (PCE), and open-circuit voltage (Voc). Optimizing these parameters is crucial for enhancing the overall efficiency of perovskite solar cells, especially when utilizing NiO as the hole transport layer (HTL) and ZnO as the electron transport layer (ETL). The findings indicate that minimizing interface defect density at the NiO/Perovskite contact is essential to achieving optimal efficiency. Additionally, the bandgap, carrier mobility, and doping acceptor density in NiO must be within specific ranges to maximize performance. An increase in interface defect density leads to a significant reduction in efficiency due to increased recombination at the interface. This recombination, along with impedance in the perovskite solar cell structure, directly affects the fill factor, open-circuit voltage, short-circuit current density, and overall power conversion efficiency.Full paper: 1571197751Comparative Analysis of Noise Figure in AlGaN\\GaN HEMTs with AlGaN and AlInN BackBarriersHusna Hamza, Julie Roslita Rusli, Wan Maziyah Ab. Halim, Izanoordina Ahmad, Balqis Budiman and Anwar JarndalGaN high electron mobility transistors (HEMTs) are widely adopted in high frequency and power switching applications due to their high electron mobility and large breakdown strength. The back barrier layer plays a crucial role in confining the two dimensional electron gas (2DEG) and suppressing leakage, which directly impacts the noise performance of the device. In this work, a comparative study is carried out on GaN HEMTs employing AlGaN and AlInN back barriers with varying Al mole fractions. Device level simulations are performed using Silvaco TCAD, incorporating polarization, mobility degradation, and trap assisted recombination models to capture realistic channel transport and noise mechanisms. The small signal noise characteristics are analyzed through noise figure (NF) extraction over a wide frequency range. Results indicate
2025 5th IEEE International Circuit and System Symposium18that although AlInN back barrier HEMT enhance 2DEG confinement, they exhibit reduced transconductance due to stronger alloy scattering and trap related effects, which in turn degrade the noise performance. In contrast, AlGaN back barrier HEMT demonstrate relatively higher transconductance and more stable noise figure behavior, owing to moderate confinement and lower sensitivity to defect induced scattering. This study highlights the tradeoff between carrier confinement and mobility in back barrier engineering, providing valuable insights for the design of low noise GaN HEMTs for high frequency and power applications.Full Paper: 1571199101Effect of off-Centre Ball on Lead Frame Plating and Wire Properties(Author name not provided.)This study investigates the influence of lead frame plating thickness, wire material, and forming gas (FG) flow rate on Off-Centre Ball (OCB) formation in the semiconductor wire bonding process. A total of over 1,600 free air ball (FAB) samples from 16 runs were fabricated and analyzed using bare copper (Cu) and palladium-coated copper (PdCu) wires on two types of lead frames: Type A (~140 µin Ag) and type B (~100 µin Ag), with FG flow rates ranging from 0.3–0.7 ℓ/min. The results indicate that the optimal condition—PdCu wire on type A lead frame with FG flow of 0.5–0.6 ℓ/min—achieved near-perfect FAB symmetry (0.999622) and a zero off-centre FAB rate, thus minimizing the likelihood of OCB occurrence. Overall, the findings demonstrate that PdCu wire, combined with thicker Ag plating and optimized FG flow, enhances FAB quality, reduces OCB formation, and improves bonding reliability.Full Paper: 1571174019Battery-Free and Sensor-Free Water Turbidity Sensing Using STM32 BLEJewahra Ademosman Saleh, Samsuzana Abd Aziz, Norulhuda Mohamed Ramli, Khairudin Nurulhuda, Roberto La Rosa, Orazio Aiello and Fakhrul Zaman RokhaniThe adoption of IoT-based wireless sensor networks in aquaculture is hindered by the high cost, maintenance, and continuous power needs of conventional systems, emphasizing the need for practical and low-cost solutions to monitor key water quality parameters. This paper presents an energy-autonomous wireless sensing system that indirectly measures light energy through water samples with turbidity between 1 and 10 NTU. The system operates without a battery, harvests and senses ambient light, providing time-domain data correlating with turbidity levels. Key advantages include improved energy efficiency, fewer components, greater miniaturization, and lower implementation costs. Built using off-the-shelf components on a 2 x 2 cm PCB with a 0.45 cm thickness, the device detects turbidity changes with an elapsed time, tadv sensitivity of 10.67 ms/NTU. This cost-effective, battery-free sensing solution holds promise for more accessible,
2025 5th IEEE International Circuit and System Symposium19scalable monitoring of aquaculture environments, contributing to improved fish health and optimized operational efficiency.Full Paper: 1571192247Design and Implementation of a Multi-Sensor MEMS-Based Flight Data Monitoring and Tracking System Using Hybrid Communication NetworksMohamed Tarmizi Ahmad, Michael Lam, Amzari Zhahir, Razali Abidin and Baizura BohariThe ability to continuously monitor aircraft flight parameters in real time is a crucial enabler for both operational safety and post-incident investigations. This paper presents the design and implementation of an integrated Flight Data Monitoring (FDM) and tracking system based on micro-electromechanical system (MEMS) sensors, multi-sensor fusion algorithms, and hybrid satellite–terrestrial communication protocols. The proposed system incorporates a tri-axis accelerometer, gyroscope, and magnetometer in conjunction with multi-constellation GNSS receivers (GPS/Galileo/GLONASS) to provide high-fidelity position, velocity, and attitude data. An Extended Kalman Filter (EKF) framework is implemented in the embedded microcontroller to fuse inertial and GNSS measurements, thereby reducing drift and improving estimation accuracy. The system utilises a dual-mode communication architecture combining GSM/GPRS and Iridium satellite networks, with automatic switching to ensure global coverage and minimal latency. Data is transmitted to a cloud-based fleet management server for real-time visualisation, archival storage, and post-flight analysis. Experimental validation conducted on a Cirrus SR20 aircraft demonstrates an average positional accuracy of ±2.5 m, attitude estimation within ±1.2°, and seamless communication switching with a latency of less than 1.5 seconds. The results confirm the viability of the proposed architecture as a low-cost, scalable, and globally deployable FDM solution suitable for both civil and military aviation applications.Full Paper: 1571192677Development of a Self-Diagnostic IoT-Based Aquaculture Monitoring System Using Raspberry PiDanny Chang Jun Wei, Asral Bahari Jambek, Mohd Yusri Azli Mohd Yusof and Mazlan AbbasThis paper presents the design and development of a self-diagnostic Internet of Things (IoT) system using a Raspberry Pi for real-time environmental monitoring in aquaculture farming. The system integrates multiple sensors, including pH, total dissolved solids (TDS), water temperature, water level, ambient temperature and humidity sensors. The measured data is continuously collected and transmitted to Favoriot, an IoT platform. A key feature of this design is its built-in diagnostic capability, which detects sensor or communication failures before triggering either self-recovery actions or user alerts. The system is programmed in Python and includes scheduled
2025 5th IEEE International Circuit and System Symposium20monitoring, sensor calibration, and automatic data logging. These diagnostic functions help identify hardware and software faults, thus improving overall system reliability. Based on the seven-day experimental results, the proposed design is capable of monitoring the environment effectively, performing self-diagnostics and providing timely feedback to the user.Technical Session 2Full Paper: 1571186043Self Heating Aware Temperature Analysis of Hetero Dielectric Vertically Stacked FeFinFET for Digital Circuit ApplicationsKajal Verma and Rishu ChaujarThis paper investigates the thermal impact on the analog and linearity performance of Hetero Dielectric Vertically Stacked Ferroelectric FinFET (HD-VS-FeFinFET), integrating advanced technologies like SOI, strained tri-layered channel, and ferroelectric material for improved gate control. It examines how temperature fluctuations can significantly affect device performance in terms of drain current. Also, the device exhibits a Zero Temperature Coefficient (ZTC) point at a gate voltage of 0.5 V, where the drain current remains stable across temperatures. Further, with reduction in peak gm2 and gm3 by 23.7% and 46.5% respectively along with 14.9% enhancement in 1dB compression point at 400K shows its improved linearity performance with rising temperature. Further, device self- heating effects (SHEs) in nonplanar transistors have become a serious issue in designing well-tempered CMOS devices for future logic nodes. So, this work examines the influence of Self- Heating Effects (SHEs) on the input and output characteristics of the device. Proceeding with the basic parameters of HD-VS- FeFinFET, the authors show the digital applications with the implementation of HD-VS-FeFinFET based CMOS inverter. These insights not only advance the understanding of the device but also affirm the suitability of HD-VS-FeFinFET for next- generation low-power, high-performance digital circuit applications.Full Paper: 1571189403Evaluation of 6T SRAM Bit Cells Using Mono3D Integration with Optimized MIV ConfigurationsYap Jia Jun, Noor Ain Kamsani, Roslina Mohd Sidek and Fakhrul Zaman RokhaniThis work explores the application of monolithic 3D integration (M3D) to a 6T SRAM bit cell, addressing bandwidth and area limitations in conventional 2D designs. Using a modified FreePDK45nm process, two M3D layouts were implemented: one with four monolithic inter-tier vias (MIVs) connecting both inverter inputs and outputs across tiers, and another with three MIVs using local vias at one inverter input to reduce interconnect complexity. Both designs were compared against a 2D baseline. Results show that the 3D SRAM achieves a 51.41% area reduction and 20.98-22.38% lower dynamic write power but incurs a write access time (WAT) increase of
2025 5th IEEE International Circuit and System Symposium211.34–4.22% due to added parasitic effects from MIVs. These findings demonstrate the potential of M3D SRAM for compact, low-power memory, with trade-offs in performance that warrant further optimization.Full Paper: 1571169218Robust Equivalent Transmit Beamforming Under Random Element Failures: A Stochastic Geometry ApproachAdil Farooq, Hasan Mir and Lutfi AlbashaEquivalent transmit beamforming (ETB) allows a frequency diverse array to emulate a static beampattern at a chosen spatial location. Existing ETB solutions, however, implicitly assume that all array elements remain operational, while in practice, elements may fail due to various hardware and environmental factors. This work embeds a Bernoulli-thinning model of random element outages into the ETB framework and derives a second-order cone program that provides robust beampattern fidelity under the modeled outages with high statistical confidence. Simulations confirm that the proposed design maintains the desired beampattern mainlobe and deep nulls even in the presence of element failures and demonstrates improved robustness compared to conventional minimum variance designs.Full Paper: 1571187813A Robust Hybrid Image Watermarking Scheme Using DWT, DCT, and QR Decomposition Based on Spread SpectrumMuhammad Farhan Attila, Gelar Budiman and Ledya NovamizantiDigital content protection faces the critical challenge of balancing robustness against attacks with im-perceptibility. To address this, we propose a novel hybrid watermarking scheme integrating Discrete Wavelet Trans-form (DWT) for multi-resolution analysis, Discrete Cosine Transform (DCT) for frequency-domain embedding, QR decomposition for numerical stability, and Spread Spectrum (SS) for signal modulation. Our method achieves PSNR more than 30 dB across test images with BER as low as 0.0010 under JPEG compression, outperforming existing techniques in compression resilience. The layered approach maintains content fidelity while resisting common attacks, validated through rigorous testing on standard images. This framework offers significant improvements for applications requiring both security and quality preservation.Full Paper: 1571176510Low-Voltage Reference with Enhanced CLM Immunity in 130 nm CMOS for IoT Edge Nodes
2025 5th IEEE International Circuit and System Symposium22Khang Yian Ng, Harikrishnan Ramiah, Kai Song Tan, Yee-Chyan Tan and Gabriel ChongThis paper presents a MOS-resistor-only threshold (VTH) reference circuit operating from a 0.6–2 V supply in a 130 nm CMOS process. Unlike traditional bandgap reference circuits (BGRs), which rely on bipolar BJT devices and typically require ≥1.2 V supply voltage to ensure proper biasing and headroom for analog blocks such as op-amps and current mirrors [3], the proposed design achieves a low reference voltage of 365 mV without curvature compensation or startup circuitry. A key innovation is the use of an active feedback mechanism that suppresses channel-length modulation (CLM) effects, ensuring drain-source voltage matching in the PTAT core. This technique improves current mirroring accuracy and VREF stability, even under low-nm process nodes where CLM effects are more pronounced. Simulation results validate the robustness of thedesign across supply and temperature variations.Full Paper: 1571197845Piezoelectric and Electromagnetic Hybrid Micro-Energy Harvester for Wireless Electronic DevicesMohammad Alif Akhirudin Hablee, Noor Hazrin Hany Mohamad Hanif and Mohd Ismifaizul bin Mohd IsmailEnergy harvesting offers the potential to convert ambient vibrations into usable electrical energy, thus enabling the self-powered operation of electronic devices and reducing reliance on traditional batteries. However, existing hybrid harvesters face challenges in harnessing and converting ambient vibrations effectively. Design limitations, including restricted bandwidth frequency and power losses during conversion hinder their efficiency. This study explored a hybrid energy harvester using dual PZT-5H bimorph cantilevered piezoelectric beams and wound coils. To optimize voltage output, adding proof mass and different beam arrangements were tested, along with frequency sweeps. Repulsive magnets were used to fine-tune the frequency, while impedance matching maximized power transfer. The results reveal that adding proof mass, a series connection, and a stacked arrangement of the beams increased the AC voltage. The harvester reached its peak performance of 16.79V at resonance. This high voltage was maintained at 30Hz but dropped notably at 60Hz. After rectification, the 12V AC at 18Hz yielded an 8.31V DC, which approximately aligns with theoretical expectations. Full Paper: 1571223244Performance Analysis of Horizontal Single-Axis Tracker Versus Fixed Tilted Photovoltaic Systems
2025 5th IEEE International Circuit and System Symposium23Muhamad Khairol Ab Rani, Mohd Zubir Khalid, Noor Shelida Salleh, Raja Mohd Fuad Tengku Azizand Muhamaad Fikrii ZahariThis study compares the performance of Horizontal Single-Axis Tracker (HSAT) and Fixed Tilted Photovoltaic (FTPV) systems. The primary goal is to evaluate the efficiency of a HSAT system with solar position algorithms against a FTPV system and a HSAT with a light sensor. The first part involves a concurrent comparison of three systems (fixed-tilted slightly facing south, solar tracker with light sensor, and solar tracker with solar position algorithms) to measure irradiance. The second part utilizes a row of 80 solar panels configured as a fixed tilted system set as flat and as a solar tracker system enabled with solar position algorithms. From the experiment, we found out that the HSAT outperform FTPV by 26%. The results highlight the advantages and limitations of using a single-axis tracker system, providing information on potential improvements to the efficiency of solar energy harvesting.Technical Session 3Full Paper: 1571185608A LoRa-Enabled Battery-Less Node for AI-Driven Smart AgricultureMario Costanza, Mike Hayes, Francesca Volti, Orazio Aiello and Roberto La RosaAs climate challenges intensify and resources become increasingly scarce, making agriculturemore efficient and sustainable is more crucial than ever. In this work, we introduce a completely battery-free Internet of Things (IoT) device that helps farmers make smart irrigation decisions using only solar energy. The system combines a low-power microcontroller, photovoltaic energy harvesting (EH), and a compact neural network (NN) to process real-time data from environmental sensors. A simple energy-aware schedule enables the device to determine when to collect data, run its machine learning model, and transmit results using the Long Range (LoRa) communication. All of this happens without the use of batteries or manual intervention. In field tests, the system achieved 97% accuracy in predicting when plants need water. To our knowledge, this is the first Artificial Intelligence (AI) powered sensing platform for agriculture that is entirely without battery, offering a practical and sustainable solution for precision farming.Full Paper: 1571189384Truncated Adder Integration in a Convolutional Neural Network Approximate AcceleratorLim Qi Yang, Lim Yang Wei, Fakhrul Zaman Rokhani and Noor Ain KamsaniWith the increasing demand for energy-efficient hardware to support the growing complexity of deep learning applications, optimizing power and area consumption in neural network
2025 5th IEEE International Circuit and System Symposium24accelerators has become a critical challenge. This paper investigates the integration of approximate adders into the Eyeriss architecture to improve its energy efficiency without significantly compromising output accuracy. Our results show that using 6-bit approximation achieves an average mean percentage error of 2.90%, while reducing total cell count by 16.87%, area by 18.90% and power consumption by 23.67%. Extending the approximation to 8 bits increases the error to 6.89% but yields further reductions in cell count (22.12%), area (24.58%), and power (32.22%). This study highlights the trade-off between computational accuracy and hardware efficiency for resource-constrained CNN accelerators.Full Paper: 1571189644Development of an Artificial Intelligence (AI)-Based Automated Crayfish Measurement SystemMuhamad Irwan Hakim Ahmad, Asral Bahari Jambek, Chakradhar Cheekati, Hilal A. Fadhil, Mohd Yusri Azli Mohd Yusof and Mohammad Firdaus OthmanThis study presents the development of an automated crayfish measurement system using a deep learning approach based on the YOLOv8-pose architecture. The system aims to measure the length of crayfish from top-view images by detecting head and tail keypoints and converting the pixel distances into real-world measurements. A dataset of 1,787 annotated images was collected and enhanced through data augmentation. The model was trained and validated using GPU resources on the Kaggle platform, achieving a high mean Average Precision (mAP-50) of 0.98. The system integrates OpenCV-based calibration with a reference square to ensure consistent length estimation with real-world measurement. To verify the system, pre-recorded videos containing live crayfish with moderate movement were used. The experimental results show that the system can provide reliable and accurate measurements for both small and large crayfish samples, with a measurement error margin of less than 5%. This indicates that the proposed system offers an accurate solution for automated crayfish measurement.Full Paper: 1571191742Integration of Aerial Object Detection System with Flight ControllerHilam Prasath Swami Vivekananda, Ray Anselm Hai Seng Lim, Ermira Junita Abdullah and Mohd Faisal Abdul HamidThis paper presents the design and implementation of an onboard object detection systemintegrated with a fixed-wing unmanned aerial vehicle (UAV) flight controller. The system employs a Raspberry Pi 4 and Pi Camera 3 as a lightweight vision module running a fine-tuned YOLOv8n model for real-time aerial detection. A custom dataset of 83 annotated images was collected and used for transfer learning, achieving a mean Average Precision (mAP@50–95 = 0.871) across four target classes which are buildings, cars, houses and lakes. The optimized YOLOv8n model operates
2025 5th IEEE International Circuit and System Symposium25at 2–3 FPS with FP16 precision on the Raspberry Pi 4, maintaining stable inference and acceptablepower consumption within an ~11 W system envelope. Field experiments verified onboard detection capability and operational stability under flight conditions. The results demonstrate the feasibility of deploying deep-learning-based vision models on compact, low-cost UAV platforms for aerial monitoring and environmental observation applications.Full Paper: 1571197749Introducing IEEE P7014.1: Recommended Practices for Ethical Emulated Empathy in GeneralPurpose AI SystemsAndrew McStay, Karen Bennet and Boon Chong AngAs General-Purpose Artificial Intelligence (GPAI) systems increasingly function as empathic partners, personal assistants, co-pilots, and companions, the ethical implications of emulated empathy become critical. IEEE P7014.1 establishes a Recommended Practice (RP) to guide the responsible design, deployment, and governance of empathic AI partners. This paper introduces the scope, core ethical concerns, and key recommendations of IEEE P7014.1, emphasizing its role in preventing deception, protecting user autonomy, and ensuring culturally sensitive, bias-aware AI interactions. We highlight how this standard fills a critical gap in AI ethics by focusing on downstream human-AI partnerships and provide actionable insights for researchers, developers, and policymakers to adopt its principles. The goal is to foster global awareness and accelerate the integration of P7014.1 into AI development frameworks.Full Paper: 1571200000Printed Circuit Board Defect Detection System Using Deep Learning on FPGALee Jia Qian and Nasri SulaimanThis paper presents the development and implementation of a real-time Printed Circuit Board (PCB) defect detection system using deep learning on FPGA. A YOLOv3-Tiny object detection model was trained using a publicly available dataset containing 9014 high-resolution images annotated with six common PCB defect types: missing hole, mouse bite, open circuit, short circuit, spur, and spurious copper. The training was conducted using the Hank AI Darknet framework, and the best weights were achieved at iteration 28,819 with a mean Average Precision (mAP) of 99.55%. To enable deployment on resource-limited hardware, the trained model was optimized using the DNNDK toolchain. The model was quantized to 8-bit fixed-point and compiled for execution on the Deep Processing Unit (DPU) integrated into the Xilinx PYNQ-Z2 FPGA board. Both static image inference and real-time inference were successfully executed. The FPGA-based system achieved a real-time frame rate of 2.015 FPS and a post-deployment mAP of 28.17% at IoU threshold of 0.5. Despite a reduction in detection accuracy due to quantization, the system
2025 5th IEEE International Circuit and System Symposium26remains suitable for a standalone, power-efficient, and cost-effective PCB defect detection system for real-time industrial applications.Full Paper: 1571200620Evaluating YOLOv8-Pose Model Variants for Accurate Pose Estimation in Oil Palm Ripe Fresh Fruit Bunches (FFB) DetectionRozilawati Mohd Nor, Wan Zuha Wan Hasan, Hafiz Rashidi Ramli, Muhamad Saufi Mohd Kassim, Nazmi bin Mat Nawi and Nor Mohd Haziq NorsahperiThis study applies YOLOv8-pose variants of nano, small, and medium to detect ripe Fresh Fruit Bunches (FFB) and estimate their poses for orientation analysis in oil palm plantations. A custom dataset of ripe FFB images was annotated with five key point annotations representing anatomical features to support pose estimation. Comparative analysis shows that YOLOv8s achieved the highest mAP 50 of 90.01%, which is 2.3% higher than YOLOv8n and 0.23% higher than YOLOv8m. For pose estimation, YOLOv8s also led with mAP of 89.20% outperforming YOLOv8s and YOLOv8m. Despite this, YOLOv8n offered the best efficiency, with only 3.5 million parameters and a recall of 99.25%. On the other hand, validation loss analysis further confirms the robustness and efficiency of YOLOv8s-pose, which recorded a total loss value that was almost 4.4% lower than YOLOv8n and 6.8% lower than YOLOv8m. These findings indicate that either YOLOv8n or YOLOv8s poses as a suitable base architecture for future improvements, focusing on refining key point definitions, expanding datasets, and optimizing the backbone with lightweight convolutional blocks. It also highlights the model’s efficiency in handling the irregular topology of FFBs and its suitability for real-time applications.Full Paper: 1571200634Dynamic Experience Management for Mobile Robot Navigation in Dynamic EnvironmentsYingjie Zhu, Wan Zuha Wan Hasan, Hafiz Rashidi Ramli, Nor Mohd Haziq Norsahperi and Muhamad Saufi Mohd KassimIn dynamic navigation scenarios, traditional reinforcement learning algorithms often suffer from limited generalization and inefficient experience utilization. To address these limitations, this study proposes an improved Twin Delayed Deep Deterministic Policy Gradient algorithm that incorporates a training-phase-aware scheduling mechanism. Specifically, the replay buffer size and batch size are dynamically adjusted using a smooth growth function to align with different training stages. Comparative experiments show that the improved TD3 outperforms the baseline in terms of average reward, collision rate, and convergence speed, demonstrating its effectiveness andadaptability in dynamic navigation tasks.
2025 5th IEEE International Circuit and System Symposium27Technical Session 4Full Paper: 1571178849A Natively Flexible 8-Bit Differential Resistive Ladder SAR-ADCMohsen Padash, Leon Brindley, Adam Rearden, Thom Smith and Brian CobbThis paper presents a novel structure for a fully differential Successive-Approximation Register Analog-to-Digital Converter (SAR-ADC) Flexible Integrated Circuit (FlexIC). The ADC’s fully differential structure makes it very robust against DC offset variance caused by supply voltage and temperature variation, resulting in consistent performance in a broader range of operation scenarios. Measurement results indicate the ENOB (Effective Number of Bits) is about 7.47 bit. Also, measurement results post-fabrication show that the circuit achieves a maximum INL of ± 1.5 LSB, with a footprint of just 3.3mm2 and consuming 0.84mW power.Full Paper: 1571179208Comparison Between Gate-Driven CMFBs on Inverter-Based OTAs in Multiple SpecificationsNgo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran and Orazio AielloResizing an Ultra-Low-Voltage (ULV) operational transconductance amplifier (OTA) topology to target different optimizations can be a significant challenge. This obstacle can be mitigated by using digital standard cells with an automatic place-and-route flow, thereby reducing design effort. Taking advantage of this approach, this paper explores the impact of gate-drivencommon-mode feedback (CMFB) on ULV inverter-based OTAs using digital NAND and/or NOR in the CMFB, six OTA circuits in total. By varying the drive-strength sets of digital inverters, our OTAs can target multiple specifications at a supply voltage of 0.3V. For example, with the TSMC 65nm technology node, one OTA can achieve the smallest area cost, approximately 24.48 μm2, while another can maximize FoMS, reaching around 203.14 kHz · pF/nW.Full Paper: 1571184684Low-Power Inverter-Based Fully Differential OTA in Flexible Integrated Circuit TechnologyNoor Ul Amin, Orazio Aiello, Fakhrul Zaman Rokhani and Roslina Mohd SidekThis paper presents a fully differential two-stage inverter-based operational transconductance amplifier (OTA). It utilizes inverters based on standard cells featuring 600nm thin-film transistors (TFTs) in flexible integrated circuits (FlexICs) technology, as provided by the pragmatic PDK. The OTA operates at a power supply of 3V and achieves a differential gain of 34 dB with a gain bandwidth (GBW) of 111 kHz using a 50-pF capacitive load. Despite maintaining comparable
2025 5th IEEE International Circuit and System Symposium28performance to the previous Flexible OTAs, this design exhibits a very low power consumption of 9.2 μW, accompanied by a high slew rate of 535 V/ms. The input-referred integrated noise over the entire GBW is 178 μVRMS. The OTA performance is compared to that of state-of-the-art flexible TFT-based amplifiers, with a focus on power consumption, GBW, and drive capability. It achieves remarkable performance with a figure of merit (603 MHz.pF/mW) that ranges from 2X to 826X compared to others.Full Paper: 1571186795Ultra-Low-Power Multi-Level Voltage Reference Circuit in TFTs-Based Flexible Circuit TechnologyNoor Ul Amin, Roslina Mohd Sidek and Fakhrul Zaman RokhaniVoltage reference circuits with PVT (Process, Voltage, Temperature) robustness and low power characteristics are key components applied in low power analog and mixed-signal systems. This paper presents a multi-level voltage reference circuit in Flexible Integrated Circuits (FlexICs) utilizing 600nm single N-type thin-film transistors (TFTs) provided by the Pragmatic PDK. The circuit is simulated with a supply voltage range from 1.3 V to 3 V and validated over a temperature range of -10 °C to 85 °C. It results in three different voltage references as outputs named VREF3, VREF2, and VREF1, which are 1.25 V, 0.830 V, and 0.42 V, respectively. With a supply voltage of 1.3 V, it has a total power consumption of only 53.8 pW with temperature coefficients (TC) of 491 ppm/°C, 490 ppm/°C, and 487 ppm/°C for VREF3, VREF2, and VREF1, respectively. The line regulation (LR) for VREF3 is 0.68 %V, VREF2 is 0.45 %V, and VREF1 is 0.23 %V. The area occupied by the design is only 715 μm2. The circuit provides robust performance in the presence of process variations and can be used for ultra-low power, area-constrained, and multi-level voltage reference applications in next-generation flexible-based integrated systems.Full Paper: 1571192457Low-Latency 1.5-Bit Quantizer for a 400 Mbps Continuous-Time Sigma-Delta Modulator in 65 nm CMOS for Biomedical InstrumentationWang Shengquan, Jagadheswaran Rajendran, Selvakumar Mariappan, Norhamizah Idros, Asrulnizam Abd Manaf, Narendra Aridas, Arokia Nathan and Binboga S. YarmanThis paper presents the design and post-layout simulation of a 1.5 bit flash quantizer operating at 400 Mbps for integration in a continuous-time (CT) sigma-delta modulator targeting biomedical instrumentation applications. The quantizer adopts an over-range tolerant scheme to enhance modulator stability and relax comparator precision requirements, offering improved robustness against device mismatch. A fully differential preamplifier-dynamic latch comparator pair is employed to achieve low decision latency while maintaining high linearity, with careful device
2025 5th IEEE International Circuit and System Symposium29sizing and common-centroid layout techniques used to minimize input offset. Post-layout simulation in a 65 nm CMOS process confirm correct operation at 400 Mbps with a decision delay below 400 ps and negligible metastability. The design achieves a peak SNDR of 71 dB over a 6 MHz bandwidth, consuming only 65 uW from a 1.2 V supply, and occupies 0.2025 mm2 active area. These results demonstrate the suitability of the proposed quantizer for compact, energy-efficient CT sigma–delta modulators in medical imaging and bio-signal/cell analysis applications.Full Paper: 1571197450A 14 Bit 1 GS/s Segmented CMOS DAC with Glitch-Free Switching for 5G New Radio Sub-6 GHz TransmittersNorhamizah Idros, Jagadheswaran Rajendran, Selvakumar Mariappan, Sofiyah Sal Hamid, Asrulnizam Abd Manaf, Narendra Aridas, Arokia Nathan and Binboga S. YarmanThis paper presents a 14 bit, 1 GS/s segmented CMOS DAC with a glitch free switching mechanism for 5G New Radio (NR) transmitters. Fabricated in 65 nm CMOS and operating from a 1 V supply, the design combines a 6 bit current steering (CS) MSB section with an 8 bit binary weighted resistive ladder (BWRL) LSB section, achieving an efficient tradeoff between speed and power. A flip-flop based synchronization circuit ensures glitch free transitions and enhances spectral purity. The prototype occupies 0.05 mm², consumes 30 mW, and achieves differential nonlinearity (DNL) between -0.17 LSB and +0.15 LSB and integral nonlinearity (INL) from -0.25 LSB to +0.27 LSB. Measured performance shows signal-to-noise ratio (SNDR) of 78 dB and spurious-free dynamic range (SFDR) of 80 dB at 10 MHz, and 72 dB/75 dB at Nyquist, with robustness within ±5% across PVT. Benchmarking against recent works, the proposed DAC achieves the highest Schreier figure of merit (177 dB), confirming its suitability for compact, and energy efficient 5G NR sub 6 GHz transmitters.Full Paper: 157119828623.7 fJ/Conv. Double-Tail Dynamic Comparator Design Using 180nm CMOS TechnologyJulie Roslita Rusli, Suhaidi Shafie, Wan Maziyah Ab Halim, Izanoordina Ahmad, Balqis Budiman and Roslina Mohd SidekThe performance of a Successive Approximation Register (SAR) ADC is critically influenced by the precision of its comparator, which is responsible for resolving the least significant bit (LSB) within stringent timing constraints. With continued scaling in nano-scale technologies, supply voltages are increasingly reduced to enhance dynamic energy efficiency. However, this reduction in voltage headroom poses significant design challenges for dynamic comparators, often driving transistors into the subthreshold regime and compromising accuracy. This work presents the design of an ultra-low power, high-precision dynamic comparator tailored to reliably resolve a 0.8
2025 5th IEEE International Circuit and System Symposium30mV differential input under a 0.8 V supply. Targeting integration into a 200 kS/s, 10-bit differential SAR ADC, the design is implemented using Silterra 180 nm CMOS technology, characterized by a threshold voltage (VTH) of approximately 0.4 V. The comparator architecture is optimized through careful transistor sizing to minimize bias currents and to operate with gate-source voltages (VGS) close to VTH value. Simulation results confirm that the comparator achieves accurate resolution of 0.8 mV input differences with an average power consumption of 47 nW and a Figure of Merit (FoM) of 23.7 fJ/conversion.Full Paper: 1571201848A Half-Rate Speculative Switched-Capacitor Decision Feedback EqualizerM. M. Isa and C.K. WongDecision feedback equalizers (DFEs) are widely used in communication receivers to compensate for inter-symbol interference (ISI) and ensure reliable data recovery. However, conventional implementations based on current-mode logic (CML) latches suffer from high static power consumption, making them inefficient for energy-constrained applications. This work presents a half-rate speculative switched-capacitor DFE incorporating a PMOS-input StrongARM latch (pSAL) slicer. The proposed design eliminates static bias current in the latch and common-mode biasing in the summer, achieving significant energy savings. Implemented in the Cadence GPDK045 process, the proposed DFE extends the horizontal eye margin from a closed eye to 52.5% at a BER of 10-4, demonstrating effective ISI mitigation and improved data recovery. The figure of merit (FOM), defined as the energy consumed per bit normalized to channel loss, achieved by the proposed DFE is 0.012 pJ/bit/dB, representing an 88% reduction compared to the conventional switched-capacitor DFE, while the pSAL-based slicer achieves 0.003 pJ/bit/dB, corresponding to a 95.5% improvement over the conventional CML latch-based slicer. These results validate the proposed architecture as an energy-efficient solution for communication receiver applications.Technical Session 5Full Paper: 1571153127Design of Rapid-Response Fail-Safe Protection Circuit for 200 V p-GaN HEMTs in LLC HalfBridge ConvertersXinzhi Liu, Suhaidi Shafie, Mohd Amran Mohd Radzi, Norhafiz Azis, Abdul Hafiz Abdul Karim and Nurbahirah NorddinRapid-switching 200 V Schottky p-type gallium nitride high-electron-mobility transistors (p-GaN HEMTs) enable high-efficiency half-bridge inductor–inductor–capacitor (LLC) resonant conversion with near-soft-switching transitions; however, residual resonant current at commutation can
2025 5th IEEE International Circuit and System Symposium31induce crosstalk-driven false gate activation and destructive short-circuit events. This paper presents an analog fail-safe protection circuit that concurrently monitors the gate-drive and direct-current (DC) bus voltages using dual-path absolute-value detection with tailored threshold logic to identify both bootstrap-induced and conventional fault signatures. Upon detection, both high- and low-side switches are isolated in <120 ns, preventing device overstress. The scheme is validated by SPICE simulations and multipulse bench experiments at a DC-bus range of 120–200 V and 400 kHz switching frequency, confirming reliable fault recognition and shutdown across varied load conditions without complex sensors or integrated circuits (ICs). The proposed approach significantly enhances short-circuit robustness in GaN-based resonant converters.Full Paper: 1571168732A 762.48 Ppm/V Line Sensitivity Current Reference Circuit in 130nm CMOS TechnologyPei Jie Chan, Harikrishnan Ramiah, Ying Yin Teo, Yee-Chyan Tan and Gabriel ChongThis paper presents a high-accuracy, supplycompensated current reference circuit operating from a 1.2–1.8 V supply in a 130 nm Complementary Metal-Oxide-Semiconductor (CMOS) process. The proposed design achieves a line sensitivity of 762.48 ppm/V and temperature coefficients (TC) of 2423.42 ppm/°C and 2290.02 ppm/°C over temperature ranges of 0 °C to 70 °C and −25 °C to 125 °C, respectively—unlike conventional current reference circuits, which are unable to compensate for both supply and temperature variations simultaneously. By implementing a self-biased current source based on a beta-multiplier circuit, the design minimizes the effect of input voltage fluctuations on the output current while maintaining power consumption below twice the reference current. The robustness of the design across supply and temperature variations is verified by the simulation results presented in this paper.Full Paper: 1571176451Design of a BTRO-Driven Differential Low Voltage Charge Pump with Enhanced Clock Swing and Reduced CP Stages for Energy HarvestingHaresh Haridas and Harikrishnan RamiahThe inefficiency and sizing of most devices leans to the addition of charge pumps are to be implemented but it has its shortcomings. This brief presents a compact, fully-integrated threestage charge pump (CP) architecture designed for energy-harvesting applications. Designed for low input voltages, the proposed design incorporates a differential bootstrapped ring voltagecontrolled oscillator (BTRO) that generates six-phase clock signals with enhanced voltage swing output. The usage of amplified and stepped-up replica clock signals enables efficient CP operation by reducing the number of required stages while maintaining high voltage gain, thereby significantly improving the complete switching on and off of transistors and the power conversion
2025 5th IEEE International Circuit and System Symposium32efficiency (PCE). Additionally, the deployment of replica clocks prevents the load capacitance of the pump from affecting the timing and amplitude of the ring oscillator. Implemented in a 65-nm CMOS process, the prototype achieves a boosted output voltage from an input of 0.25V under a 1MΩ load, with a measured PCE of 48.2%.Full Paper: 1571176477Quad-Band CMOS Rectifier for Ambient RFEH Using Stage Isolation for Impedance CompensationJamie How Peng Yong, Harikrishnan Ramiah, Yi Chen Lee and Wen Xun LianA quad-band rectifier capable of operating at 0.9, 1.8, 2.1 and 2.4GHz using 65nm CMOS technology is presented in this paper. A novel method is proposed to counteract the change in circuit impedance at higher operating frequency by isolating additional rectifier stages, which are inherently capacitive, to enable maximum power transfer across the quad-bands. A 2-bit control signal toggles pairs of CMOS transmission gates which decouples unit stages to reconfigure the rectifier from 14 to 8, 5 and 3 stages, reducing circuit reactance. The rectifier exhibits an S11 reflection coefficient of <−15.9dB at the targeted frequencies, with a peak PCE of 51.9% @ 900MHz at 1dBm input power. This design approach is scalable for additional frequencies without the need to increase matching components, requiring lower chip area than existing approaches, achieving an active area of 0.326mm2.Full Paper: 1571176537A Wide-PDR CMOS Rectifier Employing Dual Mode Technique for Ambient RF Energy HarvestingZe Xun Lee, Yan Joe Cheong, Harikrishnan Ramiah and Yi Chen LeeThis paper proposes a wide input range cross-coupled differential-drive (CCDD) rectifier for ambient RF energy harvesting, designed in 65 nm CMOS process. A dual-mode configuration is introduced, employing adaptive gate biasing to optimize power conversion efficiency (PCE) acrossvarying RF input power. In the high-power mode, a feedback circuit suppresses reverse leakage currents, while in the low-power mode, a gate boosting technique enhances forward current, improving PCE at low RF input power. The post layoutsimulation results show the rectifier exhibits a wide PCE dynamic range (PDR) of 18.6 dB at 900 MHz with a PCE of 65.7% and a sensitivity of -12 dBm at 1 V output across a 100 kΩ resistive load. This rectifier demonstrates the widest PDRcompared to the recent state-of-the-art design, showing its high adaptability to fluctuating RF input powers, making it well-suited to power Internet of Things (IoTs) applications.Full Paper: 1571176552
2025 5th IEEE International Circuit and System Symposium33A CMOS Rectifier with 0.9V/ 1.8V Selectable Bounded Output Voltage for IoT SensorsYan Joe Cheong, Harikrishnan Ramiah, Yi Chen Lee and Wen Xun LianThis paper presents a 900MHz CMOS rectifier with selectable bounded output voltage at 0.9V or 1.8V, targeting for low power Internet of Thing (IoT) applications. The proposed rectifier is integrated with an auxiliary rectifier, a voltage sensor and a voltage limiter. The auxiliary rectifierprovides a reference voltage to the voltage sensor, which generates control signals based on the sensed voltage. These control signals control the voltage limiter to bound the main rectifier output voltage. The voltage limiter utilizes a voltage divider topology to branch out two different nodes, 0.9V and 1.8V. The proposed rectifier is simulated in Cadence Virtuoso using TSMC 65nm technology. The post-layout simulations show the rectifier achieves an operating range of 6 dB and 3 dB for 0.9V mode operation and 1.8V mode operation respectively.Full Paper: 1571215165A Self-Tuning Magnetically Coupled Vibration Energy Harvester with a Sliding Proof MassMohammad Farhan and Asan G.A MuthalifThe growing demand for sustainable and self-sufficient power sources has driven extensive research in vibration-based energy harvesting technologies. This study presents a self-tuning magnetically coupled vibration energy harvester (VEH) that utilizes a sliding proof mass mechanism for adaptive frequency tuning. The harvester employs magnetic repulsion between a sliding magnet and a fixed tip magnet to achieve nonlinear stiffness and broadband frequency response. The experimental results demonstrated that the self-tuning energy harvester generates an average voltage of 2.4 V/g as compared to 1.2 V/g of a conventional energy harvester. The highest output voltage of 5.9 V/g at 36.6 Hz for self-tuning, whereas 7.4 V/g at 38.1 Hz for conventional has been recorded. The sliding mass mechanism passively tunes the system by responding to centrifugal and gravitational forces, eliminating the need for active control electronics. This improvement addresses key limitations in traditional harvesters, such as narrow bandwidth and sensitivity to frequency mismatches. The system exhibits self-tuning capability, allowing it to maintain resonance across varying excitation frequencies, making it suitable for realworld ambient vibration applications.Return to the top of Technical Sessions
2025 5th IEEE International Circuit and System Symposium34SPONSORSHIP
2025 5th IEEE International Circuit and System Symposium35WEBSITE:https://icsys2025.cas.ieeemy.org