EDINS Design Guide line - HDI Advanced

HDI PCB

Technology Roadmap
Design Guide Line

2019

EDINS , Made in Korea
[email protected]

HDI PCB
Technology Roadmap

2

HDI PCB Technology Roadmap 1

Items Y2019 Y2020

Key Index [um] Mass Proto Mass Proto
←
BGA Pitch(Outer layer) 0.35mm 0.3mm ← 0.25mm
←
Cu 15um 30/40 um 30/35 um ← 30/30 um
←
Cu 18um 40/40 um 35/40 um ← ←
Cu 25um ←
Tenting Cu 30um 60/60 um 50/60 um ← ←
(Panel Cu 35um ←
Fine Trace/ Space Plating) Cu 40um 70/70 um 60/60 um ← ←
Pitch (based on
80/80 um 75/75 um ← ←
Micro Via Finished CuT)
/ Pad size 90/90 um 80/80 um ← ←

Stack-up mSAP Cu 15um 30/30 um 25/25 um ← 20/20 um
(Thin PCB) (Pattern Cu 20um ←
Plating) Cu 25um n/a 25/30 um ← 25/25 um
←
n/a 25/35 um ← 25/25 um
←
THK. 65um ↓ 90/170 um 60/140 um(LTH) ← 50/130 um(LTH)
THK. 70 ~ 80um ←
Core 100/180 um 60/140 um(LTH) 50/130 um(LTH)
Layer
40 um ← ←
Annular ring 70/170 um 70/150 um(Skive) 70/140 um(Skive)
80/180 um 80/160 um(Skive) 80/150 um(Skive)
THK. 40um ↓ 100/200 um 100/180 um(Skive) 100/170 um(Skive)

Pre-preg THK. 60um ↓ 50 um 40um 35um
Layer THK. 80um ↓ 14L ← 16L
50um ← 40um
Annular ring ← 20um(#1010)
25um(#1017)
Max. Layer Count (Anylayer)

Min. Core Thickness

Min. Pre-preg Thickness

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HTDecIhPnCicBal TReoacdhmnaoplogy Roadmap 2

Items Y2019 Y2020
Key Index [um]
Mass Proto Mass Proto
Through DHS 0.25 Φ 0.2 Φ ← 0.15 Φ
Via Aspect ratio (Thin Board) 2.7 : 1 2.75 : 1 ← 3.0 : 1
←
Via drill & Micro Aspect ratio Non Fill 1.0 : 1 ← ←
Cu Plating Via (Depth Fill

/Window) 0.8 : 1 0.85 : 1 ← 0.9 : 1

SRR +/-25 um +/-20 um ← +/-15 um

Min. Blue / Green 140 um 120 um ← ←
SRO size
Black 200 um 180 um ← ←
Min.
PSR SR Dam Blue Circle 25 um ← ← 20 um
width /Green Rectangular
Surface 65 um 60 um ← ←
Finish
Router Circle 25 um ← ← 20 um
Rectangular
Black

75 um 70 um ← ←

Single Finish ENIG, ENEPIG, OSP, Hard gold, Immersion Tin, PB Free HAL

Hybrid Finish ENIG+OSP, ENIG+OSP+Hard gold, OSP+Hard gold
±100 um
Standard Type ±50 um

Optical Type

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HDI PCB
Design Guide Line

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CONTENTS

 INTERNAL LAYER(SIGNAL)
 INTERNAL LAYER(VCC/POW)
 EXTERNAL LAYER
 SOLDER MASK
 SILK
 DRILL
 PLATING
 SURFACE FINISH
 PRESS(LAMINATION)
 ROUT
 V-SCORING/BEVEL
 HDI
 MATERIAL
 AVAILABLE WORKING SIZE
 WORKING PANEL &AVAILABLE AREA

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INTERNAL LAYER(SIGNAL)

Design Rules Feature Description Preferred Min R&D
(before compensation) Production Production
S Capability Capability L : <125㎛ [5mil]
2 Oz L : Line Width S : <125㎛ [5mil]
(70㎛) S : Pad to Pad L : 150㎛ [6mil] L :125㎛ [5mil]
Pad to Line S : 150㎛ [6mil] S :125㎛ [5mil] L : <50㎛ [2.0mil]
Min 1 Oz Line to Line S : <50㎛ [2.0mil]
Trace (35㎛) L : 60㎛ [2.4mil] L : 50㎛ [2.0mil]
Width & SL S : 60㎛ [2.4mil] S : 60㎛ [2.4mil] L :<40㎛ [1.6mil]
Space 3/5Oz S :<40㎛ [1.6mil]
(21㎛) Controlled Impedance Tolerance L : 40㎛ [1.6mil] L : 40㎛ [1.6mil]
Trace Witdh ≤ 100㎛(3.9mil) S : 50㎛ [2.0mil] S : 45㎛ [1.8mil] L :<35㎛ [1.4mil]
1/2 Oz S :<35㎛ [1.4mil]
(18㎛) Trace Witdh ＞100㎛(3.9mil) L : 40㎛ [1.6mil] L : 35㎛ [1.4mil]
S : 40㎛ [1.6mil] S : 40㎛ [1.6mil] L :<30㎛ [1.2mil]
1/3 Oz S :<30㎛ [1.2mil]
(12㎛) L : 35㎛ [1.4mil] L : 30㎛ [1.2mil]
S : 40㎛ [1.6mil] S : 40㎛ [1.6mil] <± 10%

Impedance ≥ ± 10%

± 15㎛

Trace Tolerance ± 15%

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INTERNAL LAYER(SIGNAL)

Design Rules Feature Description Preferred Min Production R&D
Production Capability
Min Capability
Annual Ring
DHS+(2XX ㎛) - . AR = IPC-6012 Class 3 125㎛[5mil] 104㎛ [4.1mil]
[ PAD Size – DHS] / 2 (Min A/R 1mil) 89㎛ [3.5mil]

AR

IPC-6012 Class 2 100㎛ [4mil]
(90° Breakout)

Min 175㎛ [7mil] 150㎛ [6mil] <150㎛ [6mil]
Trace
to NPTH

Min Board Edge
Trace to
Routed edge 250㎛ [10mil] 200㎛ [8mil] <200㎛ [8mil]

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INTERNAL LAYER(VCC/POW-NEGATIVE)

Design Rules Feature Description Preferred Min R&D
Production Production
Capability Capability

Min -. D2M = 200㎛ [8mil] 175㎛ [7mil]
Clearance Anti Pad [Anti PAD Size – DHS] / 2
Size=DHS+(2XX)
(After Compensation)

D2M(Drill to Copper)

A: Thermal Pad Inner Diameter A A
B: Thermal Pad Outer Diameter ->Bit + 355㎛ ->Bit + 300㎛

(14mil) (11.8mil)

Thermal PAD A B B
-> Bit + 865㎛ -> Bit + 800㎛
(34mil) (31.5mil)

B

Copper Sliver Remove Copper 75㎛ [3mil] ← ←
Sliver Less Than
75㎛ [3mil]

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INTERNAL LAYER(VCC/POW-NEGATIVE)

Design Rules Feature Description Preferred Min R&D
Production Production
Tear-drop Capability Capability
Or Fillet
Adding MFG
Tear- Drop recommend to add tear-drop as below as :
Adding tear-drop for all via pad.

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EXTERNAL LAYER

Design Rules Feature Description Preferred Min R&D
(Before Compensation) Production Production
S Capability Capability L :<125㎛ [5.0mil]
Min Trace 70㎛ S :<125㎛ [5.0mil]
Width/Spacing 50㎛ L : Line Width L : 150㎛ [6.0mil] L : 125㎛ [5.0mil] L :<75㎛ [3.0mil]
(Base Copper + Plating) 35㎛ S : Pad to Pad S : 150㎛ [6.0mil] S : 125㎛ [5.0mil] S :<85㎛ [3.3mil]
25㎛
Impedance Pad to Line L : 100㎛ [3.0mil] L : 75㎛ [3.0mil] L :<60㎛ [2.4mil]
Line to Line S : 100㎛ [4.0mil] S : 85㎛ [3.3mil] S :<60㎛ [2.4mil]
SL
Controlled Impedance L : 65㎛ [2.6mil] L : 60㎛ [2.4mil] L :<50㎛ [2.0mil]
Tolerance S : 65㎛ [2.6mil] S : 60㎛ [2.4mil] S :<55㎛ [2.2mil]
Trace Witdh ≤ 100㎛(3.9mil)
L : 60㎛ [2.4mil] L : 50㎛ [2.0mil] <± 10%
Trace Witdh ＞100㎛(3.9mil) S : 60㎛ [2.4mil] S : 55㎛ [2.2mil]

≥ ± 10%

Trace Tolerance ± 15㎛
± 15%

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EXTERNAL LAYER

Design Rules Feature Description Preferred Min R&D
(before Production Production
Capability
compensation) Capability

Min Trace 175㎛ [7mil] 150㎛ [6mil] <150㎛ [6mil]
to NPTH

Min Trace to 250㎛ [10mil] 200㎛ [8mil] <150㎛ [6mil]
Routed edge

IPC-6012 Class 3 140㎛[5.5mil] 117㎛ [4.6mil] ←
(Min A/R 2mil) ←
Min Pad
Annual Ring - . AR =
DHS+(2XX) [ PAD Size – DHS] / 2

IPC-6012 Class 2

AR (Not greater than 125㎛ [4.9mil] 100㎛ [4mil]

90° Breakout)

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EXTERNAL LAYER

Design Rules Feature Description Preferred Min Production
Production Capability
Min Capability R&D
Non-plated
Hole edge to 200㎛ [8mil] 150㎛ [6mil] <100㎛[4mil]
Board edge

Tear-drop MFG recommend to add tear-drop
Or Fillet as below as : Adding tear-drop for all plated hole’s pad

Global Fiducial Mark
Fiducial Mark -Size

Fiducial S/M Clearance size +1,000㎛ [40mil]
-Shape

Round
Rectangle

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SOLDER MASK Feature Description Preferred Min R&D
Production Production
Design Rules Capability Capability

Min S/M Clearance Size SMD’s BGA’s PTH’s
(Only One Side Clearance
50㎛ [2mil] 34㎛ [1.3mil] <34㎛ [1.3mil]
And
Only Hoz Base Copper Base) Green 76㎛ [3mil] 70㎛ [2.7mil] <70㎛[2.7mil]
And
Min S/M DAM Width For QFP 120㎛ [4.7mil] 110㎛ [4.3mil] <110㎛[4.3mil]
And Blue Ink
BGA
Black Ink
(In hole
development)

BGA DAM 44㎛ [1.7mil] 25㎛ [1mil] <25㎛[1mil]

Min S/M CHIP S/ M CHIP 25㎛ [1mil] 13㎛ [0.5mil] <13㎛ [0.5mil]

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SOLDER MASK Feature Description S/M Clearance Size

Design Rules A:DHS DHS+125㎛ [5mil] Recommended that vias be
VIA B:External Layer SR Opensize encroached
C:External Layer Pad size
Encroachment
(Coating) A:DHS External Layer Pad+100㎛ [4mil] recommended
B:External Layer Pad size only for ICT Test point
VIA Open C:External Layer SR Opensize

Squeezing
From Both side view S/M

Prefer to encroach the via on Top & Bottom
and then Plug Vias from the Top & Bottom side.

Tenting

Thickness 0.4T [16mil] ≤ thickness ≤ 2.0T [80mil]

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SILK Feature Description Preferred Min R&D
Production Production
Design Rules Capability Capability
Min Line Width
100㎛ [4mil] 90㎛ [3.6mil] <90㎛ [3.6mil]

Min Character Height

650㎛ [26mil] 500㎛ [20mil] <500㎛ [20mil]

A

Silk Clearance S/ M Open
PAD
100㎛ [4mil] 89㎛ [3.5mil] <89㎛ [3.5mil]

C

SILK

B

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DRILL

Design Rules Feature Description Capability

LASER SIZE LAND TOLERANCE
0.07~ 0.15㎜ Above Drill +0.15 ㎜ +0.08 ㎜ / - Hole Size
VIA Below 1.0t : 0.20~0.30㎜ Above Bit +0.225 ㎜
Exceed 1.0t : 0.30~0.35㎜ Above Bit +0.225㎜ +0.08 / - Hole Size
PTH 0.20 ~ 4.00㎜ Above Bit +0.35 ㎜ +0.08 / - Hole Size
NPTH 0.20 ~ 3.00 ㎜
Slot PTH 3.05 ~ 6.40 ㎜ Above Bit +0.35 ㎜ +0.08 / -0.08㎜
Slot NPTH 0.5 ~ 4.0 ㎜ +0.05 / -0.05㎜
0.6 ~ 6.4 ㎜ +0.08 / -0.08㎜
+0.10 / -0.10㎜
+0.10 / -0.10㎜

Drill Spec
&

tolerance

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PLATING

Design Rules Feature Description Preferred Min R&D
Board Thickness Metal to Metal without S/R thickness Production Production
Capability T>2.0
Capability T>[80mil]

T≤1.6 1.6<T≤2.0
T≤[63mil] [63mil]<T≤[80mil]

PTH Aspect Ratio (Aspect Ratio = B/A) ≤6:1 ≤8:1 8:1<
MVH Aspect Ratio B Min hole size ≥ ≤0.8:1 0.8:1<

A

A

(Aspect Ratio = B/A) ≤0.65:1
B

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PRESS(LAMINATION) FOR HDI BUILD UP PCB

Design Rules Preferred Production Min Production R&D
Capability Capability 536X617[21.5X25inch]

Size 457X610 [18X24inch]
(MASSLAM application) 510X610 [20X24inch]

Overall Thickness T≤1.6 1.6<T≤2.0 T>2.0
T≤[63mil] [63mil]<T≤[80mil] T>[80mil]
Overall thickness Below 0.8T
Above 0.8T Tolerance≥± 10% Tolerance≥± 8% Tolerance<± 10%
Tolerance 16L
※ thickness tolerances Tolerance≥± 10% Tolerance<± 8%
require prior consultation Core 4PNL >16L
12L
Max Lamination BUP >Core 4PNL
Layer MLB <Core 3PNL

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ROUTE ( MILLING)

Design Rules Feature Description Preferred Maxim㎛ R&D
Production Production
Rout Capability Capability
to Rout
Tolerance ≥ ± 150㎛ [5.9mil] ≥ ± 100㎛ [3.9il] <± 80㎛[3.1mil]

Hole(Center) to Rout General ≥ ± 150㎛ [6mil] ≥ ± 100㎛ [4mil] < ± 100㎛ [4mil]
Tolerance
General ≥ ± 200㎛ [7mil] ≥± 150㎛ [6mil] <± 150[6mil]
Image(Center) to
Rout Optical router ≥ ± 75㎛ [3mil] ≥ ± 50 [2mil] < ± 50㎛[2mil]

Tolerance ≥ Φ0.8 [32mil] ≥Φ0.6 [24mil] <Φ0.6 [24mil]

Min Bit size
(Diameter, D)

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V-SCORING

Design Rules Feature Description Preferred Min R&D
Board thickness Production Production
Capability Capability ＜ 0.5T or >2.0T
[<20mil or >96mil]
0.5~2.0T
[20~96mil]

Web thickness(A) Board thickness x 1/3 -

V- Score~Pattern (30, B)
scoring ① T≤1.0t [40mil]
② 1.0t < T ≤1.6t
① ≤ 200㎛ [8mil] ① ≤ 150㎛ [6mil] ① < 150㎛ [6mil]
[40mil] [61.81mil] ② ≤ 350㎛ [14mil] ② ≤ 300㎛ [12mil] ② < 300㎛ [12mil]
③ ≤ 400㎛ [16mil] ③ ≤ 350㎛ [14mil] ③ < 350㎛ [14mil]
③ T≤2.0t [78.74mil]

Angle(F, degree) 30’, 45’ --

Cut Size 150mm:150mm＜ S＜150mm :150mm
(X Direction : Y Direction) S S＞300mm:600mm

Unit: mm ＜300mm:600mm

※ The above Table are V- scoring capacities in production. Customer requirements outside of these capabilities to are handled case by case.

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BEVELING /CHAMFERING

V-SCORE / BEVEL Feature Description Preferred Minimum R&D
Production Production
Design Rules Capability Capability

Bevel Available Angle/Tolerance(A) No Limit /± 10˚ --
Distance(B) 50㎛≤ B ≤ 350㎛ - 100㎛≤ B ≤ 300㎛
--
Distance(B) Tolerance ±150㎛ - ＜0.75T
Thinkness ≥0.75T

※ Thickness 0.75T, Distance(B)

-> When Distance(B) controlled Above 350㎛, we can controlled mass production.

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H D I Design B A D I
B’ F EF D’ I’
C I’’
C’ H GH
Note
H’ G’ H’ D’’
External Layer
BGA BGA Pitch (A) 0.5mm Pitch 0.4mm Pitch 0.35mm Pitch Internal Layer
Design MVH Size (B,B’) 100㎛ [4mil] External Layer
MVH Depth(C,C’) 70㎛ [2.8mil] 100㎛ [4mil] 70㎛ [2.8mil]
PAD Size (D,D’,D’’) 275㎛ [11mil] 70㎛ [2.8mil] 50㎛ [2mil] Note
Pattern Width/Space (E/F) 75㎛ [3mil] 250㎛ [10mil] 200㎛ [8mil]
Pattern Width (G,G’/H,H’) 75㎛ [3mil]
Cu Thickness (I,I’,I’’) 30㎛ [1mil] 50㎛ [2mil] 50㎛ [2mil]
Max. DHS Aspect Ratio 25㎛ [1mil] 25㎛ [1mil]
0.8 : 1
MVH MVH Depth (C,C’) MVH Size 0.8 : 1 0.8 : 1
VIA T ≤ 110㎛ [4.3mil] 150㎛ [6mil]
FILL T ≤ 90㎛ [3.5mil] 130㎛ [5.1mil] MVH Land Size Plating
T ≤ 70㎛ [2.8mil] 100㎛ [4mil] 300㎛ [12mil] 2 Time Plating
280㎛ [11mil] 1 Time Plating
23 250㎛ [10mil] 1 Time Plating

* MVH( Micro via hole)=BVH (Blind via Hole)

MATERIAL

Item Middle-Tg(150℃) Maker Model Halogen Lead Remarks
FR-4 Free Free
M-Tg/Low Loss Nanya NPG-151 AUTOMOTIVE
Base Material High-Tg(170℃~) EMC EM-370(5)/EM-285 O O AUTOMOTIVE
Doosan DS-7402 O O
Prepreg Sangyi Autolad 1 O O
Core ISOLA IS 400, FR-185H x O
EMC EM-355(D) x O
Copper (Base) Doosan DS-8402 O O
ISOLA FR-370HR O O
TUC TU-768 X O
TU-826HF X O
O O

PP 1027 ( 35㎛), PP 1037 (42㎛) PP 1067 (55㎛) PP 1078 (65㎛)
PP 7628 (200㎛)
PP 1080 (70㎛) PP 2116 (115㎛)

0.06T 0.1T~1.6T

9um,12um,18um, 35um 2 Oz~10 Oz copper

Surface ENIG(0.05㎛~0.07㎛) ENEPIG(0.05㎛~0.07㎛) Thick ENIG( ~ 1.2㎛) HARD GOLD
Finish PB-FREE HAL
OSP IMMERSION TIN ( 1.0㎛)

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MATERIAL ( High Performance)

Material Manufacturer Part Number Dielectric Constant Dissipation Factor Tg

Rogers 4003C 3.38 (10GHz) 0.0027 (10GHz) 280℃
4350B 3.48 (10GHz) 0.0037 (10GHz) 280℃
High-Performance NELCO N4000-13 3.70 (10GHz) 0.0080 (10GHz) 210℃
N4000-13SI 3.30 (10GHz) 0.0070 (10GHz) 210℃
PANASONIC N4800-20 3.55 (10GHz) 0.0075 (10GHz) 210℃
N4800-20SI 3.24 (10GHz) 0.0064 (10GHz) 210℃
Meteowave2000 3.40 (10GHz) 0.0040 (10GHz) 215℃
MEGTRON4 3.80 (1GHz) 0.0050 (1GHz) 185℃

MEGTRON6 3.40 (10GHz) 0.0040 (10GHz) 210℃

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MATERIAL ( High speed material)

Sourced by Streamline circuit USA

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AVAILABLE WORKING SIZE

<1220mm >
<915mm,1020mm>

– Margin is min 13mm[0.510”] for tooling and test coupons
– One axis needs additional -14mm[0.550”] from usable area for impedance coupon
– Add 2.0mm[0.100”] between images when more than one board can be fit onto a panel

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WORKING PANEL & AVAILABLE AREA

Additional 14mm [0.550”] Margin in one
axis for impedance coupons.

10mm[0.4”]
Margin

Useable Board
Area

Various internal tooling and test coupons for cross-section,
registration etc.

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Made in Korea !

We will be pleased to support
your technical issues !

Contact : EDINS Co., Ltd
Mr. N.K.Chung ([email protected])
Mr. H.J.Won( [email protected])

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