MODEL CALIBRATION FOR NWFETS 435 FIGURE 9.15 Simulation results for the NWJLFET with dNW =10 nm with and without the traps. toward the positive gate voltage by some amount. Even after using the gate electrode with minimum possible work function, i.e. 3.9 eV, the transfer characteristics obtained by simulating the simplified experimental nanowire with circular cross section and nanowire diameter 10 nm would appear as shown in Fig. 9.15. The threshold voltage of the simulated transfer characteristics appears shifted by a particular value as compared to the experimental transfer characteristics. Upon careful investigation, we can notice that the NWJLFETs fabricated in [1] were reported for application as silicon-oxide-nitride-oxide-silicon (SONOS) memory. Therefore, the oxide charges or charges in the nitride layer are inevitable. Using this logical assumption, if we use a fixed charge value in the simulations, we can shift the simulated transfer characteristics to match the experimental data. However, this shift also requires a lot of hit and trial experiments with the simulator. After a large number of efforts, we found that for a fixed charge of 3.4 × 1012 cm−2 at the Si–SiO2 interface, the simulated transfer characteristics finally matched with the experimental data as shown Fig. 9.14. The statements used in Sdevice for specifying the interface charge is given below: Physics (MaterialInterface="Silicon/Oxide") {Traps((FixedCharge Conc=3.4e+12))} The simulation deck provided in Sections 9.5.2 and 9.5.3 has been used extensively to analyze the physics of the JLFETs and NWFETs and to predict the performance of different architectures proposed to mitigate the challenges faced by these emerging FET architectures in [17–25, 28, 41]. Interested readers are directed to [42] for further information.
436 SIMULATION OF JLFETS USING SENTAURUS TCAD 9.7 CONCLUSION In this chapter, we discussed the importance of the TCAD simulations. We saw how the use of TCAD simulation augments the experimental results. We found that TCAD simulations are necessary to explain the underlying physics behind the operation of any FET. They give an insight into the working of the device as they allow us to visualize the microscopic parameters such as electric field profile, potential profile, etc. which cannot be done via experiments. Then we discussed the basic tool flow of the most commonly used TCAD Sentaurus. We also provided a detailed analysis of a demo command file for both creating structure and running the device simulations for long-channel JLFETs. This code may be utilized for validating the models developed in Chapter 8 by matching them with the simulation results. We also discussed about the validity of the results given by the simulator and the importance and the need for model calibration. The procedure for model calibration of short-channel JLFETs and NWFETs was then introduced. The calibrated simulation decks provided for the NWFETs and JLFETs in this chapter may enable the new researchers in this area to explore these devices in detail and to propose new architectures to mitigate the challenges for these FETs. In the next chapter, we present a brief overview of the road ahead for JLFETs and the various emerging fields where junctionless architecture may be efficiently exploited. REFERENCES [1] S.-J. Choi, D.-I. Moon, S. Kim, J. P. Duarte, and Y.-K. Choi, “Sensitivity of threshold voltage to nanowire width variation in junctionless transistors,” IEEE Electron Device Lett., vol. 32, no. 2, pp. 125–127, Feb. 2011. [2] C.-H. Park, M.-D. Ko, K.-H. Kim, R.-H. Baek, C.-W. Sohn, C. K. Baek, S. Park, M. J. Deen, Y.-H. Jeong, and J.-S. Lee, “Electrical characteristics of 20-nm junctionless Si nanowire transistors,” Solid-State Electron., vol. 73, pp. 7–10, July 2012. [3] I. Wong, Y. Chen, S. Huang, W. Tu, Y. Chen, and C. W. Liu, “Junctionless gate-all-around PFETs using in-situ boron doped Ge channel on Si,” IEEE Trans. Nanotech., vol. 14, no. 5, pp. 878–882, Sept. 2015. [4] S. Migita, Y. Morita, T. Matsukawa, M. Masahara, and H. Ota, “Experimental demonstration of ultrashort-channel (3 nm) junctionless FETs utilizing atomically sharp V-grooves on SOI,” IEEE Trans. Nanotechnol., vol. 13, no. 2, pp. 208–215, Mar. 2014. [5] Sentaurus Device User Guide, Synopsys, Mountain View, CA, 2017. [6] ATLAS Device Simulation Software, Silvaco, Santa Clara, CA, 2017. [7] Genius, 3-D Device Simulator, Version1.9.0, Reference Manual, Cogenda Pvt. Ltd., Singapore, 2008. [8] E. M. Buturla, P. E. Cottrell, B. M. Grossman, and K. A. Salsburg, “Finite-element analysis of semiconductor devices: The FIELDAY program,” IBM J, Res. Dev., vol. 25, no. 4, pp. 218–231, July 1981.
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438 SIMULATION OF JLFETS USING SENTAURUS TCAD [26] V. Thirunavukkarasu, Y.-R. Jhan, Y.-B. Liu, and Y.-C. Wu, “Performance of inversion, accumulation, and junctionless mode n-type and p-type bulk silicon FinFETs with 3-nm gate length,” IEEE Electron Device Lett., vol. 36, no. 7, pp. 645–647, July 2015. [27] Y. R. Jhan, V. Thirunavukkarasu, C. P. Wang, and Y. C. Wu, “Performance evaluation of silicon and germanium ultrathin body (1 nm) junctionless field-effect transistor with ultrashort gate length (1 nm and 3 nm),” IEEE Electron Device Lett., vol. 36, no. 7, pp. 545–656, July 2015. [28] S. Sahay and M. J. Kumar, “Comprehensive analysis of gate-induced drain leakage in emerging FET architectures: Nanotube FETs vs. nanowire FETs,” IEEE Access, vol. 5, pp. 18918–18926, Dec. 2017. [29] Web plot digitizer [online], Available: http://arohatgi.info/WebPlotDigitizer/app3 12/, Accessed: Dec. 23, 2017. [30] A. Schenk, “Rigorous theory and simplified model of the band-to-band tunneling in silicon,” Solid-State Electron., vol. 36, no. 1, pp. 19–34, 1993. [31] J. J. Liou, “Modeling the tunnelling current in reverse-biased p/n junctions,” Solid-State Electron., vol. 33, no. 7, pp. 971–972, 1990. [32] G. A. M. Hurkx, D. B. M. Klaassen, and M. P. G. Knuvers, “A new recombination model for device simulation including tunneling,” IEEE Trans. Electron Devices, vol. 39, no. 2, pp. 331–338, 1992. [33] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 32, no. 1, pp. 83–91, 1961. [34] M. J. Kumar, R. Vishnoi, and P. Pandey, Tunnel Field-effect Transistors (TFET): Modelling and Simulation, John Wiley and Sons, Ltd, Ltd., West Sussex, UK, 2016. [35] S. Sahay and M. J. Kumar, “Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using heterodielectric BOX,” IEEE Trans. Electron Devices, vol. 62, no. 11, pp. 3882–3886, Nov. 2015. [36] L. D. Michielis, M. Iellina, P. Palestri, A. M. Ionescu, and L. Selmi, “Effect of the choice of the tunnelling path on semi-classical numerical simulations of TFET devices,” SolidState Electron., vol. 71, pp. 7–12, 2012. [37] D. Esseni, M. Pala, P. Palestri, C. Alper and T. Rollo, “A review of selected topics in physics based modeling for tunnel field-effect transistors,” Semicond. Sci. Technol., vol. 32, pp. 083005–083031, July 2017. [38] S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, “On enhanced Miller capacitance effect in interband tunnel transistors,” IEEE Electron Device Lett., vol. 30, no. 10, pp. 1102–1104, Oct. 2009. [39] J. Fan, M. Li, X. Xu, Y. Yang, H. Xuan, and R. Huang, “Insight into gate-induced drain leakage in silicon nanowire transistors,” IEEE Trans. Electron Devices, vol. 62, no. 1, pp. 213–219, Jan. 2015. [40] J. Fan, M. Li, X. Xu, and R. Huang, “New observation on gate induced drain leakage in silicon nanowire transistors with epi-free CMOS compatible technology on SOI substrate,” in Proc. IEEE SOI-3D-Subthreshold Microelectron. Technol. Unified Conf. (S3S), Oct. 2013, pp. 1–2. [41] A. K. Jain, S. Sahay, and M. J. Kumar, “Controlling L-BTBT in emerging nanotube FETs using dual-material gate,” IEEE J. Electron Dev. Soc., vol. 6, pp. 611–621, June 2018. [42] S. Sahay, “Design and analysis of emerging nanoscale junctionless FETs from gateinduced drain leakage perspective,” Ph.D. Thesis, IIT Delhi, New Delhi, India, Mar. 2018.
10 CONCLUSION AND PERSPECTIVES In the previous chapters, we discussed the promising potential of the junctionless field-effect transistors (JLFETs) and the distinct advantages that they offer over the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs). We saw how the absence of metallurgical junction not only reduces the fabrication complexity and cost but also provides flexibility while choosing the materials for the gate stack due to a lower thermal budget [1–15]. We discussed how the junctionless architecture leads to an altogether new conduction mechanism whereby the field-effect transistor (FET) operates under the flat band condition in the ON-state with a significantly reduced vertical electric field. The low electric field alleviates the reliability issues in JLFETs which is a menace for the conventional MOSFETs [16]. Also, the bulk conduction feature enables the integration of other materials like Ge, III-V, SiC, etc. in JLFETs as the performance is not severely degraded due to the interface traps and defects [16]. We also discussed how the electrostatic squeezing of carriers in the OFF-state leads to an unintentional underlap in JLFETs and helps to realize a larger effective channel length than the drawn gate length [15]. This unique feature of JLFETs not only increases their immunity to the short-channel effects as compared to the MOSFETs but also enhances their scalability. Moving further, we saw how the impact ionization induced steep subthreshold swing occurs at a lower drain voltage in JLFETs as compared to MOSFETs [17]. We also discussed the device architectures, which harness impact ionization phenomenon in JLFETs to achieve Junctionless Field-Effect Transistors: Design, Modeling, and Simulation, First Edition. Shubham Sahay and Mamidala Jagadesh Kumar. © 2019 by The Institute of Electrical and Electronics Engineers, Inc. Published 2019 by John Wiley & Sons, Inc. 439
440 CONCLUSION AND PERSPECTIVES steep subthreshold swing at subunity drain voltages. These attributes strengthen the candidature of the JLFETs to replace the MOSFETs in the future complementary metal–oxide–semiconductor (CMOS) technology for logic applications. However, the high source/drain series resistance in JLFETs reduces their ON-state current and degrades their dynamic performance [1–15]. Moreover, achieving volume depletion requires costly ultrathin SOI films. Also, the OFF-state leakage current is significantly increased in JLFETs due to the band-to-band tunneling (BTBT) induced parasitic bipolar junction transistor (BJT) action [1–15]. Therefore, we also discussed in detail the different device architectures proposed to boost the ON-state current, achieve volume depletion, and mitigate the BTBT gate-induced drain leakage (GIDL) in the previous chapters. We also discussed the specific challenges faced by each of these device architectures to evaluate their potential for commercial applications. The high sensitivity of JLFETs to random dopant fluctuations (RDF) and process variations as compared to MOSFETs limit their applications. However, the chemical doping-free electrostatic doping techniques such as charge plasma (CP) doping discussed in Chapter 7 may mitigate RDF and sensitivity to process variations in JLFETs. This may pave the way for utilization of field-induced source/drain doping in charge plasma JLFETs (CPJLFETs) for application in the mainstream CMOS technology. Moreover, we also discussed the specific challenges associated with different emerging FET architectures such as tunnel FETs (TFETs), impact ionization-MOS (I-MOS), negative capacitance FETs (NCFETs), nanowire FETs (NWFETs), nanotube FETs (NTFETs) to replace the conventional MOSFETs in Chapter 1. One of the major issues bothering all these FETs with metallurgical junctions is the stringent requirement of ultrasteep doping profile at the junctions. The chemical doping-free field-induced doping of source/drain regions on an intrinsic or lightly doped ultrathin silicon film utilizing electrostatic doping techniques such as CP may enable the realization of junctionless version of these emerging FETs [18–22]. The junctionless versions of these emerging FET architectures such as JLTFETs, JL-IMOS, discussed in Chapter 7, are not only immune to RDF but also exhibit comparable performance to their doped counterparts. Therefore, junctionless versions of the emerging FETs are also lucrative alternative to the conventional CMOS. The major challenge associated with CP doping is the metal-induced gap states (MIGS), which lead to Fermi-level pinning at the semiconductor–metal interface and degrade the performance of CP-based FETs [23]. With the advancements in the fabrication technology in future and the introduction of novel techniques such as ultrathin insulator between the metal and the semiconductor, MIGS may be mitigated and junctionless versions of the emerging FETs may become viable alternative to the MOSFETs in the mainstream CMOS technology for logic applications. So far, we have only discussed the advantages and limitations of the JLFETs for logic applications. However, we are living in an era of Internet of Things (IoT) and big data where almost all the facets of our life are connected to the Internet. A new ecosystem of connected devices including a swarm of sensors, actuators, memories,
JLFETS AS A LABEL-FREE BIOSENSOR 441 etc. under the umbrella of IoT is touching our daily lives. Low-cost and low-power sensors and memories have become inevitable to sustain this era of IoT. Junctionless architecture with lower cost, low fabrication complexity, and a better immunity to the short-channel effects may enable realization of ultralow power and low-cost FET-based biosensors and memories. In the subsequent sections, we shall see the application of JLFET for biosensing and memory applications. 10.1 JLFETS AS A LABEL-FREE BIOSENSOR MOSFET-based biosensors are gaining popularity owing to their low cost and the ability to detect unlabeled biomolecules when functionalized with appropriate receptors [24–39]. In this approach, the gate oxide is etched forming a nanocavity as shown in Fig. 10.1 and the target biomolecules are allowed to flow in the cavity. The silicon surface is functionalized with appropriate receptors, which bind the target biomolecules once they contact the receptors. The change in the FET characteristics in the presence and absence of the biomolecules allows for their detection. The target biomolecules are characterized by their equivalent electrical property such as dielectric constant or charge. However, the MOSFET-based biosensors offer poor selectivity and the signal-tonoise ratio is very low due to the intrinsic variations. To overcome these limitations, other variants of FETs such as TFETs and I-MOS have been utilized for biosensing applications [32–35]. The steep subthreshold swing offered by these emerging FETs enhances the sensing margin. However, these FETs especially I-MOS have a p–i–n asymmetric structure and is not scalable. The size of the proteins lies in the sub-10 nm range, and the most commonly used proteins such as biotin or streptavidin are ∼3–5 nm in size. Therefore, for efficient detection, the nanogaps should be designed in the range of ∼10 nm so that they allow the biomolecules to flow while exhibiting enhanced sensitivity. Therefore, the FETs used as biosensors should also be scalable Cavity Cavity Channel N+ Drain N+ Source N+ VGf VGb VD VS FIGURE 10.1 Three-dimensional (3D) view of the DGJLFET with nanocavities for biosensing application.
442 CONCLUSION AND PERSPECTIVES –1.4 –1.2 –1.0 k = 1 k = 3.57 –0.8 –0.6 –0.4 Gate voltage, VGS (V) Drain current, ID (A/μm) 10–11 10–9 10–7 10–5 FIGURE 10.2 Transfer characteristics of the DGJLFET biosensor in the presence of different biomolecules [39]. to the sub-100 nm range to offer increased packing density along with enhanced sensitivity. The JLFETs can offer a low-cost, scalable, and highly sensitive biosensor when operating in the impact ionization dominant regime exhibiting steep subthreshold slopes like I-MOS as discussed in Chapter 6. The performance of the JLFET-based biosensor in the impact ionization regime is shown in Fig. 10.2. The efficacy of the JLFET-based biosensor has been tested on three target biomolecules: biotin, streptavidin, and (3-aminopropyl)triethoxysilane (APTES) modeled with a dielectric constant of 2.63, 2.1, and 3.57, respectively [39]. The shift in the threshold voltage in the presence and absence of biomolecules is taken as the sensing margin. The presence of the biomolecule increases the effective gate capacitance leading to a larger electric field coupling. This suppresses the lateral electric field reducing the impact ionization rate. Therefore, a larger gate voltage has to be supplied to attain the steep switching behavior. In addition to the dielectric constant, the biomolecules also exhibit an inherent charge depending on their isoelectronic point (pI), pH of the solution, and the concentration of the solution. If the pH of the solution is more than the isoelectric point, the biomolecules gain a negative charge while if the pH is less than the pI, the biomolecules become positively charged. The magnitude of the charge also depends upon the difference in the magnitude of pH and pI. Although the charge density of biomolecules in the different solutions has not been characterized well, the observed charge densities in the presence of biomolecules are in the range of – 1011 to –1012 cm–2. The presence of an additional negative charge helps in depleting the underneath silicon film, forcing the transfer characteristics to further shift toward more positive gate voltages as shown in Fig. 10.3. The steep switching behavior can be obtained at lower drain voltages with asymmetric operation as observed in Section 6.7. Therefore, the asymmetric operation, which enhances the impact ionization-induced bipolar effects, may be utilized to further enhance the sensitivity of the JLFET-based biosensor in the impact ionization dominant regime.
JLFETS AS CAPACITORLESS DRAM 443 Biomolecule charge (C-cm–2) 1010 2.0 2.5 3.0 Δ VTh (V) 3.5 4.0 APTES, k = 3.57 Biotin, k = 2.63 Streptavidin, k = 2.1 1011 1012 FIGURE 10.3 The shift in the threshold voltage (ΔVTh) for different biomolecules with different charge [39]. 10.2 JLFETS AS CAPACITORLESS DRAM The snapback property in the output characteristics of JLFETs may be utilized for capacitorless dynamic random access memory (DRAM) application [40–53]. The DRAM, a memory element, as you may know consists of an array of capacitors in a 1T-1C (1 transistor, 1 capacitor) configuration. The information is stored in the form of charge in the capacitor. However, the capacitor needs to be refreshed continuously, which consumes a lot of power, and scaling the capacitor is also a technological challenge. Therefore, the field of capacitorless DRAM where the silicon body in the MOSFET itself stores the charge carriers has attracted the attention of the researchers. However, the snapback characteristics are obtained at a large drain voltage>8 V in a SOI MOSFET [40–53] and the read current margin (i.e., difference between read currents in state “0” and “1”) is also low. Therefore, the quest for capacitorless DRAM devices operating at low supply voltages is underway. In JLFET-based capacitorless DRAM, the charges would be stored in the highly doped silicon channel region. The snapback window allows to distinguish between the states “0” or “1” during read cycle once the JLFET has been written (programmed) to state “0” or “1” by applying an appropriate drain voltage. For instance, we may select a drain voltage, VDS =1.75 V for writing state “0” and a VDS =2.25 V for writing state “1” and chose a drain voltage of 2.1 V for reading the state of the JLFET according to the output characteristics of the JLFET shown in Fig. 10.4. For this case, the read current obtained after programming the memory cell (JLFET) in state “1” is three orders of magnitude more than that obtained after programming the memory cell in state “0.” The two states may be easily distinguished without the need of an ultrasensitive sense amplifier. Therefore, the JLFETs offer a large memory window, i.e. snapback window along with a large read margin at a low drain voltage and may be a lucrative alternative to the MOSFETs for low static power capacitorless DRAM.
444 CONCLUSION AND PERSPECTIVES Drain voltage, VDS (V) Drain current, ID (A) 10–9 10–8 10–7 10–6 10–4 10–5 1.5 2.0 2.5 Read “0” Read “1” Write “0” Write “1” ΔI ΔV FIGURE 10.4 The hysteresis in the output characteristics of the DGJLFET obtained during voltage-controlled measurements and the different programming voltages for the application of DGJLFETs as capacitorless DRAM [40]. 10.3 NANOWIRE JUNCTIONLESS NAND FLASH MEMORY The introduction of flash memory changed the storage landscape. We can find flash memory in the external storage card of every smartphone owing to the high storage density, low program/erase time, and high endurance and retention. The flash memory exploits the floating gate MOSFETs to store data. The floating gate MOSFET has two gates as shown in Fig. 10.5(a): a floating gate (FG), which is not connected to any external bias and stores charge (in the form of trapped electrons), and a control gate (CG), which controls the charge transfer between the MOSFET channel and the floating gate. Generally, the floating gate is made of polysilicon. In the program mode, a large bias is applied to CG. A portion of the voltage applied to CG couples to the FG through capacitive coupling. FG acts as the gate of the underlying MOSFET and depending on the capacitively coupled voltage, electrons are injected from the channel region of the MOSFET to FG via Fowler–Nordheim (FN) tunneling or channel hot electron injection. Since the FG is surrounded by insulators, the electrons are trapped on FG. The stored negative charge on FG increases the threshold voltage of the underlying MOSFET and the flash memory is said to store bit “1.” The application of a CG voltage of opposite polarity enables the stored electrons to tunnel back into the MOSFET channel region restoring the original threshold voltage. This is erase operation, and the flash memory is said to store bit “0.” During the read operation, a small voltage is applied to the gate and the threshold voltage shift is evaluated by measurement of the drain current. On the other hand, the voltages required for program/erase operation is very high (in excess of ∼12 V), which requires an additional supply or a charge pump circuitry increasing area overhead and routing complexity. Also, to increase the storage density, the floating gate MOSFETs must be scaled. However, the CG–FG coupling ratio degrades significantly with scaling of the floating gate MOSFETs [54]. Therefore, flash memory architectures with a different charge trap layer such as nitride layer, high- dielectric, or silicon nanocrystals were explored [55–62].
NANOWIRE JUNCTIONLESS NAND FLASH MEMORY 445 Channel P– (a) (b) (c) VCG VG SiO2 SiO2 Si3N4 SiO2 SiO2 Si3N4 SiO2 SiO2 Si3N4 VD VS VS VD Drain N++ CG FG Source N++ Channel P– Drain N++ Word line (WL,2) Bit line (BL) Word line (WL,1) Common source line (CSL) Source N++ N+ N+ N+ N+ FIGURE 10.5 Three-dimensional view of (a) floating gate MOSFET, (b) conventional SONOS memory cell, and (c) NAND flash memory based on JLFETs. The flash memory utilizing the silicon nitride layer for charge trapping is known as silicon-oxide-nitride-oxide-silicon SONOS as the gate stack consists of a silicon nitride sandwiched between an ultrathin SiO2 tunneling layer and a relatively thick SiO2 blocking layer as shown in Fig. 10.5(b). In the program mode, the application of a voltage on the gate results in a large electric field leading to tunneling of electrons (FN tunneling or direct tunneling depending on tunnel layer thickness) through ultrathin SiO2 layer into the charge trapping nitride layer. The storage of charge on the nitride layer increases the threshold voltage of the SONOS memory and stores bit “1.” Similarly, the application of a gate voltage of opposite polarity leads to tunneling of holes from the channel region to the nitride layer and bit “0” is stored in the SONOS memory cell. The SONOS memory cell offers a better scalability as compared to the floating gate MOSFETs [55–61]. However, the short-channel effects
446 CONCLUSION AND PERSPECTIVES hinder the scaling of SONOS memory cell. The multi-layered gate stack consisting of O-N-O restricts the scaling of effective oxide thickness (EOT) since the charge stored depends on the thickness of the nitride layer. The blocking layer also cannot be scaled as it blocks the tunneling of the charges from the nitride layer to the gate electrode. A higher EOT reduces the immunity of the SONOS memory cell against the short-channel effects. The use of ultrasteep doping profiles may reduce the short-channel effects. Also, holes tunnel from the channel region to the nitride layer during the erase operation. If somehow the holes are increased in the channel region before the erase operation, the efficiency of the erase operation would increase and the distribution of the threshold voltage after erase would be narrowed [63]. As discussed in Chapter 5, GIDL leads to an accumulation of holes in the channel region [1–13]. Therefore, if somehow GIDL is triggered before the erase operation, an efficient erase operation would be ensured. An ultrasteep doping profile is required even from a higher GIDL perspective. You may wonder that a phenomenon that degrades the performance of devices for logic operation is beneficial for memory application. To increase the flash storage density, the SONOS memory cells may be stacked vertically via three-dimensional (3D) integration [64–71]. However, realizing ultrasteep doping profiles for reducing short-channel effects and achieving efficient erasure of memory cell is extremely difficult in 3D multistacking integration owing to the complex thermal budget. Therefore, 3D NAND flash memories with a junction-free polysilicon channel and virtual source/drain regions (created via fringing gate fields) were introduced [72, 73]. The lower mobility of polysilicon and the high series resistance of the virtual source/drain regions lead to a very low read current. The read current may hit the noise floor, and erroneous data may also be interpreted leading to failure of read operation. The JLFETs with a uniformly doped silicon film may circumvent all the above challenges owing to their low thermal budget, ease in fabrication, reduced short-channel effects, and reduction in surface scattering due to bulk conduction. Moreover, the GIDL in JLFETs which is detrimental for logic application may enable efficient erasure and aid its memory applications. Therefore, SONOS NAND flash memory based on JLFETs (Fig. 10.5(c)) was proposed and experimentally realized [63, 71, 74–76]. The cross-sectional TEM image of the fabricated NWJLFETs with SONOS stack is also shown in Fig. 3.10(g). The JLFETs based 3D NAND flash memory exhibits a high read current, a large programming window, i.e. the difference in the threshold voltage between the program and erase operations, a narrow distribution of threshold voltage after erase operation and an improved endurance (number of program/erase cycles which the device can sustain without failure). Therefore, the JLFETs-based flash memory overcomes all the challenges faced by the 3D flash memory. So far, we have discussed the potential of JLFETs for application as biosensors and memory devices owing to their low cost. Since the JLFETs do not have any metallurgical junctions, there are no stringent constraints on realizing ultrasteep doping profiles. As a result, JLFETs do not require rapid annealing processes and complex
JUNCTIONLESS POLYSILICON TFTS WITH A HYBRID CHANNEL 447 thermal budgets. The lower thermal budget for JLFETs and junctionless versions of emerging FETs facilitates their realization on single-crystal silicon-on-glass substrates. This may lead to a new domain of exciting possibilities whereby these devices could be employed in display devices and for biocompatible and optoelectronic applications. Therefore, polysilicon junctionless thin film transistors (TFTs) have been experimentally demonstrated [78, 79]. However, the large source/drain series resistance in JLTFTs result in a very low ON-state current. To reduce the source/drain series resistance and improve the performance of JLTFTs, a hybrid channel JLTFT was proposed [79, 80]. We discuss the JLTFTs with a hybrid channel in the next section. 10.4 JUNCTIONLESS POLYSILICON TFTS WITH A HYBRID CHANNEL The structure of the junctionless polysilicon TFT with a hybrid channel is shown in Figs. 10.6(a) and 6(b). The structure is similar to the HSJLFET discussed in Section 5.8.1 and consists of a n+ substrate below the p+ active polysilicon channel region. Although there is a vertical p–n junction, the JLTFT with a hybrid channel is still junctionless in the direction of current flow, i.e. in the lateral direction. The vertical p–n junction induced depletion helps to realize a smaller effective polysilicon p+-channel thickness as compared to the actual physical thickness. This helps to realize efficient volume depletion even when the p+-polysilicon film thickness is large. A large p+- polysilicon film thickness also reduces the source/drain series resistance increasing the ON-state current of the JLTFT with the hybrid channel. The JLTFT with a hybrid channel offers a better immunity to the short-channel effects due to the enhanced gate control owing to a lower effective channel thickness. The low OFF-state leakage current and the improved subthreshold swing of the JLTFT with a hybrid channel are attributed to these factors. Moreover, the threshold voltage may be tuned by changing the doping of the underlying n+-substrate allowing multithreshold voltage circuit design. JLTFTs with multiple hybrid channels (p+-channel-n+ channel) stacked on top of each other as shown in Figs. 10.6(c) and 6(d) have also been proposed and experimentally demonstrated [80]. The bottom p+ channel in the JLTFT with a stacked hybrid channel is sandwiched between the top and bottom n+-substrates. As a result, it is depleted from both top and bottom leading to an effective channel thickness, which is significantly small as compared to the actual physical thickness. Therefore, the gate controllability is further improved in the JLTFT with the stacked hybrid channel, resulting in a significantly reduced OFF-state current as shown in Fig. 10.7. Moreover, the ON-state current is also larger in the JLTFT with a stacked hybrid channel owing to the reduced source/drain series resistance and increased number of channels for current flow. Also, the JLTFT with the stacked hybrid channel exhibits better immunity to the negative bias instability and a reduced low-frequency noise [80].
448 CONCLUSION AND PERSPECTIVES Buried Oxide Si substrate N+ P+ Source Drain Gate Gate Gate S/D P+ P+ P P + + D D D S S S P+ N+ N+ N+ N+ N+ Gate P-type ch N-type sub BOX Substrate BOX (a) (b) (c) (d) FIGURE 10.6 (a) Three-dimensional view and (b) cross-sectional view of a JLTFT with a hybrid channel [79] and (c) 3D view and (d) cross-sectional view of the JLTFT with vertically stacked hybrid channels [80]. –4.0 JLTFT Hybrid TFT Stacked hybrid TFT –5.0 –3.0 –2.0 0.0 1.0 –1.0 2.0 Gate voltage, VGS (V) 10–15 10–13 10–11 10–9 10–7 10–5 Drain current, (A/μm) VDS = –0.4 V FIGURE 10.7 Transfer characteristics of the JLTFT, JLTFT with a hybrid channel, and the JLTFT with a stacked hybrid channel [80].
JLFETS FOR 3D INTEGRATED CIRCUITS 449 10.5 JLFETS FOR 3D INTEGRATED CIRCUITS As discussed in Chapter 1, gate length scaling of the conventional MOSFETs is limited due to the short-channel effects, GIDL, direct source-to-drain-tunneling, and inability to realize ultrasteep doping profile. Therefore, to sustain the Moore’s law, researchers have started exploring the vertical dimension and stacking devices on top of each other to increase the area efficiency without scaling the lateral dimensions such as gate length. Vertical stacking of the front end of line FETs on top of the back end of line (BEOL) interconnects is an integral part of these sequential 3D integrated circuits. This has triggered the research and development in the field of thru-silicon via and other 3D integration techniques. In addition, it has also led to a quest for BEOL compatible transistors. The BEOL consists of a dense network of copper interconnects with low- dielectric. Therefore, the BEOL transistors must be processed at a lower temperature (<430°C) without affecting the thermal stability of the copper interconnects with low- dielectric. Moreover, the BEOL compatible transistors should exhibit high performance and high scalability. In view of these requirements, the JLFETs owing to their low thermal budget could be a lucrative alternative for “cold” processed BEOL compatible transistors. Recently, BEOL-compatible JLFETs for 3D sequential integration have been experimentally demonstrated in [81, 82]. Double-gate JLFETs may be fabricated on top of a processed wafer at temperature below 430°C using the process flow demonstrated in [81] and shown in Fig. 10.8. First, the silicon-on-insulator (SOI) wafer containing the active silicon film is ion implanted and annealed at high temperature to achieve the required uniform doping for realizing JLFETs. A gate stack may then be deposited over the doped crystalline SOI layer. This gate stack would act as the back gate once this wafer is transferred on to the processed wafer containing the BEOL interconnects. A low-temperature direct wafer–wafer dielectric bonding process (using oxide–oxide or SiCN–SiCN) may then be used to transfer the SOI wafer with active JLFET to the processed wafer. The substrate and BOX of the donor SOI wafer are then etched. Once the wafer has been transferred, high-temperature processes are not permissible due to the thermal instability of BEOL at temperatures above ∼450°C. Therefore, a gate first approach is used and HfO2 gate dielectric is deposited using atomic layer deposition at 300°C followed by deposition of TiN metal gate using chemical vapor deposition at 430°C. The replacement metal gate process commonly used in fabricating Fin field-effect transistors requires a temperature greater than 500°C and cannot be used for this process [81]. Furthermore, the selective epitaxial growth of source/drain regions to obtain a lower source/drain series resistance also requires a temperature more than 500°C. Therefore, direct tungsten (W) contacts are taken at the source and drain regions using a Ti/TiN barrier layer. As a result, the source/drain series resistance dominates and the ON-state current is low [81]. The stacked hybrid-channel nanowire junctionless polysilicon TFTs discussed in Section 10.4 may also be used for monolithic sequential 3D integrated circuits.
450 CONCLUSION AND PERSPECTIVES Carrier wafer PECVD oxide PECVD oxide Bottom gate electrode (TiN) Bottom gate dielectric (HFO2) Top Si implantation & anneal Top Si layer thinning SOI donor wafer Anneal & CMP Anneal & CMP Bonding & anneal Edge trimming Si substrate grinding Si dry etch (stop on BOX) Dry + wet BOX removal Si mesa etch Gate stack (HfO2/TiN/W) & patterning ILD0 fill and CMP Local interconnect etch Direct contacting to S/D (Ti/TiN/W) Contact Cu BEOL Anneal & CMP Anneal & CMP SICN BEOL 50nm SiCN FIGURE 10.8 Fabrication flow for realizing BEOL-compatible DGJLFET on an already processed carrier wafer [81]. 10.6 SUMMARY In this chapter, we discussed the novel attributes of JLFETs and examined the competitive advantages of JLFETs over the conventional MOSFETs. It is quite possible that JLFETs or the junctionless version of the emerging FETs such as JLTFETs may be employed in the mainstream CMOS technology in future. In addition, the junctionless architecture, owing to its low cost, low fabrication complexity, and lower thermal budget may open up a new domain of exciting possibilities whereby these devices could be employed as sensors, memories, such as capacitor-less DRAM, NAND flash memory, display devices, and for biocompatible, optoelectronic, and 3D sequential integrated circuit applications apart from logic applications. The enormous possibilities offered by the junctionless architecture offers exciting opportunities to the
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INDEX <211> silicon, 19 1D slice, 419 2D density of states, 373 2D electron gas (2DEG), 102, 373 2D material, 47–48, 57, 63 2D Poisson equation, 333, 365–366 2D simulation, 401, 422 300-mm wafer, 199 3D density of state, 373 3D multistacking integration, 446 3D NAND flash memories, 446 3D sequential integration, 449–450 3-nm technology node, 49 5-nm technology node, 49 abrupt doping profile, 31, 423 abrupt interface, 212 abrupt junction, 203, 226, 229, 291 abrupt p+–n+ vertical junction, 199 abrupt potential step, 159, 213, 218 acceptor ions, 5 acceptor traps, 135, 208 accumulated holes, 175 accumulation, 4–6, 71, 78, 80, 83–85, 87, 94–95, 97, 105, 113, 116–117, 126–128, 136, 153, 155, 162–164, 166–167, 169, 176, 188, 191–192, 194–197, 201–202, 205, 208, 222, 236, 253, 257–259, 264, 274, 296, 300, 312, 335–336, 344, 348, 352–354, 361–363, 382, 384, 402, 438, 446 accumulation layer, 78, 84, 87, 335 accumulation mode, 5, 78, 80, 84–85, 95, 97, 113, 126–128, 163, 166, 264, 300, 335, 352–353, 361–362, 382, 384, 402 acoustic phonon scattering, 92 activation energy, 88 active device layer, 19, 47, 133, 136–140, 144–145, 199, 202, 208, 220, 236 active layer thickness, 133, 139, 208–210, 225 active shell thickness, 222, 224–225 actual physical thickness, 449 acute-angled triangles, 389, 397 additional source/drain implantation, 82, 126 adequate mesh, 395 Junctionless Field-Effect Transistors: Design, Modeling, and Simulation, First Edition. Shubham Sahay and Mamidala Jagadesh Kumar. © 2019 by The Institute of Electrical and Electronics Engineers, Inc. Published 2019 by John Wiley & Sons, Inc. 457
458 INDEX air spacer, 154–155, 239 AlGaN/GaN, 102, 122 alignment, 18, 86, 206, 212, 237 alignment challenges, 206, 212 aluminum, 44, 46, 68, 285, 454 aluminum- and zirconium-doped hafnium oxide, 46 ambipolar conduction, 33–34, 309 analog applications, 39, 218 analog circuits, 41 analog performance, 136, 158, 172, 321, 455 analytical model, 24, 58, 72, 76, 114, 165, 168, 250, 328, 344, 381, 383 analytical modeling, 327–329, 333, 379, 381, 387, 451 anisotropic constants, 43 annealing, 22–23, 26, 28, 31, 67–68, 80, 82, 111, 148, 164–165, 199, 203, 220, 226, 229, 252, 281, 287, 291–292, 310, 319, 447 anode current, 286–287 anode voltage, 286 anomalous behavior, 93, 195–196 approximations, 8, 328–329, 335, 340, 354, 387, 407, 423 APTES, 442 area advantage, 55 area efficiency, 50, 449 area overhead, 131–132, 444 area-driven perspective, 4 areal electron density, 358 assumptions, 329, 387, 409–410 asymmetric, 38–39, 41, 113, 154, 166–167, 171, 269–270, 276, 382, 384, 441, 442, 454 asymptote, 352 atomic layer, 48, 64, 81, 210, 449 atomic layer deposition, 64, 81, 210, 449 atomically thin layers, 48 atomistic modeling, 328–329 Auger generation, 34, 60 Auger recombination, 402, 417, 432 avalanche breakdown, 34, 277 avalanche multiplication, 35–37, 40 avalanche multiplication factor, 40 azimuth direction, 333 back gate, 33, 120, 230–234, 237, 268–271, 449 back gate engineering, 33 back gate underlap, 233–234 backscattering, 54, 89 background doping, 285, 306, 308 ballistic transport, 54, 89, 118, 329 band alignment, 17–18, 33, 110, 180, 192 band bending, 18, 28–29, 32–33, 57, 182, 189–190, 214–245, 310, 359 band gap, 17, 30–33, 36, 38, 48, 80, 93, 99, 101–102, 104, 106, 116, 182, 186, 198–199, 235, 261, 267, 284–285, 303, 318, 372, 377, 390, 402, 432 band gap narrowing, 80, 99, 116, 267, 390, 402, 432 band offset, 245, 259 band pass filtering, 31 band structure, 87, 198, 390, 402 band structure lab tool, 198 barrier height, 7, 14–15, 17, 20, 22, 30, 54, 89–90, 98, 101–102, 128, 147, 155, 173, 175–177, 181–182, 187, 189, 192–196, 199–202, 205–207, 210, 215–216, 218, 222, 232, 235, 239–240, 242, 257, 266, 269, 274, 296, 303, 306, 309–310, 313, 316 barrier lowering, 192, 372 barrier thinning, 310 barrier width, 17, 19, 59, 246–247, 303–304, 316 base, 39–40, 61, 110, 128, 175–178, 189, 192–193, 195, 197–198, 199, 201–203, 226, 235–236, 239, 247, 258, 296, 321, 389, 406 base current, 40, 176, 192, 258, 296 base width, 128, 177–178, 189, 193, 195, 197–199, 203, 226, 235–236, 239, 247, 406 basic nonlocal BTBT model, 419 BEOL (back end of line), 449–451, 456 BEOL transistors, 451 bias-temperature instability (BTI), 94, 248, 440 big data, 13, 440 binomial theorem, 340 biocompatible, 288, 447, 450
INDEX 459 biosensors, 165, 255, 279, 441, 446, 452–453 biotin, 441–442 bipolar action, 40, 273–275, 322 bipolar effects, 263, 266, 273–274 bipolar enhanced JLTFET, 294 bipolar gain, 276, 278, 296 bipolar IMOS, 39 bipolar operation regime, 263 bipolar signature, 274 BJT (bipolar junction transistor), 2, 25, 39–40, 61, 65, 110, 123, 128, 162, 170, 175–179, 181–182, 185, 189, 192–203, 205–206, 208–211, 214–215, 222, 225–227, 231–232, 235–236, 239–240, 245, 247–248, 250, 254–255, 258–259, 264, 276–277, 282, 296, 321–322, 340, 380, 389, 406, 409, 437, 440, 451 black box, 328 block-decomposition method, 403 blocking layer, 445–446 body contact, 40, 206, 426 body factor, 45–46 body terminal, 6 Bohr’s theory, 17 Boltzmann limit, 3, 11, 23 Boltzmann statistics, 333 Boltzmann transport equation, 328 Boltzmann tyranny, 3, 21–23, 42, 44, 317 Boolean operators, 394 boron doping, 103, 395 bottom-up techniques, 49 boundary condition, 75, 329, 333–337, 340–342, 345–350, 358, 366–367, 369–371, 374, 379, 387–388, 390, 401, 404, 431 BOX (buried oxide), 1, 33–34, 60, 115, 131–135, 137–138, 164, 204–208, 231, 252–253, 277, 296, 323, 380, 411, 438, 449–451 BPJLFET (bulk planar JLFET), 137–140, 143, 152, 208–210 breakdown voltage, 24, 34, 37–39, 41, 102, 248, 258, 289 BTBT (band-to-band tunneling), 17–19, 25, 27–28, 34–36, 44, 50–52, 55–57, 64–66, 101, 110, 115, 123, 125, 128, 139, 149, 151–152, 162, 170, 172–182, 184–192, 195–203, 205–206, 208–211, 214–215, 217, 220, 222, 224–225, 227, 231–232, 239, 242–243, 245–246, 248–250, 254–255, 258, 277, 291, 294, 296, 308–310, 317, 322–323, 379–380, 389, 406–407, 409, 413, 417–423, 432, 437, 438, 440, 451–452 BTBT model, 162, 176–177, 181, 185, 187, 409, 417, 419, 420–422 BTBT-generated holes, 174, 201–202 BTBT-induced parasitic BJT, 110, 128, 162, 177–179, 189, 192, 197–199, 203, 208, 211, 214, 225, 227, 231, 245, 409 buffer layer, 102, 122, 206–208 built-in potential, 371 bulk, 5–6, 18, 20, 36–38, 48, 50, 65, 76, 79–80, 83–85, 87–88, 91, 95–97, 99–100, 112, 117–118, 120, 137, 144, 146, 152–153, 162, 166–167, 169, 205, 208, 253, 261–262, 277, 329, 356, 382, 389, 396, 438–439, 446, 455–456 bulk conduction, 83, 95, 97, 100, 439, 446 bullet, 54, 89 calibrated simulation decks, 436 calibrated simulation setup, 422, 434 calibration, 386, 420 Canali mobility model, 417, 432 capacitance matching, 46 capacitance mismatch effect, 45 capacitance–voltage (C–V) relationships, 385 capacitive coupling, 444 capacitive load, 41 capacitorless dynamic random access memory, 255, 279, 443, 453 capture cross section, 135, 208 carbon allotrope, 46 carrier ballisticity, 54, 82, 89, 118, 125, 385 carrier concentration fluctuation, 95–96 carrier heating, 38, 40 carrier lifetimes, 402, 405, 432 carrier scattering, 48, 402, 432 carrier transport efficiency, 157, 159 carrier–carrier scattering, 390
460 INDEX catalyst seed, 51 center of the nanowire, 50, 184, 187, 227 central potential, 335, 337, 339, 343–344, 350, 352–353, 354, 366–369 channel charge, 14, 97, 136, 351 channel doping, 72, 76, 92, 104, 109, 213, 306, 308, 329, 360, 370, 374, 377, 423, 425 channel length, 7, 12–15, 18–19, 47–48, 54, 59, 67, 88–89, 97–98, 101, 105–107, 128, 143, 155, 165, 177, 179, 192, 206–207, 226, 229, 235, 271–272, 300, 329, 331, 340, 348, 370–373, 406, 410 channel thickness, 47, 54, 71, 83, 96, 101, 106, 108–109, 152–153, 175, 179, 224, 235–236, 266, 270, 331, 340, 344, 348–349, 365, 367, 371–377, 447 charge carrier profiles, 50, 53 charge density, 20–21, 42, 73, 329, 331–332, 336, 338, 343, 345, 347, 351–356, 359–360, 366, 374, 379, 407, 442 charge dynamics, 5, 14 charge plasma based p–n diode, 283 charge plasma concept, 287, 290–291, 294, 298, 304, 319 charge plasma doping, 282, 287–288, 293, 319 charge plasma of electrons, 284 charge plasma of holes, 284 charge pump, 130–132, 444 charge sharing, 97 charge trapping, 51, 445 charge-based model, 113, 166, 351, 353–355, 361, 363 charge-based modeling approach, 319, 351 chemical doping, 281–282, 287, 290–292, 298, 302, 304, 312–313, 317, 319, 327, 440 chemical vapor deposition (CVD), 48, 449 chip, 2–4, 12–13, 64, 130 circuit designers, 42, 131, 328 circuit layout, 31 circuit simulations, 60, 165, 321, 328 circuit-level analysis, 328 classical electron density, 184, 377 classical generation–recombination process, 418 classical mechanics, 184 classical physics, 328 classical transfer characteristics, 379 closed form analytical solution, 335, 345, 370 closed switch, 6 CMOS (complementary MOS), 10–13, 17, 23, 28, 31, 33, 44, 46, 58, 64–65, 90, 100, 103–104, 113–114, 116–117, 121, 126, 136–137, 152, 163, 167, 169, 170, 172, 234, 248, 250, 253, 277–278, 285, 314–315, 317, 325, 438, 440, 450 CMOS incompatible, 46 CNFETs (carbon nanotube FETs), 195–196 CNFETs with a Schottky source, 195 CNormPrint, 400, 403, 415 coarse mesh, 389 cobalt, 284 coercive field, 43, 62 Cogenda visual TCAD, 386 coherent relaxation, 100 collected charge, 276 collector, 40, 110, 175, 192, 258, 296, 321 collector current, 40, 258 compact analytical models, 328 compact modeling, 328, 379, 381, 387, 418 compact models, 328 complex thermal budgets, 82, 447 complimentary dopants, 67 compressive strain, 88 computationally efficient, 328, 348, 351 conduction band, 17–20, 28–29, 32–35, 50, 56, 101, 109, 151, 173, 180, 182–184, 192, 198, 205, 235, 292, 306–309, 373–375, 377, 406, 417, 419 conduction channel, 270 conduction mechanism, 34, 69, 82–83, 87, 89, 94, 97, 106, 111, 248, 260, 439 conformal mapping, 379 constant current method, 8, 145 constant electric field, 12 constant electric field scaling rule, 12 contact length, 312, 397, 413 contact pads, 81 contact placement, 396–397 contact resistance, 48, 101, 306, 309 contact sharing, 31, 38, 41
INDEX 461 contacting strategy, 306 contaminate, 44, 46 continuity equation, 328, 420 control gate, 157, 160–161, 214–217, 313–316, 318–319, 444 conventional carbon nanotube, 195 convergence, 340, 389, 395, 403–404, 409, 413, 432 copper interconnects, 449 copper sulfide, 68 core diameter, 55, 57, 221, 224–225, 241–242 core doping, 222, 224–226 core gate, 52–54, 56–57, 237–240, 242–243 core gate dielectric, 57, 243 core–shell interface, 220, 229 core–shell nanowire, 101, 220 core–shell NWJLFET, 220 cost of manufacturing perspective, 82 Coulomb blockade mechanism, 93 Coulomb scattering, 84, 93, 95 coupling ratio, 444 CP (charge plasma) diode, 286–288 CP doping, 440 CPFETs (charge plasma FETs), 309 CPJLFET, 298–305, 307, 309, 310–312, 440 critical electric field, 36 critical voltage, 36 cross-talk, 315, 319 cryogenic temperatures, 93 crystal lattice, 32 crystal orientation, 19 current-carrying capacity, 55 current continuity equations, 386–387, 405 current-controlled measurements, 275 current driving capability, 50, 52, 56–57, 146–147, 155, 157, 186, 299, 304 current gain, 40, 128, 176, 189, 192–193, 195, 198–199, 202, 258 curve fitting, 328 cutoff frequency, 158, 219 cylindrical coordinates, 333 damage mitigation, 291 damped Newton iterations, 404 damping method, 404 dangling bond, 48 Debye length, 282–283, 285, 301, 308, 371 decay rate, 276 deep depletion approximation, 338 default parameters, 386 defect centers, 22 defect-free interface, 48, 206 defects, 17, 44, 63, 83–84, 97, 100–101, 103, 125, 206, 248, 287, 439 degeneracy, 373, 377 Del Alamo model, 390 delaunization, 397 delaunizer, 389, 397, 413 delay perspective, 140, 153, 171 Dennard’s scaling rule, 12 dense mesh, 389, 396 density gradient model, 199 density of states (DOS), 19–20, 34, 48, 50, 53, 102, 184, 373, 377, 390, 402, 420–421 depletion, 4–6, 13–15, 17–18, 21, 24–25, 29, 35, 37–38, 60, 64–65, 70–77, 80, 83–84, 91–92, 94, 96–98, 101, 103, 105–106, 108–109, 112, 115, 125, 127–128, 130–133, 136–137, 139–144, 146, 149, 153, 155, 160, 162–163, 169–170, 172–173, 177, 184–188, 192, 199–200, 204–206, 208, 210, 222, 224, 227, 232, 237, 239, 249, 256, 260, 262, 264, 270, 277, 282, 285, 288, 297–298, 301, 308, 321–323, 329, 331–333, 335–339, 343–345, 348, 350, 351, 353–355, 357–358, 360–362, 364, 370, 374, 379–380, 382, 389, 402, 437, 440, 447, 451 depletion approximation, 73, 331, 336, 338, 350, 356, 358 depletion capacitance, 21, 92, 136, 357 depletion charge, 73, 74, 285, 301, 308, 332, 343, 345, 351, 353–354, 360, 374 depletion mode I-MOS, 37 depletion region, 5–6, 13–15, 17–18, 29, 35, 70, 72, 75, 77, 92, 96–98, 103, 128, 136, 139, 142–143, 146, 153, 177, 204, 282, 331, 336–337, 356–357, 362 depletion region width, 5, 13–14, 17–18, 29, 35, 75, 77, 92, 136, 146, 153, 204, 331, 336, 356–357
462 INDEX design constraints, 76 design space, 327–328 DGFETs (double gate FETs), 50, 53, 104 DGJLFET, 71, 73–74, 76–79, 83, 85, 129, 149, 150–152, 230–237, 265, 268, 269–276, 333–336, 338–340, 343, 345, 347–352, 354–357, 359–360, 363, 365, 367–368, 371–373, 375–377, 391, 441–442, 444, 450 dielectric constant, 46, 100, 102, 106, 153, 156–157, 170, 240–241, 254, 441–442 differential amplifiers, 104 differential channel resistance, 356 diffusion, 7, 14, 17–18, 23, 29, 31, 63, 67–68, 102, 195, 212, 259, 262, 281, 286–287, 291, 356, 358, 360, 371, 379, 382 diffusion current, 102, 358, 382 digital circuit, 9, 11, 33, 38–39, 41, 46, 126, 136, 172, 327 dipole moment, 42 direct band gap, 32 direct tunneling, 178, 409 discovery of transistor, 2 discretization of energy bands, 198, 372 discretization step, 348–349 dispersion relation, 419 display devices, 288, 447, 450 DMG NWJAMFET, 214–219 DMG NWJLFET, 213–214, 216–219 donor atoms, 70, 85–86 donor traps, 135, 207–208 dopant activation, 22, 31, 67, 100, 281, 287, 291, 299 dopant atoms, 17, 22, 67, 84–85, 93, 103–104, 119, 237, 281 dopant diffusion, 281 dopant dose, 80 dopant inactivation, 92–93 dopantless junctionless devices, 276, 327 dopant-segregated Schottky FETs, 306 doped, 5, 6, 14, 16–18, 22, 25, 28, 32, 34, 37–38, 40, 44, 46–47, 53, 59–60, 62, 67, 69, 71–72, 76, 80–81, 83–84, 86, 97, 99–100, 102–105, 108–109, 116–117, 120–121, 126–129, 131, 133–134, 136–137, 139, 140, 144–146, 148, 152, 163–164, 167, 190–192, 195, 199, 203–205, 209, 213, 224, 226, 229, 232, 250–251, 259, 261, 276, 281, 285–287, 289, 291–292, 294–297, 299, 303–304, 306, 308, 309, 313, 315, 317–318, 321, 323, 359, 402, 432, 436, 440, 443, 446, 449 doping concentration, 6, 14, 16, 31, 48, 72, 74, 84–85, 87–88, 101, 103–104, 126, 141–146, 151, 168, 175, 227, 237, 285–287, 291, 306, 413, 434 doping depth, 144 doping fluctuation, 301 doping gradient, 22, 67, 141–143, 195, 318 doping techniques, 23, 48, 68, 281, 327, 440 doping transition length, 145 double-gate, 25, 29, 60, 71–72, 112–113, 116–117, 123, 126, 165–167, 172, 230, 250, 254, 279, 320, 324, 333, 340, 381–384, 407, 453 double spacer I-MOS, 38 drain, 6 drain conductance, 93 drain current, 7 drain current model, 58, 112, 166, 172, 358, 360–361, 363, 365, 381–382 drain induced barrier lowering (DIBL), 15, 23, 29, 35, 48, 50, 98, 121, 148, 155, 156, 177, 181–182, 184, 186–187, 192, 225, 235–236, 243, 355, 365, 371 drain voltage, 7 drain-induced barrier lowering, 24, 29, 97–98, 139, 148, 181 drain-induced barrier thinning (DIBT), 182, 184, 186, 225, 236, 243 DRAM (dynamic random access memory), 255, 275, 443–444, 450, 453–454 drawn channel length, 22 drift–diffusion, 29 drive current, 3, 12, 50–51, 55, 146, 170, 218–219, 221, 241, 253 dry etch, 81, 450 direct source-to-drain tunneling (DSDT), 19–20, 23, 48, 239–240 dual source, 251, 259, 260, 278 dual-material gate (DMG), 25, 58–59, 66, 115, 157–162, 171–172, 212–220, 250,
INDEX 463 253–254, 277, 323, 380–381, 438, 452 dual- spacers, 154 dynamic boundary conditions, 379 dynamic nonlocal BTBT model, 419 dynamic performance, 46, 56–57, 152, 203, 213, 218–219, 233, 243, 293, 319, 440 dynamic power dissipation, 2, 3, 11 dynamic recombination, 262 dynamically configurable devices, 282 E-beam lithography, 81, 231, 430 EDFET (electrostatically doped), 313–317 EDTFET, 317–319 effective band gap, 80, 182 effective base width, 195, 236 effective carrier mass, 19, 30, 48 effective carrier transport mass, 87, 186 effective channel length, 22, 35, 97, 103–107, 128, 147, 155, 189, 192–193, 216, 239, 272, 300, 370, 439 effective drive current, 219 effective mass, 183–184, 329, 372–374, 421 effective mass approximation, 183, 372–374 effective silicon film circumference, 238 effective tunneling mass, 32 efficient gate control, 50, 55, 173, 180 efficient volume depletion, 143, 162, 222 Eigen values, 187, 329, 376, 377 electric displacement vector, 75, 334, 342, 347, 350, 366 electric field, 5, 6, 12, 15, 20, 29, 3–32, 35–36, 38, 40, 42–44, 57, 68, 70, 74–75, 78, 80, 83, 88, 94, 96, 98–99, 102, 116, 128, 159–161, 173, 182, 188–189, 201, 208, 210, 213–215, 218, 242–243, 245, 256–257, 260–262, 264–269, 272–273, 283, 290, 296–297, 305–306, 312, 314, 318, 330–335, 337, 341, 345, 347, 349, 352, 358, 365–367, 385–386, 388–390, 401–403, 406, 417–419, 422, 436, 439, 442, 445, 452 electrical behavior, 328, 386, 398 electrical displacement vector, 332 electrical junction, 282 electrical shorting, 51 electrical Vernier, 231, 237, 270 electron affinity, 70, 284–285, 309 electron concentration, 6, 71, 76, 78, 85, 133, 185, 223, 225, 228, 232, 264, 267–268, 274, 285, 287, 298, 300–301, 306, 313, 333, 360, 375, 401 electron plasma, 286, 289, 298 electron quasi-Fermi level, 360 electron quasi-Fermi potential, 332, 335, 337, 348, 359, 363 electron redistribution, 187 electron temperature, 260–261, 270 electron velocity, 102, 159–160, 219 electron–hole pair (EHPs), 15, 36, 50, 256–257, 275–276 electronic states, 373 electron–phonon scattering, 89 electrostatic depletion region, 98 electrostatic doping, 282, 287, 313, 315, 319, 327, 440 electrostatic integrity, 47–48, 139, 170, 181, 189, 208, 220, 225, 227–228, 235–236, 251 electrostatic pinch-off, 260 electrostatic squeezing, 98, 177, 195, 300, 439 electrostatically doped, 317 electrostatics, 48, 50, 139, 327, 367, 409 emerging FET, 27, 57, 66, 115, 169, 249, 277, 319, 323, 380, 435, 438, 440, 451 emitter, 40, 110, 175, 192, 258–259, 296, 321 empirical compact models, 328 empirical constants, 328 endurance, 38, 444, 446, 455 energy band profiles, 16, 18, 29, 35, 54–55, 70, 73–74, 76–78, 110, 138, 174, 183, 189, 191, 215–217, 238, 240, 243, 245–246, 282, 292, 306–307, 317, 329, 340, 374, 406, 408, 432–433 energy gained by an electron, 269 energy level, 15, 17, 19, 30, 31, 36, 86, 183–184, 372–373, 420 energy quantization, 50 energy relaxation length, 270 energy states, 17, 19, 30–31, 50, 85–86, 329 energy–momentum relationship, 373
464 INDEX EOT (effective oxide thickness), 91, 94, 106, 119, 121, 133–134, 262–263, 273, 324, 423, 446 EPFL JL-1.0, 351 epitaxial growth, 148 equipotential lines, 333 error function, 343–344, 359 evanescent mode analysis, 379 expectation value, 376 extended back gate, 25, 65, 112, 163, 230, 250, 277, 323, 380, 437, 452 extended measure–stress–measure (eMSM), 94 extended metal electrode on the sides, 286 fabrication complexity, 127, 288, 298, 441, 450 fabrication flow, 51, 80 fabrication point of view, 82 FDSOI (fully depleted SOI), 256–258 feedback loop, 262, 266 Fermi level, 31, 70–71, 76, 86, 100–102, 282, 284, 302–303, 309, 323–324, 360, 377, 440 Fermi potential, 8, 329, 332, 335, 337, 348, 359–360, 363, 371 Fermi–Dirac distribution, 30–31, 184, 374 Fermi-level degeneracy, 102 Fermi-level pinning, 101, 309, 323–324, 440 ferroelectric FET, 27 ferroelectric material, 42–46 FIELDAY, 386 field-effect, 2, 4–5, 14, 25, 27, 58–60, 64–65, 67–68, 115, 118, 125–126, 163, 170–172, 249–250, 254–255, 265, 277, 281–282, 287, 313, 322–323, 327, 333, 380–382, 385, 389, 437, 451–452, 453 field-programmable gate arrays, 315 fin width, 102, 146 FinFETs, 102, 104, 112, 114, 122–123, 152–153, 162, 165, 167, 171, 251, 253, 281, 320, 438 finite difference method, 348–350 first principle analysis, 328 fixed charge, 435 fixed-voltage scaling rule, 12 flash memory, 119, 169, 444–446, 450, 454–456 flat band condition, 71, 77–79, 83–84, 92, 94–95, 99, 127, 139, 263, 300, 335, 344, 348, 351, 360, 439 flat band operation, 78 flat band voltage, 73, 77, 79, 91, 95, 117, 168, 263 flexible electronics, 47 floating, 40, 199, 202, 251, 256, 258, 260–261, 267–268, 275–278, 444–446, 454 floating body effect, 256, 258, 261, 275–276, 278 floating gate, 444–446 flux, 57, 242 footprint, 53, 57, 102, 242 forbidden gap, 29–31, 418 forward bias, 175–176, 258, 266, 286–287 forward sweep, 274 foundry, 328 four probe bending analysis, 88 Fowler–Nordheim (FN) tunneling, 444 free electron, 17, 313 free energy, 42, 43 frequency of operation, 3, 11, 158 fringe capacitance, 156, 160, 218 fringing fields, 57, 102, 112, 155–156, 189, 240, 272–273 front end of line, 449 full depletion, 73, 76, 335, 338, 344, 348, 350–351 full depletion mode, 73, 76, 264, 339, 350, 402 full quantum simulation, 187 full scaling rule, 12 future technology nodes, 144, 241, 298, 328 gadolinium, 284 GaN (gallium nitride), 100, 102, 122, 125 gap length, 293 gate-all-around nanowire, 49, 58, 71, 80, 114–115, 122, 149, 169, 379 gate-bulk substrate capacitance-gate voltage characteristics, 87 gate capacitance, 45–46, 56–57, 92, 136, 156, 218–219, 233–234, 240–241, 442
INDEX 465 gate-channel capacitance-gate voltage characteristics, 87 gate to channel coupling, 210 gate-controlled resistor, 68 gate dielectric, 31, 48, 57, 62, 100, 155–156, 210–212, 243, 252, 273, 293, 295, 394, 449–450 gated intrinsic region, 34–35 gated resistors, 69 gate–drain overlap, 17, 18, 33, 51, 53, 60, 173, 177, 195, 234, 296, 309, 323 gate–drain underlap, 33, 41, 177 gate-drain underlapped architecture, 308 gate electrode, 14, 21, 34–35, 49, 71–73, 77, 81, 107–109, 126, 130–132, 138–139, 141, 146, 149, 154–155, 157, 184, 188, 208, 213, 222, 224, 227, 266, 274, 283, 293–294, 308, 312, 355, 396, 402, 413, 446, 450 gate-induced drain leakage (GIDL), 15, 17–18, 23–25, 50–52, 55–57, 64–66, 110, 115, 151–152, 169–170, 173, 176–177, 179, 181, 183, 185, 187, 189–195, 197, 199, 201, 203–205, 207, 209, 211–215, 217, 219, 221, 223, 225, 227, 229, 231, 233, 235–237, 239, 241–243, 245, 247, 249–250, 277, 308–310, 312, 323, 380, 409, 422, 438, 440, 446, 449, 451, 454 gate leakage current, 178, 196 gate length, 3, 12, 14–15, 18–19, 53, 56, 81, 97–98, 105, 114, 117, 121–122, 134, 139, 143, 144, 147–148, 153, 155, 160–162, 168, 170, 177–179, 189, 192–193, 197–199, 203, 216, 226, 231, 235, 239, 240, 242, 247–248, 253, 256, 271–272, 300–301, 367, 370, 394, 438, 439, 449 gate length scaling, 3, 14, 56, 134, 139, 143–144, 147–148, 177–179, 198, 203, 235, 239, 247–248, 300–301, 449 gate overdrive, 14, 88, 158, 160, 229 gate oxide capacitance, 44, 92, 136 gate oxide damage, 41 gate pitch, 312 gate sidewall spacer, 20, 56, 149, 153–154, 189, 238–239, 273 gate to source capacitance, 136 gate-on source/drain overlap, 18 gate stack materials, 82 gate terminal, 5 gate voltage, 7 Gaussian, 113, 140–141, 167, 384, 395 Gaussian doping profile (GDP), 141–144 Gauss’s law, 332, 338, 343, 347, 350–351, 358 generation current, 290 generation rates, 419 generation–recombination noise, 96 GeO2, 100 germanene, 47 germanium, 32, 47, 83, 100–101, 106, 118, 120–121, 153, 167, 302, 323–324, 438, 454 GHz frequency, 46 glass substrate, 68, 319 Global Foundaries, 49 gold, 284 graded doping profile, 31 gradual channel approximation, 329–331, 357 grain orientation, 107–108 graphene, 46–47, 63, 68 graphical user interface (GUI), 395, 397, 426–428 graphite, 46 green electronics, 451 grids, 386 ground plane, 34, 131, 133–136, 204–205, 411–412 ground plane doping, 134–135 GUI + command file, 428 hafnium, 44, 46, 285, 289, 291, 298, 305 hafnium oxide–based ferroelectric materials, 46 half logic function, 10 Hamiltonian, 329, 376 Hamiltonian operator, 329 hard breakdown, 248 HBJLFETs, 136 heart of the JLFET, 71 heavily doped, 17, 34, 67, 69, 72, 80, 90, 97, 104, 126, 192, 213, 259, 294, 308 Heisenberg principle, 373
466 INDEX heterodielectric, 33, 60, 115, 164, 204, 207, 212, 252, 277, 296, 323, 380, 438, 451 heterodielectric buried oxide (BOX), 33 heterogate dielectric, 210–212 heterostructures, 33, 38, 63–64 HfAlOx/HfZrOx, 46 HfO2, 25, 62, 65, 131, 133–135, 137, 154, 155, 189, 205, 207, 210, 212, 231, 250, 252, 449 high electron mobility transistors (HEMTs), 102, 122 high injection effects, 286–287 high mobility materials, 83, 100, 125 high performance (HP), 53 high temperatures, 90, 94, 281 high work function, 71 high-frequency, 2, 12, 39, 102, 136 high–low junction, 126, 128, 142, 143, 145, 192 highly doped, 76, 108, 226, 261 high-resistance, 6 high-, 31, 33–34, 57–58, 64, 111, 131, 135, 153–156, 162, 164, 169, 170–172, 189, 204–208, 210–212, 231, 239, 251–252, 272–273, 294, 305, 409, 445, 454 high- dielectric, 34, 64, 131, 155, 204, 206, 210, 212, 231, 273, 445, 454 high- gate dielectric, 31, 58, 111, 210, 273, 294 high- spacer, 57, 155–156, 171–172, 189, 239, 272 hit and trial, 413, 421, 433, 435 hole accumulation, 188, 202, 222, 257 hole concentration, 175, 185, 195, 200, 227, 232, 264, 265, 266, 274, 286, 287, 291, 313, 385 hole density, 201 hole gas, 101 hole generation rate, 174–175 hole plasma, 285–286, 289 hole sink, 199–200, 201–203 Hooge mobility, 95 hot electron effect, 39, 41, 99, 127 hot electron generation, 38 hot electron injection, 444 hot electrons, 15, 38, 99 human body–gadget analogy, 1 hybrid channel, 25, 65, 123, 170, 250, 277, 322, 362, 364, 380, 437, 447, 448, 451 hysteresis, 40, 45–46, 62, 274–275, 444 IBM, 49 ideal switches, 2 III–V heterojunction TFETs, 32–33 III–V materials, 32–33 IMEC, 49 IMOS (impact ionization MOS), 27, 34–41, 57, 60–61, 287–290, 321–322, 440–442, 453–454 I-MOS with a Schottky source junction, 38 impact ionization, 15, 27, 34–41, 44, 61, 68, 99, 127–128, 197, 248, 255–277, 287–288, 290, 322, 390, 402, 439, 440, 442, 452 impact ionization coefficients, 37 impact ionization induced steep subthreshold swing, 260 impact ionization rate, 38, 99, 261, 267, 270, 442 impact ionization–dominant regime, 263 impurity scattering, 80, 84–85, 90, 93, 102, 109, 116, 127, 166, 186, 228, 299, 390, 402, 417 in-built electric field, 70 inclined motion, 271 incomplete ionization, 92, 299 independent operation, 53, 270 indirect band gap materials, 32 indium gallium arsenide, 83 induced carriers, 176, 282 inductive plasma etching, 49 inefficient volume depletion, 222, 333 InGaAs, 60, 83, 100–102, 121–122, 125, 196–197, 251 inherent scaling advantage, 226 initial guess, 345–347, 390, 403–404, 420 InP (Indium phosphide), 60, 102, 122 input capacitance, 3, 9, 12 input impedance, 15 input logic, 9 in situ doping, 53, 101, 148, 220 insufficient volume depletion, 188 insulator, 5, 33, 44, 68, 71, 99, 101–102, 116–118, 120–121, 130, 163–164, 174,
INDEX 467 256, 283, 285, 303–307, 323–324, 333, 381–382, 389, 410, 440, 449, 452, 454 integrated circuits, 2, 9, 31, 449 integration constant, 343, 345 Intel, 49 intentional gate misalignments, 270 interband tunneling, 34, 58, 381 interconnects, 449 interdiffusion, 157, 162, 172, 212 interface states, 79, 88, 252, 302 intergate coupling, 315, 319 internal amplification, 40 International Technology Roadmap for Semiconductors (ITRS), 160 Internet of Things, 440 intraband, 19, 48, 240 intraband tunneling, 19, 240 intrinsic carrier concentration, 76, 329, 345, 377 intrinsic channel, 28–29, 37, 298–299 intrinsic core, 226–230 intrinsic delay, 32, 56, 126, 156–157, 219, 234, 241, 243 intrinsic Fermi level, 71, 76 intrinsic performance, 89 intrinsic region, 35–36, 228, 288 intrinsic silicon film, 282, 291, 294, 298 inversion, 4, 6–7, 20–21, 29, 36–37, 50, 53–54, 58, 62, 72, 76, 80, 83–85, 87–88, 94, 101, 108, 113, 115, 117, 119, 123, 126–127, 153, 164–167, 252–253, 261–262, 317, 329, 359–360, 373, 382, 396, 432, 438 inversion layer, 6–7, 20–21, 29, 36, 72, 76, 80, 83–85, 87–88, 101, 108, 261–262, 329, 359–360, 396, 432 inversion layer charge, 7, 20–21, 329, 359–360 inverter, 9–11, 53, 136, 156, 219, 234, 241 ion bombardment, 275 ion implantation, 17, 22, 67, 81, 101–104, 141, 148, 203, 229, 237, 281, 287, 291 ION/IOFF, 9, 11–12, 14, 22, 60, 110, 121, 131, 141, 143, 156–157, 177, 186, 191, 193, 203, 205, 213, 222, 224–227, 229, 231, 233–237, 239, 241–244, 246–248 ionization, 27, 36–39, 60–61, 93, 99, 136, 248, 255–257, 260–268, 270, 272–276, 278, 288, 290–291, 299, 321–322, 439, 442, 453 ionized impurities, 84–85, 93 ion strike, 276 isoelectronic point, 442 JAMFET (Junctionless accumulation-mode FET), 126, 128, 191–192, 193–194, 196, 212, 219–220, 231, 306 JIMOS (junctionless I-MOS), 289–291 JLFET-based biosensor, 442 JLFETs (Junctionless FETs), 25, 58, 64–65, 69, 70–72, 76–80, 82–113, 115, 123, 125–132, 134, 136–137, 140, 143–144, 146–149, 151–164, 166–167, 170, 173, 175–179, 184, 186–187, 189–190, 192, 199, 203–204, 206, 209–212, 220, 231, 235–237, 239, 243, 248–253, 255, 258, 260–270, 272–277, 287, 291, 294, 297–308, 310–311, 318–320, 322–323, 327, 329–331, 333, 335, 337, 339, 341–345, 347–351, 358, 365, 367, 369–371, 377, 379–380, 383, 385–386, 390, 394, 396, 402, 406, 409, 411, 413, 415, 417, 419–422, 432, 435–440, 442–443, 445–447, 449–451, 456 JLTFET (junctionless tunnel FET), 291–297 JLTFT with a hybrid channel, 447 JLTFT with a stacked hybrid channel, 447–448 Julius Edgar Lilienfield, 68 junction FETs, 68 junctionless polysilicon TFT, 447 kinetic energy, 15, 36, 99, 256, 373 kink, 192, 202, 251, 258, 260, 262, 278 kink effect, 192, 202, 251, 258, 260, 278 Koomey’s law, 13, 23 Lambert W function, 340 Landau’s theory, 43 Landaur’s approach, 329 large and negative gate voltages, 51, 194–195 larger doping, 187
468 INDEX laser annealing, 292 lateral band-to-band tunneling (L-BTBT), 50–51, 55–57, 110, 151, 173–174, 180, 184–185, 189, 191–192, 196, 199, 214, 222, 239, 308–310, 422–423, 432 lateral electric field, 15, 99, 256, 260, 417, 442 lateral heterostructure, 33 lateral nanowires, 221 lateral NWFETs, 49 lateral straggle, 17, 22 lateral tunneling, 177 lattice mismatch, 44, 100 L-BTBT-induced shielding effect, 186, 188 LDD (lightly doped drain), 18, 25, 38, 60, 296–297, 321 lead titanate (PbTiO3), 43, 46 lead zirconate (PbZrO3), 43, 46 leakage current, 2, 11, 14–15, 18, 25, 29–31, 36, 38, 48, 51, 64, 71, 90, 101, 106, 110, 115, 133, 138, 140–143, 149, 163, 171, 177–179, 182, 185–187, 191, 195–199–209, 212, 222, 227, 239, 248, 250, 253, 255, 277, 292, 322, 380, 409, 437, 440, 447, 451 leakage mechanism, 151–152, 184, 191 length of source/drain contacts, 243 length of the source/drain electrodes, 311–312 LER (line edge roughness), 106–107 life time, 259 lightly doped, 6, 40, 80, 92, 97, 126–127, 259, 303, 308–309 lightly doped source, 97, 259 Lilienfield transistors, 68 line contacts, 396 linear region, 361 load capacitance, 3, 9–10, 11–12 local BTBT models, 418 local doping, 105 localized states, 93, 104 location of the subbands, 93 logic applications, 450 logic performance, 234 Lombardi mobility model, 402, 417, 432 long-channel MOSFET, 15 long-channel JLFETs, 90–91, 330, 365, 379, 391, 406, 417, 436 long-channel surface potential, 367 longitudinal electric field, 83 loss of gate control, 110, 188, 193, 197, 239 low drain doping, 33 low field mobility, 87 low standby power (LSTP), 53 low temperatures, 90, 93, 117, 273 low work function, 71, 173 low-frequency noise (LF noise), 60, 95, 119–120, 169, 323, 447 low resistance, 6 low-, 33, 210–212, 273, 303, 449 low- gate dielectric, 210–212 low- spacers, 33 Maclaurin series, 350 macroscopic behavior, 385 majority carriers, 6, 71, 76–77, 80, 264, 286–287 material specific, 389, 402 mathematical solver, 388 Matthiessen’s rule, 84 maximum frequency of operation, 158 Maxwell–Boltzmann distribution, 3 mean free path, 54, 88–89 mechanical exfoliation, 48 memory allocation, 395 memory cell, 96, 443, 445–446, 454–456 mesh, 386–389, 392, 394–397, 401, 403, 413, 416, 419–420, 426, 428, 432 mesh engine, 389, 397 mesh points, 386–389, 395–397, 413 mesh spacing, 394–397, 413 metal, 2, 3, 5, 10, 17, 25, 27–28, 34, 44, 47, 51, 53, 61, 63–64, 67–71, 81, 101–102, 109, 116–117, 120–121, 123, 125–126, 130, 133, 157, 162–164, 171–173, 205, 252–253, 255, 278, 281–287, 293–294, 298, 302–305, 309–310, 313–315, 320–324, 329, 340, 381–382, 389, 402, 409, 422, 432, 439–440, 449, 452–453, 455–456 metal interdiffusion technique, 157 metal organic regrowth process, 101 metal wet etch process, 157
INDEX 469 metal-induced interface states, 302 metallurgical junction(s), 58, 68–69, 82, 97–98, 137, 145, 199, 238, 260, 281–282, 288–289, 327, 439–440 metal–semiconductor (M–S) junction, 282 metal–semiconductor work function difference, 70 metastable polarization states, 42 MFMIS, 44–45 microscopic properties, 328, 385, 388 microwave annealing, 28, 31, 148, 199, 203, 220 midgap, 127, 135, 208, 298, 302, 306, 432 midgap work function, 127, 298 MIGS (metal-induced gap states), 302–304, 306, 309, 440 Miller capacitance, 33, 53, 136, 234 minimum central potential, 369 minimum surface potential, 371 minority carrier, 20, 175, 286–287 minority carrier injection, 175 MIS, 303–308, 311 misalignment, 165, 206–207, 247, 270–271, 276, 279 mobile carriers, 84, 125, 142–143, 359, 367 mobile charge Qm, 87, 347, 353–356, 360–361, 363, 374 mobile electron charge, 345 mobility, 48, 50, 53–54, 64, 79, 80, 82–96, 100–104, 109, 116–117, 121, 125, 127, 144, 146, 163–164, 186, 213, 228–229, 232, 273, 299–300, 329, 385, 390, 402, 417, 432–433, 437, 446 mobility reduction coefficient, 87 model calibration, 388–389, 407, 409–410, 420–422, 433, 436 modeling approaches, 327, 329 moderately doped, 103, 140, 204 modes, 4–5, 55, 80, 95, 342 modified local density approximation, 199 molecular beam epitaxy, 292 molecular monolayer doping, 148, 164, 199, 203, 220, 226, 229, 252 momentum, 15, 32–33, 99, 256, 373 momentum space, 373 monolayer, 47–48, 63, 148, 164, 199, 203, 220, 226, 229, 252 Moore’s law, 13, 23–24, 449 MOS capacitor, 4–6, 14, 70, 71, 313 MoS2, 47 MOSFET as a switch, 3, 9 MOSFETs, 2–4, 6, 9–15, 17–19, 22–24, 27–28, 30–32, 34, 38, 40, 42–43, 45–46, 49–52, 57, 62, 65, 67–69, 72–73, 76, 79–80, 82–83, 84–90, 92, 94–110, 112–116, 118–123, 125–127, 162–169, 172–173, 177, 191–192, 196–197, 202, 236, 248, 250–251, 253, 255–263, 274–279, 281, 291, 298, 300, 310–311, 318–320, 324, 329, 331, 340, 345, 358–360, 366, 370–371, 373, 379–384, 396, 439–440, 443–444, 446, 449–450 M–S (metal-semiconductor), 282–283, 285, 302–304, 306–308, 309–310, 313–314 MSM (metal-semiconductor-metal), 313–314 multigate, 61, 71, 109, 112, 119–120, 148–149, 151–152, 163–164, 249, 278, 333, 452 multiple box placement, 396 multiple hybrid channels, 447 multiple threads, 403 multithreshold, 53, 447 n+ active shell layer, 220 nanocavity, 441 nanogaps, 441 nanorods, 53, 66, 254 nanotube, 25, 27, 52, 53, 58, 65, 66, 115, 172, 195, 237–238, 251, 254, 277, 320, 323–324, 380, 438, 452 nanowire diameter, 50, 179–182, 184, 186, 197–198, 220–222, 224, 385, 435 nanowire dopings, 187 nanowire width, 123, 250, 297, 436 nanowires, 27, 49–50, 80, 100–101, 118, 152, 165, 169, 221, 229–230, 242, 384, 423, 433–434, 455 native oxide, 83 natural length, 366–367 nature of GIDL, 51, 177, 191 NCFETs (negative capacitance FETs), 42–46, 57, 440 n-channel JLFETs, 79
470 INDEX n-channel MOSFET, 79, 277 negative body factor, 46 negative capacitance, 42–43, 45–46, 61–62, 440 negative differential resistance, 34, 274 negative gate voltages, 110, 176, 191, 194, 197, 236, 239, 270, 309, 423 NEGF (nonequilibrium Green’s function), 114, 169, 328–329 neighboring mesh points, 388 neutral channel, 95–96, 369 neutral conduction path, 76 neutral defect scattering, 91 neutral impurity defect scattering, 92 neutral region, 72, 76–77, 93, 96, 142, 184, 256 Newton method, 390, 403 Newton solver, 404–405, 419–420, 432 Newtonian perspective, 17 nickel, 284, 313, 317 nickel silicide, 313, 316–317 nitride layer, 435, 445–446 nitrogen ambient, 80 node, 27, 44, 57, 106, 117, 160, 162, 171, 281, 395, 400–401, 404–405, 417, 431–432, 433 nodes, 315, 329, 386, 422 noise floor, 446 noise immunity, 39 noise power spectral density, 95–96 noncatalytic growth, 49 noncentrosymmetric structure, 42 nonlocal BTBT models, 418 nonlocal mesh, 413, 419–420, 426, 432 nonlocal mesh lines, 419–420 nonlocal path, 419 nonlocal tunneling model, 409, 413, 419, 432 nonuniform carrier concentration, 290 NOT gate, 9 n-program mode, 316 NTFETs (nanotube FETs), 52–57, 238, 240, 440 n-type doped semiconductor, 5, 282 n-type MOS capacitor, 5–6 number of cores, 395 number of iterations, 391, 404 numerical integration, 359, 365 numerical simulations, 327, 352, 388, 438 numerical simulations, 374 numerical solver, 8, 390, 395, 403, 407, 432 numerical solvers, 8, 187 NWFETs (nanowire FETs), 50–57, 88, 114, 151, 167, 191–193, 195, 197–199, 313, 422–423, 433–436, 440 NWJAMFET, 191–198, 213–219, 238–239 NWJLFETs, 80–82, 85, 88, 157, 178, 179, 180–198, 212, 213–215, 217–218, 220–224, 226–227, 229–230, 238–241, 333, 385, 433–435, 446 NWMOSFETs, 51, 54, 56, 173, 190–195, 423, 431–432 OFF-state, 2–3, 7, 9, 11, 14, 19–20, 22, 29, 33–36, 38, 45, 50–52, 55–57, 71, 89, 97–98, 102–103, 106, 108–110, 121, 125–131, 133–135, 137, 138–143, 145–147, 149, 151, 153–156, 158–162, 173–182, 185–187, 189, 190–193, 196–209, 212–221–236, 238–247, 255, 261, 277, 292, 295–298, 300–301, 309–311, 314, 316–317, 330, 423, 432, 439–440, 447 OFF-state current, 3, 9, 11, 14, 19, 22, 35–36, 52, 55–57, 89, 102, 106, 110, 121, 128, 130, 134–135, 137, 139–141, 143, 145–147, 153–156, 158, 160–161, 176–177, 179–180, 182, 186–187, 189, 190–192, 197–199, 201, 203, 205, 209–219, 221, 222, 224–229, 231–232, 234–236, 238–247, 295–298, 300–301, 310–311, 317, 423, 447 Ohm’s law, 329, 356–357 Ohmic contacts, 33, 69, 80, 100, 103, 109, 140, 209, 227, 304, 309, 324 O-N-O (oxide-nitride-oxide), 446 ON-state, 2–3, 7–9, 11–12, 14, 20, 22, 28–34, 36, 45–46, 48, 50–52, 54–55, 58, 78–80, 84, 89–90, 92, 94–95, 99, 102–103, 106, 108–110, 126–128, 131–134, 137–147, 153–156, 158–161, 177, 182, 186–187, 190–191, 203, 206, 209–210, 213, 215, 218, 221–222, 224–225, 227–229, 231–233, 239, 241,
INDEX 471 245–247, 290, 292–301, 303–305, 308, 310–312, 314, 316–319, 344, 433, 439–440, 447, 449 ON-state current, 3, 8, 9, 12, 14, 22, 31–33, 46, 48, 50–52, 54–55, 80, 89–90, 102–103, 108–109, 126, 132–133, 137, 139–140, 143–145, 147, 153, 155, 159–161, 186, 190–191, 203, 206, 209–210, 213, 215, 218, 222, 224–225, 227–229, 231–232, 239, 245, 247, 290, 293–296, 298–301, 303–305, 308, 310, 312, 317–319, 433, 440, 447, 449 ON-state to OFF-state current ratio, 3, 186 open base configuration, 39–40 open switch, 6 operating regionwise approximation, 341 operating voltage, 32, 38–41, 60–61, 94, 126, 288, 290, 321–322 optical phonons, 89 optoelectronic, 47, 288, 447 orbital, 374 oscillation peaks, 93 oscillations, 92–93, 119 outer fringe capacitance, 57 outer gate, 53–54, 237 outer surrounding gate, 56 output characteristics, 7, 33–34, 158, 233, 258, 274–275, 286, 289–290, 385, 443–444 output logic, 9 output swing, 41 overlap resolution, 394, 413, 426 overshoot, 53, 136, 234 oxide, 2, 3, 5, 10, 12, 15, 21, 25, 27–28, 33–34, 38, 40–41, 43–47, 53, 61, 67–68, 73, 75–76, 80–81, 83, 88, 90–92, 94–97, 99–101, 105, 108, 116–117, 120–121, 125–126, 131, 133, 136, 151, 160–161, 163, 171, 173, 204, 208, 212, 231, 254–255, 262–266, 273, 275–276, 278, 281, 283, 285, 317, 322, 324, 329, 332, 340–341, 359, 367, 371, 373–374, 381–382, 389, 391–393, 407, 409–411, 423–426, 435, 439, 440–441, 446, 449–450, 452–454 p+ core, 220–222, 226 palladium, 285 Pao–Sah integral, 319, 353, 356, 359–360, 363, 365 parabolic approximation, 340, 344, 348, 354 parabolic potential approximation, 366–367 parabolic potential profile, 344 parameter file, 388–389, 390, 401, 405, 417, 421, 433 parasitic bipolar effect, 258–260, 263 parasitic BJT, 40, 110, 128, 162, 175–179, 189, 192–193, 195–199, 203, 205, 209, 214, 222, 231, 236, 239, 245, 248, 255, 258–259, 296 parasitic BJT action, 25, 65, 110, 123, 162, 170, 176–177, 178–179, 185, 189, 195–196, 199, 201–203, 205–206, 209, 214–215, 222, 226, 231, 236, 239–240, 245, 247–248, 250, 254–255, 258, 277, 296, 322, 380, 437, 451 parasitic BJT effect, 206, 239, 258–259 parasitic BJT theory, 194–195, 197 parasitic capacitance, 62, 152, 160–161, 293–294, 315, 319 parasitic Fermi level pinning, 302 parasitic inner fringe capacitance, 161 parasitic series resistance, 155 partial depletion, 71, 76–77, 96, 264, 335–336, 344, 348, 351, 364 partial depletion mode, 76–77, 84, 96, 127, 264, 344, 348, 351, 362, 364 passivated, 47 Pauli exclusion principle, 5 partially depleted SOI (PDSOI), 202, 256–260, 274, 276 percolation of contaminants, 44 permittivity, 42, 73, 75, 285, 331–332 perturbation energy, 376 perturbation in the surface potential, 365 perturbation potential, 183, 184, 376–377 pH, 442 phase space, 373 Philips unified mobility model, 390, 402, 417, 432 phonon scattering, 84, 90–92, 402, 432 phosphorene, 47 phosphorus, 47, 103, 164, 395
472 INDEX phosphorus doping, 103 photolithography, 81 photoresists, 106 physical basis, 13, 328 physical equations, 328, 386, 388, 390–391, 395, 401, 403–404 physical gate length, 97 physical layer thickness, 139 physical models, 386, 388–390, 401–402, 405, 407, 414, 417, 419, 432 physical shell thickness, 222 piezoelectric, 42 piezoresistance, 87–88, 118 piezoresistance coefficient, 87–88 p–i–n, 28, 29, 31–32, 34–39, 41, 195, 288, 291–292, 294, 317, 441 pinched off, 232, 362 Planck’s constant, 373 plasma implantation, 292 plasma-treated nanosphere lithography, 53, 66, 238, 254 platinum, 109, 130, 285, 289, 291, 294–295, 402, 426 PLT file, 388 p–n junction, 5, 14, 16–17, 22, 67–68, 71, 121, 137, 139–140, 152, 175, 192, 199–201, 203, 208, 258, 447 p–n–p–n TFET, 31 pocket, 31–32, 59, 167, 293, 322 Poisson equation, 8, 73, 103, 146, 184, 328–329, 330, 333–334, 336, 338, 340, 345, 346–349, 358, 365–367, 372, 374, 386–387, 390, 403–404, 420 polarity gate, 282, 313–317, 319 polarization, 42–43, 45–46 polarization switching, 43, 46 polarization switching time, 46 polysilicon channel, 446–447 polysilicon junctionless thin film transistors, 447 positive feedback, 34, 36, 40, 256, 258, 266, 270, 274 potential barrier, 16–17, 19, 30, 85–86, 104, 175, 183, 227, 236, 245, 258, 274, 292, 296, 303, 314, 358, 373–374, 376 potential distribution, 73, 331, 337, 340, 342, 377, 385 potential fluctuation, 104 potential mirroring effect, 227 potential profile, 269, 300, 333, 344, 348, 350, 367, 386, 388, 436 potential well, 16, 85–86, 373–374, 376 power consumption, 2, 3, 11, 13 power dissipation, 3–4, 11, 13, 23, 48, 51, 90, 102 power-driven scenario, 4 principal quantum number, 374 pristine surface, 48 process flow, 44, 80–82, 104, 131, 152, 231, 243, 387, 449 process variation, 108, 125, 206, 236, 302, 318, 323, 440 program mode, 444–445 program/erase operation, 444 programming window, 446 proteins, 441 proton implantation, 259 pseudo-2D method, 340 pseudojunctionless, 126, 213 p-type doped semiconductor, 5 p-type MOS capacitor, 5–6 quantization effects, 183, 186, 198–199 quantized electrons, 373 quantized energy, 374 quantum confined electrons, 373 quantum confinement, 25, 65, 86, 101, 112, 163, 182–184, 186–187, 198–199, 250–251, 277, 323, 372, 379–380, 382, 389, 437, 452 quantum confinement effects, 50, 86, 93, 101, 182, 184, 186, 198, 199, 235, 328 quantum correction models, 199 quantum correction term, 379 quantum dots, 93 quantum electron density, 184, 254, 377 quantum harmonic oscillator, 374, 377 quantum limit, 328 quantum mechanical perspective of electron, 17 quantum mechanical phenomenon, 389, 418 quantum mechanical treatment, 302 quantum mechanics, 328 quantum number, 377
INDEX 473 quantum transfer characteristics, 379 quantum well, 183, 196–197, 376–377 quasi-2D approach, 366, 370 quasi-2D scaling equation, 366, 368 quasi-2D scaling theory, 367 quasi-electron Fermi-level, 329 quasi-stationary energy states, 85–86 radio frequency, 2, 39, 95 radio frequency circuits, 2 rail-to-rail swing, 38–39, 41 random dopant fluctuation (RDF), 53, 93, 104–107, 123, 125, 128, 203, 276, 281, 291, 294, 297, 302, 308, 313, 315, 318, 320, 323, 440 random telegraph noise (RTN), 97 rapid annealing, 82 rapid thermal oxidation, 81 reactive-ion etching, 238 read margin, 443 read operation, 444, 446 receptors, 441 recombination, 40, 80, 96, 128, 262, 275, 390, 402, 405, 417–419, 432, 438 recombination centers, 259 recombination lifetime, 80 recombination rate, 80, 128 reconfigurability, 313 reconfigurable electrostatic doped FETs, 315 reduced Planck’s constant, 30, 184, 372 ref/eval window, 396 refinement size, 395–396, 411, 413, 424, 426 regional approximation approach, 363 regionwise refinement, 396 reliability, 24, 38, 59–60, 82, 90, 94–95, 99, 116, 120, 125, 127, 169, 248, 298, 321, 381, 439, 452 remnant polarization, 46 resistivity, 40, 69, 87, 103, 306, 307, 324, 356 resist roughness, 106 resonant transmission, 86 resonant tunneling, 85–86 retrograde doping, 145–148 reverse biased, 16, 28–29, 34, 71, 288, 291–292, 317 reverse sweep, 273 RGB, 396 rough sketch, 391 routing complexity, 131, 444 saturation, 33, 39, 102, 158, 176, 193, 218, 232–233, 358, 361, 364, 417, 432 saturation characteristic, 232 scaling factor, 12, 366–367 scattering centers, 84, 93, 402 scattering events, 79, 83, 89 Schottky barrier, 25, 61, 65, 93, 101, 250, 303, 306, 309–311, 313–314, 316, 322, 324 Schottky tunneling, 306, 314 Schro¨dinger equation, 16, 183, 328–329, 372, 374 Schro¨dinger–Poisson model, 187 scotch tape, 48 screen gate, 157 screening effect, 84–85, 108, 117, 163 screening length, 103 SDE, 387–391, 394–398, 401, 428 Sdevice, 387–391, 397, 401–405, 413, 420–421, 431–432, 435 second-order differential equation, 366–368 second-order linear differential equation, 340 selective epitaxial growth, 53, 449 self-aligned gate, 17 self-consistent solution, 328, 350, 372, 374 self-limited oxidation, 49, 423 semiclassical transport, 328 semiconductor, 2, 5–6, 10, 16, 21–23, 25, 27–28, 44–45, 47, 54, 61, 63–64, 67–71, 73, 76–78, 80–81, 86, 92, 95, 103, 105, 111, 116–121, 125–126, 163, 171, 173, 248, 255, 281–285, 302–304, 309–310, 312–313, 322–324, 329, 332, 340, 351, 373, 382, 389, 391, 422, 436, 439–440, 452–454 semiconductor capacitance, 21, 45, 92 sense amplifier, 443 Sentaurus device, 387 Sentaurus mesh, 387 Sentaurus process, 387 Sentaurus structure editor, 387 Sentaurus TCAD, 386–387 Sentaurus visual, 388
474 INDEX sequential 3D integrated circuits, 449 series resistance, 29, 33, 35, 80, 91–92, 97, 102–104, 125–127, 133, 139, 144, 153, 155, 162, 186, 190–191, 206, 213, 224–225, 227–229, 232, 288, 297, 299, 310, 317, 433, 440, 447, 449 sheet conductivity, 356 sheet resistivity, 103 shell layer, 220 shell thickness, 220–222, 224–225, 227–229 shielding effect, 85, 185, 197, 222, 390 Shockley, Brattain, and Bardein, 68 Shockley–Read–Hall (SRH) recombination, 80 short-channel, 3, 13–15, 19, 22–24, 29, 31, 35, 48, 50–52, 62, 83, 91–92, 97–100, 102, 106, 108, 112–114, 120, 125, 128, 139, 144, 147, 152–153, 155, 157, 159, 165–168, 170, 173, 177, 179, 187, 192, 213, 215–216, 228, 237, 240, 243, 256, 272, 298, 300–301, 365, 367–368, 370–371, 379, 381–384, 406, 409–410, 413–414, 417–418, 420, 422, 432, 436, 439, 441, 446–447, 449 short-channel effects, 3, 13–14, 22, 23–25, 27, 29, 31, 35, 38, 41, 50, 52, 62, 65, 79, 83, 90, 96–97, 100, 102–103, 105–106, 108, 112, 114, 116, 118–120, 123, 125, 128, 139, 144, 147, 153, 155, 157, 159, 163, 165–166, 168, 173, 182, 184, 187, 189, 192, 213, 215–216, 228, 237, 243, 250, 251, 252–253, 263–264, 267–268, 272, 276–279, 298, 300–301, 320, 323–324, 365, 367, 371, 380–381, 383, 390, 396, 406, 437, 439, 441–442, 446–447, 449, 452–453 short-channel JLFETs, 92 Si3N4, 189, 243, 246, 445 SiCN–SiCN, 449 side contacts, 302, 304 SiGe source, 259 signal-to-noise ratio, 441 signum function, 351 silicene, 47 silicide formation, 283, 285, 304 silicon, 2, 5–6, 19, 24, 32–33, 40, 44, 47–49, 53, 55, 57, 64–65, 69, 71, 73–81, 83–85, 87–89, 91, 93, 95–97, 100–101, 103–109, 114–119, 121–122, 125, 130, 134–135, 137, 144, 152–153, 163–164, 169–171, 173–174, 178–180, 184, 186–189, 198, 203, 208–209, 212, 221–222, 226, 231, 235–238, 242–244, 249, 251, 253–254, 256, 261–262, 265–267, 270, 274–276, 282–283, 285–286, 288, 291, 294, 297–298, 301–304, 306–314, 316, 318, 321, 324, 328–329, 331, 333, 335–338, 340–341, 343–344, 347, 351, 355, 359, 365, 371, 377, 381, 392, 394–396, 402, 405, 410, 413, 420, 422, 424, 426, 428, 435, 438, 440–443, 445–447, 449, 452, 454, 456 silicon film, 53, 57, 69, 73–75, 76–81, 83, 87, 95–97, 103–106, 108–109, 125, 130, 144, 173, 178–180, 184, 186–189, 198, 203, 208–209, 222, 226, 236–238, 242–243, 261, 265–267, 270, 274–276, 282, 285–286, 291, 294, 297–298, 301–303, 306–308, 310–313, 318, 328–329, 331, 335–338, 340–341, 343, 347, 351, 355, 359, 365, 371, 402, 413, 420, 426, 440, 442, 446, 449 silicon film thickness, 53, 73, 76–77, 78–80, 83, 96–97, 103, 105–106, 108–109, 125, 130, 173, 178–179, 180, 184, 186, 198, 203, 208–209, 222, 236, 242, 265–266, 275, 285, 297, 302, 308, 318, 336, 340, 347, 365 silicon nanocrystals, 445 silicon-on-thin BOX (SOTB), 231 silicon thickness, 48, 53, 55, 57, 76, 85, 89, 93, 107–108, 186, 222, 235–236, 341 Silvaco Atlas, 344 Silvaco TCAD, 386 simulation deck, 434–435 simulation time, 388–389, 395 single crystal silicon-on-glass substrates, 288 single event upset (SEU), 276 single transistor latch-up, 255, 266, 273, 276 single gate, 72, 74, 76, 109, 149, 150, 330, 333, 338, 412, 455 Si–SiO2, 5, 29–30, 50, 56, 73, 75, 78, 89, 99, 103, 110, 129, 134, 146, 174, 181, 183–184, 188–189, 191, 204, 215–217,
INDEX 475 223, 228, 231, 236, 238, 240, 242–243, 245, 262, 274, 307, 314, 316, 318, 332, 334, 338, 342–343, 347–350, 366, 373, 391, 408, 418, 432–433, 435 Slotboom, 116, 390, 402, 432 smart-cut process, 131 SMG (single material gate), 157–160, 213–219 snapback, 274–275, 279, 443, 453 snapback effect, 274 soft breakdown, 248 SOI (silicon-on-insulator), 24–25, 33, 60, 65, 71, 80–81, 91, 109–110, 112, 116, 120–121, 130–143, 149, 151–156, 163, 167, 171, 174–175, 177–178, 192, 199, 200–209, 231, 244–245, 247–251, 253, 256, 258, 260, 277–278, 283, 285–286, 294–295, 321, 323, 333, 338, 379–383, 410, 413–414, 431, 436–438, 440, 443, 449–451, 453–454 solution-processed growth, 49, 51 SONOS, 119, 169, 435, 445–446, 454–456 source, 6 source/drain depletion regions, 97, 370, 379 source/drain extension region, 53, 153, 190, 306, 308 source/drain junction, 69 source/drain series resistance, 91, 97, 103, 126, 229, 447, 449 source/drain-induced depletion region widths, 14 source-to-channel barrier height, 15, 54, 89, 176–177, 181, 192, 194, 201, 207, 210, 222, 232, 269 spacer length, 205, 242–243, 310–312, 396 spacer thickness, 53 spatial generation, 418 spatial proximity, 28–29, 50, 180, 192, 292, 317, 406, 417 speed of NCFETs, 46 spike annealing, 31 split capacitance–gate voltage (C–V) measurement, 87 Sprocess, 387–388 SRAM (static random access memory), 59, 104, 115, 165, 169 SRH (Shockley-Reed-Hall), 80, 96, 176–177, 390, 399, 402, 405, 414, 417, 420, 429, 432 standard deviation, 141, 143–144 standby performance, 57 static behavior, 355 static performance, 203, 218 static power dissipation, 2, 3, 11 steep switching, 27–28, 45, 263, 273, 279, 290, 442 step doping profile, 144–148 step size, 404, 420 stochastic distribution, 22, 67, 281 strain engineering, 87 strain-enhanced mobility, 88 streptavidin, 441 stress, 37–38, 49, 87–88, 94, 99–100, 118, 207, 248, 407, 423 stress-limited oxidation, 49 stretch out in the C–V characteristics, 103 strong inversion, 373 sub-10 nm, 27, 48, 51, 55, 57, 63, 67, 88–89, 110, 179, 219, 220, 226, 248, 255, 281, 329, 372, 422 subband, 182–184, 198, 235, 328–329, 372–374, 376–378 subband gap, 268, 270 subband quantization, 328 substitution method, 345 substrate bias, 130, 132, 140, 267–268, 276, 278 substrate doping, 140, 153 subthreshold current, 14, 21, 90, 108, 114, 168, 360, 365, 383–384 subthreshold regime, 7, 21, 89, 218–219, 252, 358, 361, 366, 374, 378, 402 subthreshold slope, 9, 22, 32–33, 34, 41, 44, 59, 61–62, 104, 111, 127, 145, 148, 155–156, 248, 260, 276, 278, 294, 452 subthreshold swing, 9, 11, 21, 22, 27, 30–31, 34, 38, 42, 45, 50, 57–58, 105, 106, 111, 153, 155, 182–183, 228–229, 231, 233, 239, 255, 260, 267–268, 271–272, 276–278, 294, 317, 324, 355, 439–441, 447 supercomputing cluster, 329
476 INDEX supply voltage, 2–3, 11–12, 22, 62, 78, 130, 145, 423 surface, 5–6, 8, 18, 20, 21, 36–37, 44–45, 48, 50, 73, 75–76, 78–80, 83–85, 92, 95, 97, 101, 103–104, 106, 108, 116, 119, 141–142, 144, 146, 166, 172, 261–262, 264, 270–271, 274, 285, 306, 312, 319, 324, 329–355, 359, 363–368, 370–371, 376, 379, 381, 402, 432, 441, 446 surface conduction, 83, 106 surface nonidealities, 80 surface potential, 8, 20–21, 44–45, 73, 75, 92, 104, 146, 172, 306, 319, 329–334, 336, 338–345, 347–348, 350–355, 363–368, 370–371, 379, 381 surface potential model, 172, 329, 333, 345, 348, 350–351 surface recombination, 268, 270 surface roughness, 83–85, 116, 119, 166, 402, 432 surface scattering, 50, 79–80, 84, 270, 300, 446 suspended nanowire growth, 49, 51 Svisual, 388, 397, 403, 406, 413–414 switching probability, 3 symmetric, 31, 39, 41–43, 83, 104, 112–113, 165–167, 171, 227, 244, 268–269, 333–334, 338, 343, 349, 351, 379, 382–384 symmetric lattice, 42 symmetrically doped, 16, 195, 286 tail of the Fermi–Dirac distribution, 30 tantalum, 284 TAT (trap-assisted tunneling), 34, 51 Taylor series, 357 T-BTBT (transverse BTBT), 18, 50, 173, 177, 192, 195, 308, 423 TCAD (technology computer aided design), 61, 279, 327, 340, 344, 354–355, 359, 361, 365, 374, 385–392, 394–396, 398, 400, 402, 404, 406–410, 412, 414, 416, 418–420, 422, 424, 426, 428, 430, 432, 434, 436, 438, 451, 453 TCAD simulation, 361, 407, 436 TD (tunnel dielectric), 243–248 TD thickness, 246–247 TDDB (time dependent dielectric breakdown), 248 TDR, 387–388, 390, 397, 401, 403–406, 417, 419, 420, 432–433 TDR file, 387–388, 390, 397, 401, 403–405, 417, 419, 432–433 technological challenge, 31, 33, 44, 48, 51, 144, 152, 203, 219, 236–237, 247–248, 443 technology roadmap, 106 TEM (transmission electron microscope), 81–82, 407, 446 temperature dependence, 82, 89–92, 125, 402 temperature fluctuations, 90 temperature variations, 92 tensile strain, 88 TFET (tunnel FET), 24, 27–35, 38, 41, 57–60, 68, 82, 107, 111, 172, 254, 287, 290–296, 317–319, 32–325, 381, 421, 438, 440–441, 454 TGJLFETs (triple gate JLFETs), 148, 152 theoretical foundations, 328 theoretical modeling, 328 thermal annealing, 17–18, 31 thermal budget, 23, 68, 82, 101, 238, 281, 287–289, 291–292, 310, 314–315, 319, 439, 446–447 thermal energy, 84, 90, 93 thermal stability, 449 thermal voltage, 76, 285, 329, 344 thermally assisted lateral diffusion, 22, 67 thermionic emission, 22, 27, 310, 316 thermionic injection, 20, 34, 44–45, 294, 317 thermodynamic processes, 329 three-dimensional (3D) integration, 446 threshold voltage, 6–9, 11, 14–15, 20, 23–24, 38, 45–46, 50, 58, 72–76, 79–80, 83, 87, 90–92, 94–95, 97–99, 101, 104–106, 108–109, 112–113, 118, 123, 126, 128, 145, 147–148, 150–151, 160–161, 166–167, 179, 182, 184, 187, 214–216, 250, 257–258, 261–263, 266, 281, 291, 294, 297–298, 302, 320, 324, 329, 338, 355–357, 365, 369–371, 374, 378–379, 381–383, 409, 435–436, 442–444, 446–447
INDEX 477 threshold voltage roll-off, 14, 50, 97–98, 365, 371 thru-silicon via (TSV), 449 Ti/TiN barrier layer, 449 tilt angle evaporation and lithography, 157 time-dependent dielectric breakdown, 248 time-independent perturbation theory, 376 TiN (titanium nitride), 25, 65, 81, 107–108, 250, 449, 450 top-bottom approach, 51, 152, 230 top-down approach, 49 trade-off, 57, 156, 203, 219, 310 transcendental, 339 transconductance, 79, 92–94, 102, 157–158, 160–161, 218 transconductance oscillations, 93 transfer characteristics, 7–9, 29, 38, 41, 45–46, 53–55, 82, 90, 105, 131, 135–137, 141, 145, 149, 154, 158, 161, 180–187, 189–191, 202–203, 205–209, 212, 214, 216–217, 221, 227–228, 231, 235–236, 238–239, 244, 274, 290, 292, 294–295, 298, 301–304, 306, 316–317, 355, 379, 385, 404–407, 432, 434–435, 442 transient response, 40, 234 transient simulations, 234 transistor, 1–3, 7, 11–13, 15, 23–27, 29, 39, 58–65, 68, 80–81, 102, 104, 110–115, 117–123, 125–126, 128, 162–173, 175, 178, 191–192, 205, 230, 243, 249–255, 265–267, 273, 276–279, 281–282, 287, 320–325, 327, 329, 333, 340, 380–385, 389, 436–439, 443, 447, 449, 451–456 transition metal dichalcogenide (TMD), 47 transmission probability, 16 transport effective mass, 329 transverse electric field, 264–265 transverse tunneling, 177 trap density, 135, 207–208, 407 trap generation, 48 trap-induced mobility degradation, 50 traps, 34, 38, 44, 50, 64, 79–80, 88, 90, 95–97, 101, 103–104, 125, 134–136, 164, 206–208, 212, 248, 252, 329, 409, 435, 439 triangular potential well, 373 trigate, 71–72, 91, 112, 114, 122, 144, 162, 168, 171, 249–250, 320, 333, 383 triode region, 358 tubular, 52 tungsten, 449 tungsten titanium alloy, 284 tunnel gate, 214–216 tunneling, 15, 17–19, 25, 27–34, 38, 50, 56, 58–60, 64–65, 68, 85–86, 93, 101–102, 107, 110–111, 115, 123, 125, 128, 151, 162–164, 171–174, 177–179, 182–185, 187, 189, 191–195, 197–200, 202, 205–207, 211–212, 214, 216–218, 222, 224, 228–229, 232, 235–236, 239–240, 242–243, 245–247, 249–255, 277, 289–296, 304–306, 308–312, 314, 316–319, 322–324, 379–381, 389–390, 396, 402, 406, 409, 413, 416, 418–423, 432–433, 437–438, 440, 444–446, 449, 451, 454 tunneling CNFETs, 195 tunneling distance, 31, 34, 85, 291, 318 tunneling efficiency, 28, 30–31, 290–291, 293 tunneling length, 28, 30, 33 tunneling mass, 420–421, 433 tunneling probability, 19, 28, 32–33, 182, 192, 194, 198, 200, 235, 310, 318, 422 tunneling width, 18, 32–34, 60, 115, 128, 164, 182–183, 187, 189, 192–195, 199–200, 202, 205–207, 211–212, 214, 216–218, 222, 224, 232, 239–240, 242–243, 245, 247, 252, 277, 304, 310, 312, 314, 323, 380, 438, 451 tunneling window, 30 turn-OFF characteristics, 40, 46, 218 turn-ON, 46 twin well process, 137 two-dimensional (2D) materials, 27 two-dimensional electron gas, 102 UDP (uniform doping profile), 103, 141–143, 145, 395 ultimate scaling, 48–49, 57, 80, 149, 190, 243, 422 ultrafast annealing systems, 23, 68 ultrascaled, 203, 241
478 INDEX ultrasharp doping profile, 27 ultrashort-channel, 14, 19, 177 ultrasteep doping profile, 22–23, 31, 53, 57, 67–68, 82, 128, 148, 281, 440, 446, 449 ultrathin body, 108–109, 121, 268, 320, 379, 438 ultrathin film, 203, 329 undepleted, 14, 71, 76–77, 139, 141–142, 184, 256, 337 underlap length, 233–234 undoped channel, 84, 104, 281 undoped core, 226 undoped silicon, 303 ungated intrinsic region, 35–36 uniaxial compressive stress, 88 uniaxial tensile stress, 88 uniform composition, 107 uniform doping, 103, 141, 146, 148, 153, 395, 449 uniformly doped, 80, 137, 145 unipolar operation, 263 unity transmission coefficient, 85–86 universal Schottky tunneling model, 310 unlabeled biomolecules, 441 valence band, 17, 18, 28–30, 32–35, 50, 56, 100–102, 109, 151, 173, 180, 182, 184, 192, 198, 205, 235, 245, 292, 302, 308–309, 317, 406, 417, 419 valley edge shifts, 186 valleys, 186–187, 378 vapor–liquid–solid (VLS) growth, 49 velocity saturation, 417, 432 vertical metallurgical junction, 137 vertical NWFETs, 49 vertical stacking, 50–52, 449 vertical tunneling, 50, 192 vertically stacked NWMOSFET, 428 virtual source/drain regions, 446 voltage amplification, 45 voltage-controlled measurements, 275, 444 voltage-transfer characteristics, 53 volume accumulation, 300 volume conduction, 89, 100–101, 111, 125 volume depletion, 71, 80, 97, 101, 103, 109, 128, 131–132, 137, 139–142, 144, 173, 184–185, 187, 210, 222, 227, 262, 298, 348, 440, 447 volume inversion, 50, 53–54 wafer, 80–81, 121, 130, 143, 148, 152, 199, 206, 236–237, 449–450 wafer–wafer dielectric bonding, 449 wave function, 16, 183, 187, 302–303, 329, 372, 376 wave nature of electrons, 16 weak accumulation, 84–85, 344, 348 weak inversion, 359 weak linear dependence, 233 web plot digitizer, 410 Wentzel–Kramers–Brillouin (WKB), 30, 418, 422 wired chip network, 3 work function, 34, 70–71, 73, 107–109, 123, 126, 130–134, 155, 157, 160–161, 171–173, 205, 212, 214–216, 262, 264, 282–285, 287, 289, 294, 298, 302–306, 309–310, 320, 355, 402–403, 423, 432, 435 work function difference, 70, 73, 161, 215, 216, 282 WSe2, 47 WTe2, 47 XOR, 315 Y-method, 86–87 zero depletion region width, 77 zero gate oxide coefficient, 264 zero-temperature coefficient (ZTC), 90–92 zirconium, 284 zirconium-doped hafnium oxide, 44
BOOKS IN THE IEEE PRESS SERIES ON MICROELECTRONIC SYSTEMS The focus of the series is on all aspects of solid-state circuits and systems including: the design, testing, and application of circuits and subsystems, as well as closely related topics in device technology and circuit theory. The series also focuses on scientific, technical and industrial applications, in addition to other activities that contribute to the moving the area of microelectronics forward. R. Jacob Baker, Series Editor 1. CMOS: Circuit Design, Layout, and Simulation R. Jacob Baker, Harry W. Li, and David E. Boyce 2. Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices William D. Brown and Joe E. Brewer 3. Advanced Electronic Packaging: With Emphasis on MultiChip Modules William D. Brown 4. Low-Voltage/Low-Power Integrated Circuits and Systems: Low-Voltage Mixed-Signal Circuits Edgar Sanchez-Sinencio and Andreas G. Andreou 5. High-Performance System Design: Circuits and Logic Vojin G Oklobdzija 6. Hardware Description Languages: Concepts and Principles Sumit Ghosh 7. CMOS: Circuit Design, Layout, and Simulation, Second Edition R. Jacob Baker 8. Advanced Electronic Packaging, Second Edition William D. Brown and Richard K. Ulrich 9. DRAM Circuit Design: Fundamental and High-Speed Topics Brent Keeth, R. Jacob Baker, Brian Johnson, and Feng Lin 10. Nonvolatile Memory Technologies with Emphasis on Flash: A Comprehensive Guide to Understanding and Using NVM Devices Joseph E. Brewer and Manzur Gill 11. CMOS: Mixed-Signal Circuit Design, Second Edition R. Jacob Baker 12. Reliability Wearout Mechanisms in Advanced CMOS Technologies Alvin W. Strong, Ernest Y. Wu, Rolf-Peter Vollertsen, Jordi Sune, Giuseppe La Rosa, Timothy D. Sullivan, and Stewart Rauch, III 13. CMOS: Circuit Design, Layout, and Simulation, Third Edition R. Jacob Baker 14. Quantum Mechanics for Electrical Engineers Dennis M. Sullivan
15. Nanometer Frequency Synthesis beyond Phase-Locked Loop: A New Frontier in Electronic Design Liming Xiu 16. Electrical, Electronics and Digital Hardware Essentials for Scientists and Engineers Ed Lipiansky 17. Enhanced Phase-Locked Loop Structures for Power and Energy Applications Masoud Karimi-Ghartemani 18. From Frequency To Time-Average-Frequency: A Paradigm Shift in the Design of Electronic System Liming Xiu 19. NAND Flash Memory Technologies Seiichi Aritome 20. Understanding Delta-Sigma Data Converters, Second Edition Shanthi Pavan, Richard Schreier, and Gabor C. Temes 21. Junctionless Field-Effect Transistors: Design, Modeling, and Simulation Shubham Sahay and Mamidala J. Kumar
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