SLIDE PRESENTATION MATH (SARAH,ALAINA,PUTERI,AIMAN) (2)

ELECTRICAL ENGINEERING DEPARTMENT
ACADEMIC SESSION: 1 2021/2022

DEE20033 – DIGITAL ELECTRONICS

PRACTICAL WORK 4 : FLIP-FLOPS: JK FLIP-FLOPS WITH PRESET AND CLEAR

PRACTICAL WORK DATE : 16 NOVEMBER 2021
LECTURER’S NAME:
PUAN SITI HAJAR BT. ABDUL HAMID

GROUP NO.:

DATE SUBMIT: 16 NOVEMBER 2021

STUDENT ID & NAME : REPORT PRAC. TOTAL
(20%) SKILL MARKS
(80%) (100%)

(1) SITI SARAH BINTI KAMARUL BAHAROM

(2) SITI NUR ANTASHA ALAINA BINTI JEFRI

(3)

REPORT MARK DISTRIBUTION 20%
(1) Result /Output (12)
(2) Function of input Preset and Clear (4)
(3) Conclusion (4)

ACTION NAME & DESIGNATION SIGNATURE EFFECTIVE
DATE
Prepared by: Siti Hajar Binti Abdul Hamid
Checked & approved by: Course Lecturer

Programme Leader

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PRACTICAL SKILL ASSESSMENT (PLO5/P4/CLS3a, 3c/CLO2)

Aspect Score Description Score
23 5
1 4

IC Selection & Student was Student was Student was Student was Student was x2
Identification unable to able to identify able to identify able to identify able to identify x5
identify and and select less and select more and select all and select all x5
Circuit select any IC than half of the than half but needed IC’s IC’s quickly
Construction IC needed less than three and without
Student failed to quarter of the IC Student was the help of the
Functional of construct the Student needed able to lecturer
Circuit circuits constructed the construct all
circuits Student was the circuits Student was
1 incorrectly able to construct correctly under able to
Circuit was not part of the supervision of construct all
circuits correctly the lecturer the circuits
working under excellently
supervision of without the
the lecturer help of the
lecturer

2 3

Circuit was partly operational Circuit was fully operational

Trouble Student was Student Student was Student was Student was x4
Shooting unable to performed the able to perform able to able to do x2
perform any troubleshooting part of the troubleshoot troubleshootin 20
Demostration troubleshooting incorrectly troubleshooting the circuit with g without the
correctly the help of the help of the
Student did not Student only lecturer lecturer
demonstrate demonstrated Student Student
proper safety some safety demonstrated Student demonstrated
practices practices some safety demonstrated proper safety
practices after proper safety practices most
he/she was practices most of the times and
reminded by the of the times ensured they
lecturer were practiced
by others in the
group

Result

Total 100

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GENERIC SKILL ASSESSMENT (PLO9/A3/CLS3d/CLO3)

CLO3: Demonstrate ability to work in team to complete assigned task during practical work sessions

Attribute Sub- Score Description Score
Attribute 23 5
1 4

No clear Able to foster Able to foster Able to High ability to
evidence of relationship foster good
ability to and work relationship foster good relationship
Foster foster good together with and work
good relationships other group and work relationship together
relationship and work members effectively
together towards goal together with and work with other
effectively achievement group
with other but with other group together members x2
group limited effect towards goal
members and require members with other achievement
towards goal improvements
achievement towards goal group
.
achievement members

with some towards goal

effect(s) and achievement

require minor

improvements

No clear Attempt to Able to Able to Show clear
evidence of
ability to demonstrate demonstrate demonstrate evidence to
assume
alternate in practice in practice the in practice assume
roles as a
Teamwork Alternate group leader the ability to ability to the ability to alternate roles
roles and group
members alternate roles assume assume as a group x2
demonstrated
in practice as a group alternate roles alternate leader and a

leader and as a group roles as a group

group leader and group leader member

members but group and a group demonstrated

with limited members with member to in practice

effect and some effect(s) achieve the

require and require same goal

improvements minor

improvements

Respect Not able to Limited Able to Able to well Able to x2
and respect and respect and respect and very well 30
accept respect and accept accept respect
accept opinion of opinion of opinion of and accept
opinion others that acceptance others in others in opinion of
leads to of others’ achieving achieving others in
conflicts group’s group’s achieving
opinions in objectives objectives group’s
objectives
achievement
group’s TOTAL

objectives

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PRACTICAL FLIP-FLOPS: JK FLIP-FLOPS WITH PRESET AND CLEAR
WORK 4

1 COURSE LEARNING OUTCOMES
CLO2: Construct the logic diagrams, truth tables and timing diagrams using logic gates and
flip-flop
CLO3: Demonstrate ability to work in team to complete assigned task during practical work
sessions

2 OBJECTIVES

i. To construct JK Flip-flop by using IC 7476.
ii. To know the function of PRESET and CLEAR inputs.

3 THEORY

The J-K flip-flop is a versatile and widely used type of flip-flop. It is important to note that the
J-K flip-flop has no invalid state as does the S-R flip-flop. For this combination, the FF will
always go to its opposite state upon the positive transition of the clock signal. This condition
is called the ‘toggle’ mode of operation. Most integrated circuit flip–flops also have
asynchronous inputs. These are inputs that affect the state of the flip–flop independent of the
clock. They normally labeled are preset (PRE) and clear (CLR).For active low inputs, when
PRESET = 0 and CLEAR = 1, PRESET is activated and Q is immediately set to 1 no matter
what conditions are present at the J,K and CLK inputs..If CLEAR = 0 and PRESET = 1.The
CLEAR is activated and Q is immediately cleared to 0 independent of the conditions on the
J, K and CLK inputs.

4 EQUIPMENT / TOOLS

1. Laptop / Computer
2. Internet

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5 PROCEDURES
JK Flip-Flop by using IC 7476

Figure 3.2

1.Work in team, open Logic.ly software.

Construct the circuit as in Figure 3.2
2. Then, connect the J, K, PRE and CLR inputs to the binary switches, CLK to single-shot
clocks and connect Q and Q output to LED.
3. Set the JK, PRE, CLR and CLK switches to the values as in Table 3.1 and Table 3.2.
4. Record all the results into Table 3.1 and Table 3.2.

6 RESULT OUTPUT
INPUT (SYNCHRONOUS)
____ MODE OF
J K Preset Clear
(SW1) (SW2) (SW3) (SW4) CLK Qn+1 Qn+1 OPERATION
↑ 1
1 011 ↑ 1 0 Set
0 011 ↑ 0
1 111 ↑ 1 0 Hold
1 011 ↑ 0
0 111 ↑ 1 1 Toggle
1 011
0 Set

1 Reset

0 Set

Table 3.1

(6 marks)

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INPUT (ASYNCHRONOUS) OUTPUT

Preset Clear ____ MODE OF

(SW3) (SW4) J K CLK Qn+1 Qn+1 OPERATION
↑ 1
0 101 ↑ 0 0 Set
↑ 1
1 010 ↑ 0 1 Rest
↑ 1
0 101 ↑ 1 0 Set

1 010 1 Reset

0 101 0 Set

0 010 1 Disallowed

Table 3.2

(6 marks)

a) Define the function of input Preset and Clear in the JK flip flop aided with truth table.

(4 marks)

The PRESET and CLEAR inputs of the JK Flip-Flop are asynchronous, which means that
they will have an immediate effect on the Q and Q’ outputs regardless of the state of the
clock and / or the J and K inputs.
There are two very important additional inputs in the JK Flip-Flop.

PRESET input is used to directly put a “1” in the Q output on the JK Flip-Flop.
CLEAR input is used to directly put a “0” in the Q output on the JK.

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b) Give your conclusion pertaining to the experiment.

(4 marks)

1) We know how to construct the logic diagrams, truth tables and timing diagrams using
logic gates and flip-flop.

2) We know how to demonstrate ability to work in team to complete assigned task during
practical work sessions.

3) We know how to construct JK Flip-flop by using IC 7476.

4) We know how to the function of Preset and CLear inputs.

5) We know the meaning of Preset, Clear, and JK flip-flop.

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