438 PCI Architecture.ppt - Arizona State University

Basic Write

(PCI Local Bus S

Transaction

Specification, Revision 2.2)

25

PCI Optimizations and

 Push bus efficiency toward 10
 Bus parking

 retain bus grant for previous ma
 granted master can start next tr

 Arbitrary burst length

 initiator and target can exert flow
 discount with STOP (abort or re

GNT (by arbiter)

 Delayed (pended, split-phase)

 free the bus after request to slow

 Additional Features

 Interrupts: support for controlling
 Cache coherency: support for I/
 Locks: support timesharing, I/O,
 Configuration Address Space (p

d Additional Features

00% under common simple usage

aster until another makes request
ransfer without arbitration

w control with xRDY
etry, by target), FRAME (by master) and

) transactions

w device

g I/O devices
/O and multiprocessors
, and MPs
plug and play)

26

PCI Addre

 A PCI target can implem
types of address spaces

 Configuration space

 Stores basic information abo
 Allows the central resource o

operational settings

 I/O space

 – Used mainly with PC perip

 Memory space

 – Used for just about everyth

ess Space

ment up to three different

out the device
or O/S to program a device with

pherals and not much else
hing else

27

Accessing the A

acce
ins
and

memory acce
space (witho
(4GB)

i/o s
(64

i/o-ports 0x0CF8-0x0CFF dedicated to
(www.cs.usfca.edu/~cruse/

Address Spaces

essed using a large variety of processor
structions (mov, add, or, shr, push, etc.)
d virtual-to-physical address-translation

essed only by using the processor’s
special ‘in’ and ‘out’ instructions

out any translation of port-addresses)

space PCI
4KB) configuration

space
(16MB)

accessing PCI Configuration Space
/cs336s09/lesson19.ppt)

28

PCI Configuration

 Contains 256 bytes of ba

 addressable by 8-bit PCI bus
numbers for the device

 the first 64 bytes (00h – 3Fh)
configuration header, includin
device ID registers, to identif

 the remaining 192 bytes (40h
configuration space, such as
card for use by its accompan

 Also permits Plug-N-Play

 base address registers allow
dynamically into memory or I

 a programmable interrupt-lin
to program a PC card with an

n Address Space

asic device information,

s, 5-bit device, and 3-bit function

) make up the standard
ng PCI ID, i.e. vendor ID and
fy the device
h – FFh) represent user-definable
s the information specific to a PC
nying software driver

y

w an agent to be mapped
I/O space
ne setting allows a software driver
n IRQ upon power-up

29

Memory and

 Memory space is used by
it’s the general-purpose a

 The PCI spec recommends t
even if it is a peripheral

 An agent can request betwee
space. The PCI spec recomm
4kB of memory space, to red
address decoder

 IO space is where basic P
serial port, etc.) are mapp

 The PCI spec allows an agen
space

 For x86 systems, the maximu
ISA issues

d IO Spaces

y most everything else –
address space

that a device use memory space,

en 16 bytes and 2GB of memory
mends that an agent use at least
duce the width of the agent’s

PC peripherals (keyboard,
ped

nt to request 4 bytes to 2GB of I/O

um is 256 bytes because of legacy

30

PCI Com

 PCI allows the use of up
commands

 Configuration commands
 Memory commands
 I/O commands
 Special-purpose commands

 A command is presented
initiator during an addres
first assertion of FRAME#

mmands

to 16 different 4-bit

d on the C/BE# bus by the
ss phase (a transaction’s
#)

31

PCI Com

C/BE[3::0]# C
0000 Interr
0001
0010 S
0011
0100 M
0101 M
0110
0111 Con
1000 Con
1001 Mem
1010 Dua
1011 Mem
1100 Memory
1101
1110
1111

mmands

Command Type
rupt Acknowledge
Special Cycle
I/O Read
I/O Write
Reserved
Reserved
Memory Read
Memory Write
Reserved
Reserved
nfiguration Read
nfiguration Write

mory Read Multiple
al Address Cycle
mory Read Line
y Write and Invalidate

32

The Plug-and-

 Allows add-in cards to be
without changing jumper

 Address mapping, IRQs, CO
dynamically at system start-u

 For PNP to work, add-in c
information for the BIOS

 Type of card and device
 Memory-space requirements
 Interrupt requirements

-Play Concept

e plugged into any slot
rs or switches

OM ports, etc., are assigned
up

cards must contain basic
and/or O/S, e.g.:

s

33

Configuration

 Are generated by a host
 Use a set of IDSEL signa

 Dedicated address decoding
 Each agent is given a unique

 Are typically single data

 Bursting is allowed, but is ve

 Two types (specified via

 Type 0: Configures agents o
 Type 1: Configures across P

n Transactions

or PCI-to-PCI bridge
als as chip selects

g
e IDSEL signal

phase

ery rarely used

a AD[1:0] in addr. phase)

on same bus segment
PCI-to-PCI bridges

34

Type 00h Configura

ation Space Header

(PCI Local Bus Specification, Revision 2.2)

35

Configuration

 Two DWORD I/O locations are
transactions

 0CF8h references a read/write r
 0CFCh references a read/write

 Bus enumeration

 attempting to read the Vendor- a
combination of bus number and
function #0

 knows a device exists, and can
and I/O port addresses for the d

n Commands

e used to generate configuration

register, CONFIG_ADDRESS.
register, CONFIG_DATA.

and Device ID register for each
d device number, at the device's

then program the memory mapped
device.

36

PCI Cha

 Limited Bandwidth

 PCI-X and Advanced Graphics P
 Reduction of distance

 Bandwidth shared between all
 Limited host pin-count
 Lack of support for real time d
 Stringent routing rules
 Lack of scaling with frequency
 Absence of power manageme
 PCI-X -- an enhancement of th

higher bandwidth demand.

 a double-wide version of PCI, ru
speed

allenges

Port (AGP) for higher frequency

l devices
data transfer
y and voltage
ent
he 32-bit PCI Local Bus for a

unning at up to four times the clock

37

Inter-Networking

 Multimedia applications drive
processing of data over wired

 CPU performance doubles abo
Bus performance doubles abo

10000

1000

Relative Bandwidth 100 25-33 40

10 12 16-20 E
8
0 8b ISA 16b ISA M
4.77
Source: Intel
1980 1985 199

g Driving Demand

the need for fast, efficient
d or wireless media
out every 18 months while PC
out every 3 years

10 Gbit
Ethernet

500-1000
Gbit
350-400
133-200 Ethernet

75-100 Fast Ethernet
PCI-X
0-50 66

EISA PCI 32/33PCI 64/66

MCA

90 1995 2000

38

PCI Expre

 Serial, point

Signaling

PCI Express  2.5GHz full d
Device 1
 PCIe Gen

 Scaleable lin

 Packet base

Ref  Software co
Clock
Lane Built-in Qua
 Virtual Ch

PCI Express  Traffic Cla
Device 2
 Reliability, A

 End-to-En

x4 Link Example  Poison Pa

 Native Ho

 Flow Contro

 Advance err

ess Basics

t-to-point, Low Voltage Differential

duplex lanes (2.5Gb/s)

n 2 = 5Gb/s

nks – x1, x4, x8, x16
ed transaction protocol

ompatible but with higher speeds

ality of Service provisions

hannels
asses

Availability and Serviceability

nd CRC (Cyclic redundant checking)
acket
ot Plug support

ol
ror reporting

39

PCI Express

Link Width X1 X2
5 10
Bandwidth in Gbits/s .5 1
(Tx and Rx) .25 .5
Throughput in GB/s
(Tx and Rx)
Throughput in GB/s
(per direction)

Raw: Assuming 100%
efficiency with no
payload overhead.

Performance

2 X4 X8 X12 X16 x32
0 20 40 60 80 160

2 4 6 8 16
12348

= PCI 32/66
= PCI or PCI-X 64/66
= PCI-X 64/133

40

PCIe L

 Layered architecture
 Application Data transferred

via packets

 Transaction Layer Packet
(TLP)

 PCIe core usually
implement the lower three
layers

 Protocol handling

 connection establishing
 link control
 flow control
 power management
 error detection and reporting

(http://w

Layers

www.cast-inc.com/company/events/shows/date06/cast_pcie-
ocp_slides.pdf)

41

PCIe TLP

PCI_SIG, “PCI Express Basics”, http://www.p

Structure

pcisig.com/developers/main/training_materials/

42

Example PCI Express To

PCI_SIG, “PCI Express Basics”, http://www.p

opology – Root & Switch

pcisig.com/developers/main/training_materials/

43

Transaction Types

 Request are translated to
types by the Transaction

 Memory Read or Memory W
to a memory mapped locatio

 also supports a locked mem

 I/O Read or I/O Write. Used
location

 restricted to supporting lega

 Configuration Read or Config
device capabilities, program
4KB PCI Express configurati

 Messages. Handled like pos
signaling and general purpos

s, Address Spaces

o one of four transaction
n Layer:

Write. Used to transfer data from or
on

mory read transaction variant.

to transfer data from or to an I/O

acy endpoint devices.

guration Write – Used to discover
features, and check status in the
ion space.
sted writes. Used for event
se messaging.

44

Transaction Lay

PCI_SIG, “PCI Express Basics”, http://www.p

yer Packet Types

pcisig.com/developers/main/training_materials/

45

Example TLP Reque

 Memory transaction (32 b

 Configuration transaction

est Header Formats

bits address)

n

46

Programmed I/

PCI_SIG, “PCI Express Basics”, http://www.p

/O Transaction

pcisig.com/developers/main/training_materials/

47

Incoming

(http://www.cast-inc.com/company/events/sh

 Incoming requests perform loc
 Some incoming requests requ
 Completion TLP rules

 Must form completion packets w
Completion Boundary

 Must correctly encode fields in c
 Completion address in packet di

 Application must correctly rep
to the core

Requests

hows/date06/cast_pcie-ocp_slides.pdf)

cal subsystem read or write
uire sending completion TLP

with respect to Max_Payload and Read
completion TLP
iffers (I/O x Memory)

port a request processing problem

48

Outgoing

(http://www.cast-inc.com/company/events/sh

 Outgoing Requests are generated b
 There is a set of rules for forming o

 Must be identified by unique Tag
 Read requests restricted by Max_Read_Re
 Write requests restricted by Max_Payload
 Must not cross 4kB address boundary

 Violations will result in request bei
 Completion request processing

 Completions for multiple outstanding reque
 Must have correct values in lower addresse
 Must process both Unsupported Reques

Requests

hows/date06/cast_pcie-ocp_slides.pdf)

by the application
outgoing request TLP

equest_Size
d

ing discarded and error detected

ests must be processed by Tag
es to process multiple TLPs
st and Completer Abort responses

49