EEM336 week07 paralel handshake - Anadolu Universitesi

Paralel I/O Ports

Polling, Handshake, PIOC

Week 7: Parallel I/O Handshaking 1

Introduction

• In most µP applications, the µP must communicate 2
with a variety of peripheral I/O devices

• This information transferred can generally be
classified as either data or control

• The data is usually encoded in some suitable coding
system, e.g binary, BCD, ASCII, etc.

• Control information may be commands from the µP,
requests for service from peripheral devices, control
codes from the µP or status codes from I/O devices

• This communication between the µP and I/O devices
is a critical component of the overall system design

Week 7: Parallel I/O Handshaking

Peripheral Devices

• Pieces of equipment that exchange data
with a computer.

• Examples include switches, light-emitting
diodes, cathode-ray tube screens, printers,
modems, keyboards, and disk drives.

Week 7: Parallel I/O Handshaking 3

Interface Chip

• A chip whose function is to synchronize data transfer
between the CPU and I/O devices.

• An interface may consist of control registers, status
registers, data direction latches, and control circuitry.

• An interface chip has pins that are connected to the
CPU and I/O port pins that are connected to the I/O
devices.

• Each interface chip has a chip enable signal input or
inputs, when asserted, allow the interface chip to react
to the data transfer request.

• Data transfer between an I/O device and the CPU can
be proceeded bit-by-bit or in multiple bits.

Week 7: Parallel I/O Handshaking 4

Typical Computer with RAM, ROM, I/O Ports

ADDRESS BUS Address From input To output
Decoder device device

CE CE CE CE
RAM ROM
RW Interface Interface
Chip 1 Chip 2

68HC11

DATA BUS

Week 7: Parallel I/O Handshaking 5

I/O Scheme

1. Isolated I/O scheme (Intel)

– The microprocessor has dedicated instructions for I/O
operations

– The microprocessor has a separate address space for
I/O devices

2. Memory-mapped I/O scheme (Motorola)

– The microprocessor uses the same instruction set for
I/O operations

– The I/O devices and memory components are resident
in the same memory space

Week 7: Parallel I/O Handshaking 6

I/O Transfer Synchronization

The role of an interface chip

1. Synchronizing data transfer between CPU and interface
chip.

2. Synchronizing data transfer between interface chip and I/O
device.

control Interface handshake I/O
signals Chip or strobe
signal Device
(such as R/W) Electronics
68HC11

DATA BUS

Week 7: Parallel I/O Handshaking 7

Handshaking

• The term I/O refers to the transmission of data from
one device to another, usually the source is referred to
as the sender and the destination the receiver

• Information will not necessarily only flow in this one
direction, however, often control information will flow
in both directions for handshaking

• Handshaking is used to coordinate the I/O process; e.g.
a DAV (data available) signal might be sent initially to
inform an output device that data are available, once
the output device has accepted the data it would then
send a DACK (data acknowledge) signal to inform the
sender that it has done so

Week 7: Parallel I/O Handshaking 8

Synchronizing the Microprocessor and the
Interface Chip

POLLING METHOD INTERRUPT METHOD

For input: the microprocessor checks a For input: the interface chip interrupts
status bit of the interface chip to find out the microprocessor whenever it has
if the interface chip has received new received new data from the input
data from the input device. device.

For output: the microprocessor checks a For output: the interface chip
status bit of the interface chip to find out interrupts the microprocessor
if it can send new data to the interface whenever it can accept new data from
chip. the microprocessor.

Week 7: Parallel I/O Handshaking 9

Polling vs Interrupt

If you want to buy bread from the store,
and the store has run out of bread at
that time. What do you do?

You go to the store time to time and You get the store manager to call you
check if the bread has arrived. If so buy whenever bread has arrived and you go
it. If not go home and stop by the store home. Do you own business until a call

some time later for checking..... from the store manager comes.

POLLING INTERRUPT

Week 7: Parallel I/O Handshaking 10

Synchronizing the Interface Chip
and the I/O Devices

• Brute Force I/O Method: useful when the
data timing is not important

– For input : nothing special is done. The
microprocessor reads the interface chip and the
interface chip returns the voltage levels on the
input port pins to the microprocessor.

– For output : nothing special is done. The
interface chip places the data that it received
from the microprocessor directly on the output
port pins.

Week 7: Parallel I/O Handshaking 11

µP Initiated Unconditional I/O
Transfer

• For this type of transfer it is assumed that the input or
output devices are always ready to send data to or to
accept data from the µP

• As such no control signals need to be exchanged, data
are simply written to the output device or read from
the input device

• An example of such a device is a simple LED display
where eight LEDs are connected to an output port,
any data bytes sent from the µP to the port will then
immediately appear on the bank of LEDs

Week 7: Parallel I/O Handshaking 12

Synchronizing the Interface Chip
and the I/O Devices

• The strobed I/O method : a strobe signal is
used to indicate that data are stable on I/O
port pins

– for input : the interface chip latches the data into
its data register using the strobe signal.

– for output : the interface chip places the data on
port pins that it received from the
microprocessor and asserts the strobe signal.
The output device latches the data using the
strobe signal.

Week 7: Parallel I/O Handshaking 13

µP Initiated Conditional (Polled)
I/O Transfer

• For this type of transfer the µP must determine
whether the peripheral device is ready for
communication before the actual transfer takes place

• This type of I/O is often called polled I/O because the
device must be polled continually to check whether it
is ready for data transfer

• In this case some handshaking between the µP and the
I/O device is required, the control signals needed for
this handshaking will depend on the device involved
The flowchart on the next slide illustrates the steps
involved

Week 7: Parallel I/O Handshaking 14

µP Initiated Conditional (Polled) I/O Transfer

Read Device
Status

WAIT LOOP

Device Ready no
for Transfer?

yes

Perform Data
Transfer

Continue 15
Program

Week 7: Parallel I/O Handshaking

Interfacing an ADC to a µP

• In a typical application an analogue voltage
generated by a process transducer will be input
to an A/D converter and the output of this
converter loaded into a µP on demand

• The operation requires several communication
steps between the µP and the ADC.

Week 7: Parallel I/O Handshaking 16

Interfacing an ADC to a µP

1. The µP issues a START 68HC11 8bits START
pulse to the ADC to EOC
initiate the conversion of
its current analogue input ADC

2. The µP must then OUT
continually read and test
the status of the
converter’s EOC (End of
Conversion) output, which
goes LOW as soon as
conversion starts and
returns HIGH once the
conversion is complete

3. The µP can then read the
ADC output into one of its
registers

Week 7: Parallel I/O Handshaking 17

Interfacing an ADC to a µP

Generate START
pulse to ADC

Read EOC output START
from ADC EOC

68HC11 8bits ADC

no OUT

is EOC=1?

yes

Read Data from
ADC

Week 7: Parallel I/O Handshaking 18

µP Initiated Conditional (Polled) I/O Transfer

• This example should illustrate the major disadvantage
with polled I/O transfer – the µP has to wait for the
I/O device

• In some cases, especially for slow I/O devices, the µP
will waste a lot of its time reading and testing the
status of the I/O device

• If the µP is dedicated to this task this does not matter,
however, in many applications the µP could be
performing other tasks while waiting for the device to
become ready

• As we will see, this can be accomplished using an
interrupt scheme for such I/O transfers

Week 7: Parallel I/O Handshaking 19

Device Initiated I/O Transfer - Interrupts

• This type of I/O transfer makes more efficient use of
the µPs time because it does not have to check
repeatedly to see if the device is ready for transfer

• Instead the µP is free to perform other tasks and when
the I/O device is ready it will send a signal to one of
the µPs interrupt inputs

• At that point the µP will suspend execution of its
current program and perform a special interrupt
service routine (ISR), which typically contains
instructions to transfer data to or from the interrupting
device

• Once execution of the ISR is complete the µP will
resume execution of the interrupted program

Week 7: Parallel I/O Handshaking 20

Device Initiated I/O Transfer - Interrupts

2 $C000 1
Interrupt Occurs at
CPU saves its Main Program address $C102 (e.g.
state and jumps ADC sends EOC)

to ISR (to 4
address $C500) Once ISR is executed,
CPU resumes main
3 $C500 ISR
program (jumps to
ISR performs $C103) as f nothing
the data
transfer has happened.

Week 7: Parallel I/O Handshaking 21

Device Initiated I/O Transfer - Interrupts

• Interrupt operation is particularly useful in
applications where the µP must interface with several
I/O devices whose needs for servicing are
asynchronous

• The µP cannot predict when such devices will be
ready to send or receive information and so
programmed unconditional I/O transfers cannot be
used

• Although the interrupt process appears fairly
straightforward, there are a number of considerations
that must be dealt with and we will now look at what
these are and how they can be accounted for

Week 7: Parallel I/O Handshaking 22

Device Initiated I/O Transfer - Interrupts

• Return Address

– The first consideration is, after executing the ISR how does
the µP know what address in the main program to branch
back to?

– This is an important question, since an interrupt can occur
at any time and there is no way of predicting what
instruction the µP will be processing at the time

– This problem is taken care of automatically in µPs by
temporarily storing the current contents of the program
counter before branching to the ISR

– In 68HC11 µPs the PC register is stored on the stack
together with IX, IY, ACCA, ACCB and CCR registers

– At the end of the ISR a return from interrupt instruction is
executed which retrieves these values back off the stack

Week 7: Parallel I/O Handshaking 23

Device Initiated I/O Transfer - Interrupts

• Disabling Interrupts

– What happens if an interrupt occurs while the µP is
executing a portion of a program that requires continuous
processing? (e.g. when it is in a timing loop or already
communicating with another I/O device)

– To account for this all µPs have some provision for
disabling interrupt operation under program control, this is
usually achieved using an interrupt mask (or enable) flag (I)

– If this flag is set high (for the mask flag) or low (for the
enable flag) then the µP will ignore any standard interrupt
requests (this is always done, for example, when µP systems
are reset)

– The standard interrupt signal, IRQ on the 68HC11 is called
a maskable interrupt request signal due to the fact that it can
be masked in this way

Week 7: Parallel I/O Handshaking 24

Device Initiated I/O Transfer - Interrupts

• Disabling Interrupts

– The program below illustrates how the SEI and CLI
instructions can be used to disable the effects of an
interrupt signal during the execution of a critical time
delay sequence:

Address Label Instruction Mnemonic Comments
C100 START 0F SEI Disable Interrupts
C101 86 C0 LDAA #$C0 load ACCA with count
C103 LOOP 4A DECA decrement loop counter
C104 26 FD BNE LOOP loop if ACCA<>0
C106 0E CLI Enable interrupts
C107 .... ....

Week 7: Parallel I/O Handshaking 25

Device Initiated I/O Transfer - Interrupts

• Types of Interrupt Inputs

– Most µPs, including the 68HC11 µP, actually include two
types of interrupt input – maskable (IRQ) and nonmaskable
(XIRQ)

– A maskable interrupt is the type we have just described,
whose occurrence is ignored if the interrupt mask flag is set
The operation of the nonmaskable interrupt signal is not
affected by this flag and thus, during normal operation, the
µP will always respond to it (it cannot be software disabled)

– Additionally this input has priority over the maskable
interrupt input, if both are activated simultaneously, the
nonmaskable interrupt will be serviced first Both interrupts
are, however, disabled when the µP is reset to ensure that no
interrupts occur until the system has initialised

Week 7: Parallel I/O Handshaking 26

Device Initiated I/O Transfer - Interrupts

• Example - Power Failure Interrupt

– An example of when the nonmaskable interrupt might be
used is for a power-failure shutdown routine

– Here a special circuit could be used to monitor the power
supply voltage and to generate a signal to the XIRQ input if it
ever drops below a certain level

– The µP will then immediately branch to the ISR, which
should contain instructions to store the contents of the µPs
internal registers and important RAM locations in non-
volatile memory locations (e.g. EEPROM or battery backed
up RAM)

– This process will take only a few microseconds and, thus, can
theoretically be completed before the power supply voltage
drops low enough to destroy the contents of the volatile
memory

Week 7: Parallel I/O Handshaking 27

Device Initiated I/O Transfer - Interrupts 28

• Interrupt Handshaking

– We will use our previous example of interfacing an ADC
to illustrate the handshaking that needs to occur for
interrupt driven I/O operations

– In this case the µP does not continually poll the EOC
output from the ADC to determine when conversion is
complete, instead the positive going transition of this
signal will be used to trigger the IRQ input on the µP

– Assuming the I flag is cleared to enable interrupts, the µP
will then branch to the ISR, at this stage it will
automatically set the I flag to ensure that it does not
respond to the same interrupt again

– In this case the ISR will read the ADC output into ACCA
(and may also execute instructions to process the data)

Week 7: Parallel I/O Handshaking

Device Initiated I/O Transfer - Interrupts

• Interrupt Handshaking

– The final instruction in the ISR will always be a return
from interrupt instruction, which will return the µP to the
program it was executing at the time the interrupt
occurred

– Along with certain other registers this instruction will
pull the CCR or flag register off the stack, thereby
clearing the I flag

– To ensure that the µP does not at that point respond to the
same interrupt again the IRQ input must be cleared
beforehand

– In some µPs this is carried out automatically but in others
(including the 68HC11) it may be necessary to include
appropriate instructions in the ISR to ensure that this is
done

Week 7: Parallel I/O Handshaking 29

Device Initiated I/O Transfer - Interrupts

• Interrupt Vectors

– When an interrupt occurs, how does the µP know what
address to branch to for the ISR?

– The answer to this may vary somewhat depending on the
µP but in general, when an interrupt occurs, the µP will
obtain an interrupt vector from a fixed location in memory

– This will be loaded into the program counter as the address
of the first instruction in the ISR

– The 68HC11, for example, has more than 20 different
vectors stored in ROM that are used by different systems
of the µP, in particular the last 14 bytes of ROM are used
to some of these vectors as illustrated on the next slide

Week 7: Parallel I/O Handshaking 30

68HC11 Interrupt Vectors

Address Content Interrupt Name
IRQ
FFF2 C8 XIRQ
FFF3 00 SWI
FFF4 C5
FFF5 A0 Illegal Opcode
FFF6 E0 COP
FFF7 00
FFF8 --- Clock Monitor Fail
FFF9 --- RESET
FFFA ---
FFFB ---
FFFC ---
FFFD ---
FFFE C0
FFFF 00

Week 7: Parallel I/O Handshaking 31

68HC11 Interrupt Vectors

• For example, when the system is reset (by driving the RESET
input LOW), the µP automatically looks up the contents of
ROM locations FFFFh and FFFEh and loads the values stored
in them into the program counter (C000 in the example shown)

• Similarly, whenever the IRQ input is activated, assuming I is
0, the µP will automatically transfer the contents of FFF2h and
FFF3h into the program counter (after first saving its current
contents and the other registers to the stack)

• The SWI vector is utilized by the 68HC11 for the handling of
software interrupts, which result from the execution of a
specific instruction, SWI, that causes the µP to respond exactly
as if an externally generated interrupt had occurred

• Note: The SWI interrupt is not masked by either the I or X
flags

Week 7: Parallel I/O Handshaking 32

Can an Interrupt Service Routine be Interrupted?

• Interrupting an ISR

– When a 68HC11 µP is in the process of servicing
an interrupt resulting from a signal on its IRQ
input the I flag is automatically set to prevent
further response to that input

– Signals on the XIRQ input, however, will cause an
interrupt regardless of the state of the I flag (note
that while XIRQ interrupts are being serviced the
X flag is set to prevent further responses from the
same signal)

Week 7: Parallel I/O Handshaking 33

Can an Interrupt Service Routine be Interrupted?

• This is not a problem, however, as a result of the way
interrupts are handled by the system

• As we have seen, whenever an interrupt service is
invoked the current PC address is placed onto the
stack (along with certain other register values),
which means that the µP can always be returned back
to the same point to continue servicing the original
interrupt at a later stage

• On the 68HC11 all registers are backed up to the
stack after an interrupt call such that when the µP
returns to the original service routine it is as if
nothing has changed

Week 7: Parallel I/O Handshaking 34

Device Initiated I/O Transfer - Interrupts

• If a µP has only one or two interrupt input pins,
how can it service multiple I/O devices?

I/O Device 1 I/O Device 2 I/O Device 3
+5V

IRQ ENABLE ENABLE ENABLE
PORT C
Only one I/O device
Week 7: Parallel I/O Handshaking will access Port C
lines since only one
ENABLE line of a
device will be active

35

Synchronizing the Interface Chip
and the I/O Devices

• The handshake I/O method : used when
timing is crucial

– Two handshake signals are used to synchronize
the data transfer. One signal, call it H1, is
asserted by the interface chip. The other signal,
call it H2, is asserted by the I/O device.

– Two handshake modes are available : pulse
mode and interlocked mode.

Week 7: Parallel I/O Handshaking 36

Device Initiated I/O Transfer - Interrupts

• Multiple Interrupts

– The simplest method of handling multiple interrupts is the
polled interrupt method, it is slow but requires little external
hardware

– In this method, whenever an interrupt occurs a general ISR is
invoked that performs a sequence of operations to poll the
status of each interrupt source in turn until it finds the device
that is waiting for an I/O transfer, at which point an
appropriate ISR for that device can be invoked

– Usually the order in which devices are polled is specifically
set up according to decreasing priority so that the highest
priority device will be serviced first if simultaneous interrupt
signals are generated from two or more devices

– In the configuration shown on the previous slide, how can the
I/O devices be polled to determine the source of an interrupt?

Week 7: Parallel I/O Handshaking 37

Device Initiated I/O Transfer - Interrupts

• Preprocessing Interrupts

– The 68HC11 µP includes a specific Wait for Interrupt
(WAI) instruction

– When this instruction is executed the µP places the PC, IX,
IY, ACCA, ACCB and CCR registers onto the stack and
then executes a redundant instruction repeatedly until an
interrupt is detected

– When an interrupt does occur the registers have already been
saved to the stack so the µP simply vectors straight to the
ISR saving approximately 12 clock cycles and, therefore,
shortening the response time to the interrupt signal

– This instruction can also be used when a mode of reduced
power

Week 7: Parallel I/O Handshaking 38

Input Handshake

• Step 1. The interface chip asserts (or pulses)
H1 to indicate its intention to input data.

• Step 2. The input device puts data on the
data port pins and also asserts (or pulses)
the handshake signal H2.

• Step 3. The interface chip latches the data
and de-asserts H1. After some delay, the
input device also de-asserts H2.

Week 7: Parallel I/O Handshaking 39

Interlocked I/O Mode (Input)

1. HC11 5. Interface Chip acquires 6. After some
asserts data and de asserts H1 time, input
(requests)
(i.e. I've received the data) device deasserts
H2

H1 Valid Data
Data
3. Input Device 4. and also asserts
H2 puts valid data H2 (i.e. data is on

2. data on the on the port the port)
port is
invalid

Week 7: Parallel I/O Handshaking 40

Pulse I/O Mode (Input)

1. HC11 4. After some time, input
asserts for a device deasserts H2

while indicating data is now
invalid

H1 Valid Data
Data

H2

2. Input Device 3. and also asserts
prepares data and puts H2 for a while (i.e.
valid data on the port data is on the port)

Week 7: Parallel I/O Handshaking 41

Output Handshake

• Step 1. The interface chip places data on the port
pins and asserts (or pulses) H1 to indicate that it
has valid data to be output.

• Step 2. The output device latches the data and
asserts (or pulses) H2 to acknowledge the receipt
of data.

• Step 3. The interface chip de-asserts H1 following
the assertion of H2. The output device then de-
asserts H2.

Week 7: Parallel I/O Handshaking 42

Interlocked I/O Mode (Output)

1. Interface 2. Interface Chip 4. Output device received
chip puts data asserts H1 (i.e. data data, so we deassert H1
is valid on the port) indicating data on the port is
on the port goning to be invalid shortly

H1 Valid Data

Data 5. Output is
complete. New data
H2
may come in.
3. Output device
asserts H2

indicating it's
received data

Week 7: Parallel I/O Handshaking 43

Pulse I/O Mode (Output)

2. Interface 5. Interface chip
Chip asserts removes data on
H1 for a while
the port.

H1 Valid Data
Data

H2

1. HC11 prepares 3. Output device 4. Output device
data and puts data indicates that it's orders the Interface
chip to remove data
on the port received data
on the port

Week 7: Parallel I/O Handshaking 44

68HC11 Paralel I/O (revisited)

• The 68HC11A8 has 40 I/O pins that are arranged
in five I/O ports.

• All I/O pins serve multiple functions.
• Ports A, B, and E with the exception of port A pin

7 are fixed-direction inputs or outputs.
• Ports C and D are bi-directional I/O pins under the

control of their associated data direction registers.
• Port C, port B, the STRA pin, and the STRB pin

are used for strobed and handshake parallel I/O, as
well as for general-purpose I/O.

Week 7: Parallel I/O Handshaking 45

Paralel I/O Control Register (PIOC)

All strobed mode I/O and handshake I/O are controlled by this register

STAF STAI CWOM HNDS OIN PLS EGA INVB PIOC
$1002

00000U 1 1 After
Reset

STAF: Strobe A Flag. This bit is set when OIN: Output/input handshake
a selected edge occurs on the STRA PLS: 0à input handshake
signal. EGA: 1à output handshake
INVB: Pulse/interlock handshake
STAI: Strobe A interrupt enable. When the 0: interlocked handshake
STRA and STAI flags are both 1, an 1à pulse handshake
interrupt request will be made to Active edge for STRA
the processor. 0à falling edge
1à rising edge
CWOM: Port C wired-or mode Invert STRB
0à port C pins are CMOS outputs 0à active low
1à port C pins are open-drained 1à active high

HNDS: Handshake/simple strobe mode select
0àsimple strobe mode
1à handshake mode

Week 7: Parallel I/O Handshaking 46

Strobe Input Port C

• Strobe mode I/O is selected when the bit 4 of the PIOC register is
set to 0 and port C becomes a strobe input port.

• The bit 1 of the PIOC register selects the active edge of the
STRA pin.

• The active edge of the STRA signal latches the values of the port
C pins into the PORTCL register.

• Reading the PORTC register returns the current values on the
port C pins.

• Reading the PORTCL register returns the contents of the latched
PORTCL. Then STAF flag is cleared.

• When enabled, the active edge of the STRA signal will generate
an interrupt to the 68HC11.

Week 7: Parallel I/O Handshaking 47

Strobe Input Port C (timing)

STRA

PORTC

Remember tIS tIH
STRA means
"data is on the tIS input setup time (60ns at 2Mhz clock)
tIH input hold time (100ns at 2Mhz clock)
port C"

Week 7: Parallel I/O Handshaking 48

Strobed Output Port B (Output Timing)

The strobe signal STRB is pulsed for two E clock cycles each
time there is a write to port B.

HC11 writes to PORTB

E tPWD
Data previous data
STRB new port data
tDEB

for 2 E cycles

tPWD peripheral data write delay time 49
tDEB E fall to STRB valid delay time

Week 7: Parallel I/O Handshaking

Port C Input Handshake Protocol

• STRA is a latch command asserted by an input device (active
edge is rising in the figure in the next slide).

• STRB is a ready output driven by the 68HC11 (active high in
the figure).

• When ready for accepting new data, the 68HC11 asserts (or
pulses) STRB pin.

• The input device places data on input port pins and asserts the
STRA signal. The active edge of STRA latches data into the
PORTCL register, sets the STAF flag in PIOC register and de-
asserts the STRB signal. The de-assertion of STRB inhibits
external device from strobing new data into port C.

• Not until the 68HC11 reads PORTCL, new data cannot be
applied on port C pins.

Week 7: Parallel I/O Handshaking 50

Port C Interlocked Input Handshake Protocol

READ
PORTCL

E "READY"
STRB
tDEB
STRA
PORTC tAES

tIH

tIS

tDEB E fall to STRB delay
tAES STRA asserted to E fall
tIS port C data setup time
tIH port C data hold time

Week 7: Parallel I/O Handshaking 51

Port C Interlocked Output Handshake Protocol

• STRA is an acknowledge input (driven by the external
device) STRB is a ready output (driven by the 68HC11)

• In this figure, the active edge of STRA is rising and the
active level of STRB is high.

• The 68HC11 writes data into PORTCL and then asserts
STRB to indicates there are valid data on port C pins

• The external device then asserts STRA to acknowledge
the receipt of data which will then cause STRB to be de-
asserted and the STAF flag to be set.

• After the de-assertion of STRB, STRA is also de-asserted.

Week 7: Parallel I/O Handshaking 52

Port C Interlocked Output Handshake Protocol

WRITE
PORTCL

E tPWD
PORTC
tDEB "READY"
STRB
tDEB

STRA tAES
Peripheral data write delay time, 150 ns max (at 2 MHz)
tPWD E fall to STRB delay 225 ns (at 2 MHz)
tDEB STRA asserted to E fall setup time 0 ns (at 2 MHz)
tAES

Week 7: Parallel I/O Handshaking 53

Example

• Connect a de-bounced switch to STRA, a
LED to PORTC pin 4.

• Draw a connection diagram for the button
and LED.

• Write an ISR routine to toggle the status of
LED when button is pressed. (i.e. if LED is
on and the button is pushed, LED becomes
off and vice versa.)

Week 7: Parallel I/O Handshaking 54

Solution

Week 7: Parallel I/O Handshaking 55