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2 Basic I/O and Its Applications •O os tcfebj file type – it is a special type that serve as an interface between the VHDL programs and the host

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Published by , 2017-03-25 00:30:09

EL 310 Basic I/O VHDL - Sabancı Üniversitesi

2 Basic I/O and Its Applications •O os tcfebj file type – it is a special type that serve as an interface between the VHDL programs and the host

Access

• The objects can be crea

– variable mod1ptr, mod2
value is null;

– mod1ptr := new MODULE;
– mod1ptr := new MODULE’(

• Access & misc.

– mod1ptr.size, mod1ptr.c
– deallocate(mod1ptr);
– mod1ptr := mod2ptr;
– type bitvec_ptr is acce
– variable bitvec1: bitve

bit_vector(“1001”);
– mod2ptr := new MODULE’(

no_inputs=>2, no_output

Types

ated dynamically

2ptr: ptr; -- default

(25, 10 ns, 4, 9);

critical_dly, etc.

ess bit_vector;
ec_ptr := new
(critical_dly=>10 ns,
ts=>3, size=>100);

76

Opera

• Logical operators

– not
– associative: and, or,
– non-associative: nand, n
– Example: A nand B nan

• Relational

– =, /=, <, <=, >, >=

– bit_vector(‘0’, ‘1’
bit_vector((‘1’, ‘0

– type MVL is (‘U’, ‘
MVL’(‘U’) < MVL’(‘Z

– “VHDL” < “VHDL92” is

ators

xor, xnor,
nor
nd C; -- illegal

=
’, ‘1’) <
0’, ‘1’) is true
‘0’, ‘1’, ‘Z’)
Z’) is true
s true

77

Opera

• Shift Operators

– sll, srl, sla, sra,

– Examples:
– “1001010” sll 2 is “0
– “1001010” srl 3 is “0
– “1001010” sla 2 is “0
– “1001010” sra 3 is “1
– “1001010” rol 2 is “0
– “1001010” ror 3 is “0
– “1001010” ror -5 is “
– “1001010” rol -4 is “

ators

, rol, ror

0101000”
0001001”
0101000”
1111001”
0101010”
0101001”
“0101010”
“0101001”

78

Opera

• Arithmetic

– +, -, &
– ‘0’ & ‘1’ is “01”
– ‘C’ & ‘A’ & ‘T’ is
– *, /, mod, rem
– A rem B = A – (A/B)
– A mod B = A – B*N –
– abs, **

ators

“CAT
)*B
–- for some integer N

79

Alia

• An alias declares an alte
part of a named item.

– It provides a convenient
have long names

– Example:
signal S: bit_vector

31 30 22

sign exponent

31 26 23

opcode reg base

ases

ernate names for all or

t shorthand for items that

r (31 downto 0);

0

mantissa

18 0

offset

80

Alia

• Examples:

– signal S: bit_vector (
– alias sign: bit is S(3
– alias exponent: bit_ve

downto 23);
– alias mantissa: bit_ve

S(22 downto 0);
– alias opcode: bit_vect

downto 27);
– alias reg: bit_vector(

downto 24);
– alias base: bit_vector

downto 19);
– alias offset: bit_vect

downto 0);

ases

(31 downto 0);
31);
ector(7 downto 0) is S(30
ector(22 downto 0) is
tor(0 to 4) is S(31
(2 downto 0) is S(26
r(4 downto 0) is S(23
tor(18 downto 0) is S(18

81


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