HT9170 DTMF Receiver - ece.usu.edu

HT9170
DTMF Receiver

Features · Tristate data output for mC interface
· 3.58MHz crystal or ceramic resonator
· Operating voltage: 2.5V~5.5V · 1633Hz can be inhibited by the INH pin
· Minimal external components · HT9170B: 18-pin DIP package
· No external filter is required
· Low standby current (on power down mode) HT9170D: 18-pin SOP package
· Excellent performance

General Description DTMF tone pairs into a 4-bit code output.

The HT9170 series are Dual Tone Multi Fre- Highly accurate switched capacitor filters are
quency (DTMF) receivers integrated with digi- employed to divide tone (DTMF) signals into
tal decoder and bandsplit filter functions. The low and high group signals. A built-in dial tone
HT9170B and HT9170D types supply rejection circuit is provided to eliminate the
power-down mode and inhibit mode operations. need for pre-filtering.
All types of the HT9170 series use digital count-
ing techniques to detect and decode all the 16

Selection Table

Function Operating OSC Tristate Power 1633Hz DV DVB Package
Inhibit
Part No. Voltage Frequency Data Output Down

HT9170B 2.5V~5.5V 3.58MHz Ö Ö Ö Ö ¾ 18 DIP

HT9170D 2.5V~5.5V 3.58MHz Ö Ö Ö Ö ¾ 18 SOP

1 December 20, 1999

HT9170

Block Diagram PW DN VREF R T /G T E S T D V D V B

X2 B ia s V re f S te e r in g C o n tr o l C ir c u it
3 .5 8 M H z C ir c u it G e n e ra to r

X 1 C ry s ta l
O s c illa to r

VP P r e - F ilte r L o w G ro u p F re q u e n c y C ode L a tc h D0
O PA F ilte r D e te c to r D e te c to r & D1
D2
VN H ig h G r o u p O u tp u t D3
F ilte r B u ffe r
GS

IN H O E

Pin Assignment

VP 1 18 VDD VP 1 18 VDD
VN 2 17 R T /G T VN 2 17 R T /G T
GS 3 16 EST GS 3 16 EST
VREF 4 15 DV VREF 4 15 DV
IN H 5 14 D3 IN H 5 14 D3
PW DN 6 13 D2 PW DN 6 13 D2
X1 7 12 D1 X1 7 12 D1
X2 8 11 D0 X2 8 11 D0
VSS 9 10 OE VSS 9 10 OE

H T9170B H T9170D
1 8 D IP 18 S O P

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HT9170

Pin Description

Pin Name I/O Internal Description
Connection

VP I OPERATIONAL Operational amplifier non-inverting input
AMPLIFIER

VN I Operational amplifier inverting input

GS O Operational amplifier output terminal

VREF O VREF Reference voltage output, normally VDD/2
X1
I The system oscillator consists of an inverter, a bias resistor
X2
O OSCILLATOR and the necessary load capacitor on chip.
A standard 3.579545MHz crystal connected to X1 and X2 ter-

minals implements the oscillator function.

PWDN I CMOS IN Active high. This enables the device to go into power down
Pull-low mode and inhibits the oscillator. This pin input is internally
pulled down.

INH I CMOS IN Logic high. This inhibits the detection of tones representing
Pull-low characters A, B, C and D. This pin input is internally pulled
down.

VSS ¾ ¾ Negative power supply

OE I CMOS IN D0~D3 output enable, high active
Pull-high

D0~D3 O CMOS OUT Receiving data output terminals
Tristate OE=²H²: Output enable
OE=²L²: High impedance

Data valid output
DV O CMOS OUT When the chip receives a valid tone (DTMF) signal, the DV

goes high; otherwise it remains low.

EST O CMOS OUT Early steering output (see Functional Description)

RT/GT I/O CMOS IN/OUT Tone acquisition time and release time can be set through
connection with external resistor and capacitor.

VDD ¾ ¾ Positive power supply, 2.5V~5.5V for normal operation

DVB One-shot type data valid output, normal high, when the chip
O CMOS OUT receives a valid time (DTMF) signal, the DVB goes low for

10ms.

3 December 20, 1999

Approximate internal connection circuits HT9170

O P E R A T IO N A L VREF O S C IL L A T O R C M O S IN CM OS OUT
A M P L IF IE R X1 X2 P u ll- h ig h T r is ta te
O PA
V N V- EN
V P VO+ P A
GS 20pF 10M

10pF

CM OS OUT C M O S IN /O U T C M O S IN
P u ll- lo w

Absolute Maximum Ratings Storage Temperature.................-50°C to 125°C
Operating Temperature ..............-20°C to 75°C
Supply Voltage.................................-0.3V to 6V
Input Voltage .................VSS-0.3V to VDD+0.3V

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-
mum Ratings² may cause substantial damage to the device. Functional operation of this device
at other conditions beyond those listed in the specification is not implied and prolonged expo-
sure to extreme conditions may affect device reliability.

D.C. Characteristics Ta=25°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

VDD Operating Voltage ¾ ¾ 2.5 5 5.5 V

IDD Operating Current 5V ¾ ¾ 3.0 7 mA

ISTB Standby Current 5V PWDN=5V ¾ 10 25 mA

VIL ²Low² Input Voltage 5V ¾ ¾ ¾ 1.0 V

VIH ²High² Input Voltage 5V ¾ 4.0 ¾ ¾ V

IIL ²Low² Input Current 5V VVP=VVN=0V ¾ ¾ 0.1 mA

IIH ²High² Input Current 5V VVP=VVN=5V ¾ ¾ 0.1 mA

ROE Pull-high Resistance (OE) 5V VOE=0V 60 100 150 kW

RIN Input Impedance (VN, VP) 5V ¾ ¾ 10 ¾ MW

4 December 20, 1999

HT9170

Symbol Parameter Test Conditions Min. Typ. Max. Unit
-0.4 -0.8 ¾ mA
VDD Conditions

IOH Source Current 5V VOUT=4.5V
IOL (D0~D3, EST, DV)
fOSC 5V VOUT=0.5V 1.0 2.5 ¾ mA
Sink Current
(D0~D3, EST, DV) 5V Crystal=3.5795MHz 3.5759 3.5795 3.5831 MHz

System Frequency

A.C. Characteristics fOSC=3.5795MHz, Ta=25°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

DTMF Signal

Input Signal Level 3V -36 ¾ -6
5V -29 ¾ dBm

1

Twist Accept Limit (Positive) 5V ¾ 10 ¾ dB

Twist Accept Limit (Negative) 5V ¾ 10 ¾ dB

Dial Tone Tolerance 5V ¾ 18 ¾ dB

Noise Tolerance 5V ¾ -12 ¾ dB

Third Tone Tolerance 5V ¾ -16 ¾ dB

Frequency Deviation 5V ¾ ¾ ±1.5 %
Acceptance

Frequency Deviation Rejection 5V ±3.5 ¾ ¾ %

Power Up Time (tPU) 5V ¾ 30 ¾ ms
(See Figure 4.)

Gain Setting Amplifier

RIN Input Resistance 5V ¾ ¾ 10 ¾ MW
IIN Input Leakage Current
VOS Offset Voltage 5V VSS<(VVP,VVN)<VDD ¾ 0.1 ¾ mA
PSRR Power Supply Rejection
CMRR Common Mode Rejection 5V ¾ ¾ ±25 ¾ mV
AVO Open Loop Gain
5V ¾ 60 ¾ dB
100 Hz ¾ 60 ¾ dB
¾ 65 ¾ dB
5V -3V<VIN<3V
5V

fT Gain Band Width 5V ¾ ¾ 1.5 ¾ MHz
VOUT Output Voltage Swing 5V RL>100kW ¾ 4.5 ¾ VPP

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HT9170

Symbol Parameter Test Conditions Min. Typ. Max. Unit

RL Load Resistance (GS) VDD Conditions ¾ 50 ¾ kW
5V ¾ ¾ 100 ¾ pF
¾ 3.0 ¾ VPP
CL Load Capacitance (GS) 5V ¾
5 16 22 ms
VCM Common Mode Range 5V No load ¾ 4 8.5 ms
¾ ¾ 42 ms
Steering Control 20 ¾ ¾ ms
¾ ¾ 42 ms
tDP Tone Present Detection Time 20 ¾ ¾ ms
¾ 8 11 ms
tDA Tone Absent Detection Time
¾ 12 ¾ ms
tACC Acceptable Tone Duration ¾ 4.5 ¾ ms
¾ 300 ¾ ns
tREJ Rejected Tone Duration ¾ 50 60 ns

tIA Acceptable Inter-digit Pause

tIR Rejected Inter-digit Pause

tPDO Propagation Delay
(RT/GT to DO)

tPDV Propagation Delay
(RT/GT to DV)

tDOV Output Data Set Up (DO to DV)
tDDO Disable Delay (OE to DO)
tEDO Enable Delay (OE to DO)

Note: DO=D0~D3

V DD

T one 100kW 1 V P V D D 18 0 .1 m F
0 .1 m F 300kW
100kW 2 VN R T /G T 1 7

3 .5 7 9 5 4 5 M H z 3 GS E S T 16

20pF 20pF 4 VREF D V 15
VSS
5 (IN H ) D 3 14

6 (P W D N ) D 2 1 3
7 X 1 D 1 12
8 X 2 D 0 11

9 VSS O E 10

H T 9 1 7 0 /B /D

Figure 1. Test circuit

6 December 20, 1999

Functional Description HT9170

Overview Steering control circuit

The HT9170 series tone decoders consist of The steering control circuit is used for measur-
three band pass filters and two digital decode ing the effective signal duration and for protect-
circuits to convert a tone (DTMF) signal into ing against drop out of valid signals. It employs
digital code output. the analog delay by external RC time-constant
controlled by EST.
An operational amplifier is built-in to adjust
the input signal (refer to Figure 2). The timing is shown in Figure 3. The EST pin is
normally low and draws the RT/GT pin to keep
C R1 VP low through discharge of external RC. When a
Vi VN valid tone input is detected, EST goes high to
charge RT/GT through RC.
H T9170
R F G S S e r ie s When the voltage of RT/GT changes from 0 to
VTRT (2.35V for 5V supply), the input signal is
VREF effective, and the correct code will be created by
the code detector. After D0~D3 are completely
( a ) S ta n d a r d in p u t c ir c u it latched, DV output becomes high. When the
voltage of RT/GT falls down from VDD to VTRT
C R1 VP (i.e.., when there is no input tone), DV output
V i1 VN becomes low, and D0~D3 keeps data until a
next valid tone input is produced.
V i2
C R2 By selecting adequate external RC value, the min-
imum acceptable input tone duration (tACC) and
R3 R4 R5 H T9170 the minimum acceptable inter-tone rejection (tIR)
G S S e r ie s can be set. External components (R, C) are chosen
by the formula (refer to Figure 5.):
VREF
tACC=tDP+tGTP;
( b ) D iffe r e n tia l in p u t c ir c u it tIR=tDA+tGTA;
where tACC: Tone duration acceptable time
Figure 2. Input operation for amplifier applica-
tion circuits tDP: EST output delay time (²L²®²H²)
tGTP: Tone present time
The pre-filter is a band rejection filter which re- tIR: Inter-digit pause rejection time
duces the dialing tone from 350Hz to 400Hz. tDA: EST output delay time (²H²®²L²)
tGTA: Tone absent time
The low group filter filters low group frequency
signal output whereas the high group filter fil-
ters high group frequency signal output.

Each filter output is followed by a zero-crossing
detector with hysteresis. When each signal am-
plitude at the output exceeds the specified
level, it is transferred to full swing logic signal.

When input signals are recognized to be effec-
tive, DV becomes high, and the correct tone
code (DTMF) digit is transferred.

7 December 20, 1999

Timing Diagrams Tone n t IR HT9170
t IA
tR E J tG T A
Tone n+1 Tone C ode n+1
Tone
tE D O
tD P tD P tD A tD P
EST tA C C

R T /G T V TRT
D 0~D 3
Tone C ode n 1 tP D O tG T P
tP D V Tone C ode n tP D V

tD O V

DV tD D O
OE

Figure 3. Steering timing

Tone Tone

PW DN

EST
tP U

Figure 4. Power up timing

8 December 20, 1999

HT9170

V DD V DD

H T 9170 VDD C H T 9170 VDD C
S e r ie s S e r ie s

R T /G T R R T /G T R1
EST D1 R2
EST

(a) Fundamental circuit: (c) tGTP > tGTA :
tGTP = R1 ´ C ´ Ln (VDD / (VDD - VTRT))
tGTP = R ´ C ´ Ln (VDD / (VDD - VTRT)) tGTA = (R1 // R2) ´ C ´ Ln (VDD / VTRT)
tGTA = R ´ C ´ Ln (VDD / VTRT)

V DD

H T 9170 VDD C
S e r ie s
R1
R T /G T D1 R2

EST

(b) tGTP < tGTA :
tGTP = (R1 // R2) ´ C ´ Ln (VDD - VTRT))
tGTA = R1 ´ C ´ Ln (VDD / VTRT)

Figure 5. Steering time adjustment circuits

DTMF dialing matrix

C O L1 C O L2 C O L3 C O L4
ROW 1 1 2 3 A
ROW 2 4 5 6 B
ROW 3 7 8 9 C
ROW 4 * 0 # D

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HT9170

DTMF data output table

Low Group (Hz) High Group (Hz) Digit OE D3 D2 D1 D0

697 1209 1 HL L LH

697 1336 2 HL LHL

697 1477 3 HL LHH

770 1209 4 HLHL L

770 1336 5HLHLH

770 1477 6 HLHHL

852 1209 7 HLHHH

852 1336 8 HHL L L

852 1477 9 HHL LH

941 1336 0 HHLHL

941 1209 * HHLHH

941 1477 # HHHL L

697 1633 A HHH L H

770 1633 B HHHH L

852 1633 CHHHHH

941 1633 DHL L L L

¾ ¾ ANY L Z Z Z Z

Z: High impedance

Data output

The data outputs (D0~D3) are tristate outputs. When OE input becomes low, the data outputs
(D0~D3) are high impedance.

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HT9170

Application Circuits

V DD

100kW 1 V P V D D 18 0 .1 m F
0 .1 m F 300kW
D TM F 2 V N R T /G T 1 7 T o o th e r d e v ic e

3 GS E S T 16

100kW 4 VREF D V 15

5 IN H D 3 14

T o o th e r d e v ic e 6 PW DN D 2 13

7 X 1 D 1 12
8 X 2 D 0 11
X 'T A L
9 VSS O E 10
C1 C2
VSS H T 9 1 7 0 B /D
1 8 D IP /S O P

N o te : ( a ) X 'T A L = 3 .5 7 9 5 4 5 M H z c r y s ta l
C 1 = C 2 @ 20pF

( b ) X 'T A L = 3 .5 8 M H z c e r a m ic r e s o n a to r
C 1 = C 2 @ 39pF

11 December 20, 1999

HT9170

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Tel: 886-3-563-1999
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Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

12 December 20, 1999

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