ELECTRICAL ENGINEERING DEPARTMENT POLITEKNIK KOTA KINABALU, SABAH ELECTRICAL ENGINEERING DEPARTMENT POLITEKNIK KOTA KINABALU, SABAH
JUMRIANI & SAFARI HJ NONGKANG ELECTRICAL ENGINEERING DEPARTMENT
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02 01 03 Introduction Asynchronous up counters 8 Asynchronous down counters 11 Asynchronous up/ down counters 14 Circuit and timing diagram Asynchronous Counters Synchronous Counters 04 Principles of Counter Contents Preface Reference [email protected] Synchronous up counters 17 Synchronous down counters 22 Synchronous up/ down counters 27 Synchronous random counters 28 Circuit and timing diagram Counters 2 Modulo 3 Frequency divider 4 n Asynchronous Counter mode less than 2 33 Synchronous Counter using Don’t Care condition 38 05 Final Exam Questions Digital Electronics, Politeknik Malaysia 42 Dec 2014 - July 2019 53
Preface 088-401800 www.polikk.edu.my Lecturer Electrical Engineering Department Politeknik Kota Kinabalu Jumriani hj Nongkang & Safari hj Nongkang
• Construct Asynchronous Counters (N<2 ) & Synchronous Counters (using don’t care condition) • Construct the circuit and timing diagram of Up, Down & Up/ Down of Asynchronous Counter Construct the circuit and timing diagram of Up, Down & Up/ Down & random of Synchronous Counter [email protected] J K E 1 n
INTRODUCTION COUNTER 1.1 1.2 MODULA FREQUENCY DIVIDER 1.3 1.1 COUNTER Flip-flops can be used to form binary counters Counter is logic circuit that can increment or decrement a count by one Counter is important in digital system, it can be used for measuring of time and frequency. The counter used in computer, digital clock, digital to analog converter, frequency divider and other digital system. Counters can be formed by connecting JK or T flip-flops together and any number of flip-flops can be connected or cascaded together. Cascade means to connect the Q output of one flip-flop to the clock input of the next. Flip-flops can be used to form binary counters Counter is logic circuit that can increment or decrement a count by one Counter is important in digital system, it can be used for measuring of time and frequency. The counter used in computer, digital clock, digital to analog converter, frequency divider and other digital system. Counters can be formed by connecting JK or T flip-flops together and any number of flip-flops can be connected or cascaded together. Cascade means to connect the Q output of one flip-flop to the clock input of the next. [email protected] J K E 2
INTRODUCTION COUNTER 1.1 1.2 MODULA FREQUENCY DIVIDER 1.3 1.2 MODULA The modulus (or just modulo) is the number of states the counter counts and is the dividing number of the counter. Modulus Counters, or simply MOD counters, are defined based on the number of states that the counter will sequence through before returning back to its original value. one complete cycle A counter with 2 flip-flops will count from 0 to 3 It has 4 different output states representing the decimal numbers 0 to 3 and is called a Modulo-4 or MOD-4 counter. The modula number can be increased by adding more flipflops to the counter and cascading is a method of achieving higher modulus counters. [email protected] J K E 3
INTRODUCTION COUNTER MODULA FREQUENCY DIVIDER FREQUENCY DIVIDER 1.3 1.3 FREQUENCY DIVIDER Asynchronous counter also known as Frequency divider Frequency divider or called as clock divider, is a circuit that takes an input signal of a frequency, and generates an output signal of frequency. [email protected] J K E 4
FINAL EXAMINATION SESSION II : 2022/2023 DEE20033 (Q4b, CLO1) 5 [email protected] J K E If the input frequency for a 4-bit asynchronous counter is 40kHz, locate the value of input frequency of the counter and output frequency for second flip-flop. SOLUTION
ASYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER [email protected] J K E 6
ASYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER [email protected] J K E 7
ASYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER ASYNC. UP COUNTER ASYNC. UP COUNTER 2.1 2.1 ASYNCHRONOUS UP COUNTER Asynchronous Up Counter use to count increment value. For example, for counter mod 4, 2 bit, mod 4 ---> N = 4 2 bit n = 2 counts 0, 1, 2, 3, 0, 1, 2, 3, 0 and so on. [email protected] J K E 8
9 [email protected] J K E Construct a state diagram, circuit and timing diagram for an asynchronous up counter 3 bits by using T flip-flop with negative edge triggered. SOLUTION
10 [email protected] J K E Construct a state diagram, circuit and timing diagram for an asynchronous up counter 3 bits by using T flip-flop with negative edge triggered. SOLUTION A B C
ASYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER 2.2 ASYNC. DOWN COUNTER ASYNC. DOWN COUNTER [email protected] J K E 11
12 [email protected] J K E Construct a state diagram, circuit and timing diagram for an asynchronous down counter 3 bits by using T flip-flop with negative edge triggered. SOLUTION
13 [email protected] J K E Construct a state diagram, circuit and timing diagram for an asynchronous down counter 3 bits by using T flip-flop with negative edge triggered. SOLUTION
ASYNCHRONOUS COUNTER ASYNCHRONOUS COUNTER 2.3 ASYNC. UP / DOWN COUNTER [email protected] J K E 14
SYNCHRONOUS COUNTER SYNCHRONOUS COUNTER [email protected] J K E 15
SYNCHRONOUS COUNTER SYNCHRONOUS COUNTER [email protected] J K E 16
SYNCHRONOUS COUNTER SYNCHRONOUS COUNTER SYNC. UP COUNTER SYNC. UP COUNTER 3.1 3.1 SYNCHRONOUS UP COUNTER Synchronous Up Counter use to count increment value. For example, for counter mod 4, 2 bit, mod 4 ---> N = 4 2 bit n = 2 counts 0, 1, 2, 3, 0, 1, 2, 3, 0 and so on. [email protected] J K E 17
18 [email protected] J K E Construct a synchronous up counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
19 [email protected] J K E Construct a synchronous up counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
20 [email protected] J K E Construct a synchronous up counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
21 [email protected] J K E Construct a synchronous up counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
SYNCHRONOUS COUNTER SYNCHRONOUS COUNTER 3.2 3.2 SYNCHRONOUS DOWN COUNTER Synchronous down counter use to count decrement value. For example, for counter mod 4, 2 bit, mod 4 ---> N = 4 2 bit n = 2 counts 0, 3, 2, 1, 0, 3, 2, 1, 0 and so on. SYNC. DOWN COUNTER SYNC. DOWN COUNTER [email protected] J K E 22
23 [email protected] J K E Construct a synchronous down counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
24 [email protected] J K E Construct a synchronous down counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
25 [email protected] J K E Construct a synchronous down counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
26 [email protected] J K E Construct a synchronous down counter MOD 16 using JK flip-flop with negative edge triggered clock input. Show all the steps involved. SOLUTION
SYNCHRONOUS COUNTER SYNCHRONOUS COUNTER 3.2 3.3 3.3 SYNCHRONOUS UP/ DOWN COUNTER Synchronous counter also available in integrated circuit form as UP/DOWN counters, which can be made to operate as either UP or DOWN counter. The counter counts upwards when UP control is logic 1 and DOWN control is logic 0. In this case the clock input of each flip-flop other than the LSB flip-flop is fed from the normal output immediately preceding flip-flop. The counter counts downwards when the UP control input is logic 0 and DOWN control is logic 1. In this case, the clock input of each flip-flop other than the LSB flip-flop is fed from the complemented output of the immediately preceding flip-flop. SYNC. UP / DOWN COUNTER SYNC. UP / DOWN COUNTER [email protected] J K E 27
SYNCHRONOUS COUNTER SYNCHRONOUS COUNTER 3.2 3.4 SYNCHRONOUS RANDOM COUNTER Synchronous counters are advantageous over asynchronous counter as in synchronous counter are clocked at the same time and in asynchronous counter has propagation delay because the counter are not clocked simultaneously. Also, synchronous counter allow counter design in any arbitrary sequence. For example, synchronous random counter counts the sequence of 6, 1, 2, 4, 7, 3, 5 and repeats it again. 3.4 SYNC. RANDOM COUNTER SYNC. RANDOM COUNTER [email protected] J K E 28
29 [email protected] J K E Design using JK flip-flop, a synchronous counter which counts the sequence of 6, 1, 2, 4, 7, 3, 5 and repeats it again. Show all the steps involved. SOLUTION
30 [email protected] J K E Design using JK flip-flop, a synchronous counter which counts the sequence of 6, 1, 2, 4, 7, 3, 5 and repeats it again. Show all the steps involved. SOLUTION
31 [email protected] J K E Design using JK flip-flop, a synchronous counter which counts the sequence of 6, 1, 2, 4, 7, 3, 5 and repeats it again. Show all the steps involved. SOLUTION
32 [email protected] J K E Design using JK flip-flop, a synchronous counter which counts the sequence of 6, 1, 2, 4, 7, 3, 5 and repeats it again. Show all the steps involved. SOLUTION
PRINCIPLE OF COUNTER PRINCIPLE OF COUNTER ASYNCHRONOUS COUNTER N<2 ASYNCHRONOUS COUNTER N<2 4.1 4.2 4.1 ASYNCHRONOUS COUNTER N<2 Design a MOD synchronous binary counter less than 2 by allowing the counter to skip a situation or state. We will learn and build this counter circuit using the RESET method. [email protected] J K E 33 n n n
given N = 6, the largest decimel number = N - 1 = 6 - 1 = 5 34 [email protected] J K E Construct a circuit to perform a mod-6 asynchronous down counter, negative edge triggered JK flip-flop. SOLUTION
35 [email protected] J K E Construct a circuit to perform a mod-6 asynchronous down counter, negative edge triggered JK flip-flop. SOLUTION
36 [email protected] J K E Construct a circuit to perform a mod-6 asynchronous down counter, negative edge triggered JK flip-flop. SOLUTION
37 [email protected] J K E Construct a circuit to perform a mod-6 asynchronous down counter, negative edge triggered JK flip-flop. SOLUTION
PRINCIPLE OF COUNTER PRINCIPLE OF COUNTER 4.2 4.2 SYNCHRONOUS COUNTER USING DON'T CARE CONDITION Design a MOD synchronous binary random counter using don't care condition. Modulus can be determined by the number of flip-flop used, design the state diagram, transition table, mapping to k-map to produce the Boolean expression then construct the counter circuit. [email protected] J K E 38 SYNCHRONOUS COUNTER USING DON'T CARE CONDITION SYNCHRONOUS COUNTER USING DON'T CARE CONDITION
the largest decimel number = 14 39 [email protected] J K E Synchronous counter, negative edge triggered, T flipflop, which counts 0, 2, 4, 6, 8, 10, 12, 14 and then recycles back to 0. Determine the number of flipflop, state diagram and transition table. SOLUTION
40 [email protected] J K E Synchronous counter, negative edge triggered, T flipflop, which counts 0, 2, 4, 6, 8, 10, 12, 14 and then recycles back to 0. Determine the number of flipflop, state diagram and transition table. SOLUTION
41 [email protected] J K E Synchronous counter, negative edge triggered, T flipflop, which counts 0, 2, 4, 6, 8, 10, 12, 14 and then recycles back to 0. Determine the number of flipflop, state diagram and transition table. SOLUTION
FINAL EXAM QUESTIONS FINAL EXAM QUESTIONS [email protected] J K E 42 FINAL EXAM : DECEMBER 2014 SESSION (21 APRIL 2015) DEE2034 DIGITAL ELECTRONICS FINAL EXAM : DECEMBER 2015 SESSION (14 APRIL 2016) DEE2034 DIGITAL ELECTRONICS FINAL EXAM : DECEMBER 2016 SESSION (11 APRIL 2017) DEE2034 DIGITAL ELECTRONICS FINAL EXAM : DECEMBER 2017 SESSION (10 APRIL 2018) DEE2034 DIGITAL ELECTRONICS FINAL EXAM : DECEMBER 2018 SESSION (24 APRIL 2019) DEE2034 DIGITAL ELECTRONICS
FINAL EXAM QUESTIONS FINAL EXAM QUESTIONS [email protected] J K E 43 [email protected] J K E
FINAL EXAM QUESTIONS FINAL EXAM QUESTIONS [email protected] J K E 44 [email protected] J K E
FINAL EXAM QUESTIONS FINAL EXAM QUESTIONS [email protected] J K E 45