(8th Edition) Barry B. Brey-The Intel Microprocessors-Prentice Hall (2008)

ANSWERS TO SELECTED EVEN-NUMBERED QUESTIONS AND PROBLEMS 909

VCC mechanism is silent and very accurate because its
placement can be continuously adjusted.
1K 28. A CD-ROM is an optical device for storing music or
digital data and has a capacity of about 660M or
U1 700M (80 minute) bytes.
30. A TTL monitor uses TTL signals to generate a dis-
2 1A1 1Y1 18 D7 play and an analog monitor uses analog signals.
4 1A2 1T2 16 D6 32. Cyan, magenta, and yellow
6 1A3 1Y3 14 D5 34. 1024 lines with 1280 horizontal elements per line
8 1A4 1Y4 12 D4 36. The DVI-D and HDMI connectors are the latest style
11 2A1 2Y1 D3 of digital video input connectors for all types of video
13 2A2 2Y2 9 D2 equipment.
15 2A3 2Y3 7 D1 38. 16 million colors
17 2A4 2Y4 5 D0
3 CHAPTER 14

INTA 1 1G 2. Word (16-bits, ±32K), doubleword (32-bits, ±2G),
19 2G and quadword (64-bits, ±9 × 1018)

74ALS244 4. Single-precision (32 bits), double-precision (64 bits),
and temporary-precision (80 bits)
FIGURE D–10
6. (a) -7.75 (b) .5625 (c) 76.5 (d) 2.0 (e) 10.0 (f) 0.0
46. Program sensitivity and single or multiple 8259s 8. The microprocessor continues executing micro-
48. The most recent interrupt request level becomes the
processor (integer) instructions while the coprocessor
lowest level interrupt after being serviced. executes a floating-point instructions.
50. INT 8 through INT 0FH 10. It copies the coprocessor status register to AX.
12. By comparing the two registers and then by transfer-
CHAPTER 13 ring the status word to the AX register. If the SAHF
instruction is next executed, a JZ instruction can be
2. When a 1 is placed on HOLD, the program stops exe- used to test the outcome of the coprocessor compare
cuting and the address, data, and control buses go to instruction.
their high-impedance state. 14. FSTSW AX
16. Data are always stored as an 80-bit temporary preci-
4. I/O to memory sion number.
6. DACK 18. 0
8. The microprocessor is in its hold state and the DMA 20. Affine allows positive and negative infinity, while
projective assumes infinity is unsigned.
controller has control of the buses. 22. Extended (temporary) precision
10. 4 24. The contents of the top of the stack are copied into
12. The command register memory location DATA as a floating-point number.
16. A pen drive is a USB device that acts as a storage 26. FADD ST,ST(3)
28. FSUB ST(2),ST
device using a flash memory.
18. Tracks
20. Cylinder
22. See Figure D–11.
24. The heads in a hard disk drive are aerodynamically

designed to ride on a cushion of air as the disk spins
and are therefore called flying heads.
26. The stepper motor positioning mechanism is noisy
and not very precise, while the voice coil positioning

100 101 000 0

D CD D C CC

FIGURE D–11

910 APPENDIX D

30. Forward division divides the top of the stack by the FLD TEMP
FYL2X
contents of a memory location and returns the quo- FSTP TEMP
MOV ECX,TEMP
tient to the top of the stack. Reverse division divides RET
POW ENDP
the top of the stack into the contents of the memory
54. GAIN PROC NEAR
location and returns the result to the top of the stack.
MOV ECX,100
If no operand exists, then forward division divides .REPEAT

ST(1) by ST and reverse division divides ST by FLD DWORD PTR VOUT[ECX*4–4]
FDIV DWORD PTR VIN[ECX*4-4]
ST(1). CALL LOG10
FIMUL TWENTY
32. It performs a MOV to ST if the condition is below. FSTP DWORD PTR DBG[ECX*4-4]
.UNTILCXZ
34. RECIP PROC NEAR RET
TWENTY DW 20
MOV TEMP,EAX GAIN ENDP
FLD TEMP
FLD1 56. The EMMS instruction clears the coprocessor stack
FDIVR
FSTP TEMP to indicate that the MMX unit has completed using
MOV EAX,TEMP
RECIP ENDP the stack.
TEMP DD ?
58. Signed saturation occurs when byte-sized numbers
36. Finds the function 2X – 1.
are added and have values of 7FH for an overflow and
38. FLDPI
80H for an underflow.
40. It indicates that register ST(2) is free.
60. The FSAVE instruction stores all the MMX registers
42. The state of the machine
in memory.
44. CAPR PROC NEAR
FLDPI 62. Single-instruction, multiple-data instructions
CAPR FADD ST,ST(1)
FMUL F 64. 128 bits
FMUL C1
FLD1 66. 16
FDIVR
FTSP XC 68. Yes
RET
ENDP CHAPTER 15

46. In modern software it is never used. 2. 8- or 16-bit depending on the socket configuration.

48. TOT PROC NEAR 4. See Figure D–12.
FLD R2
TOT FLD1 6. See Figure D–13.
FDIVR
FLD R3 8. See Figure D–14.
FLD1
FDIVR 12. 16 bits
FLD R4
FLD1 14. The configuration memory identifies the vendor and
FDIVR
FADD also information about the interrupts.
FADD
FLD1 16. This is the command/bus enable signal that is high to
FDIV
FADD R1 indicate the PCI bus contains a command and low for
FSTP RT
RET data.
ENDP
18. MOV AX,0B108H
BX,0
MOV DI,8
1AH
MOV

INT

50. PROD PROC NEAR 20. 2.5 GHz
MOV ECX,100
PROD .REPEAT 22. Yes

FLD ARRAY1[ECX*8–8] 24. COM1
FUML ARRAY2[ECX*8–8] 30. 1.5 Mbps, 12 Mbps, and 480 Mbps
FSTP ARRAY3[ECX+8–8]
.UNTILCXZ 32. 5 meters
RET
ENDP 34. 127

52. POW PROC NEAR 36. An extra bit that is thrown in the data stream if more
MOV TEMP,EBX
FLD TEMP than six ones are sent in a row.
F2XM1
FLD1 38. 1 to 1023 bytes
FADD
MOV TEMP,EAX 40. The PCI transfers data at 33 MBs, while AGP trans-

fers data at 2 GBps (8 ×).

ANSWERS TO SELECTED EVEN-NUMBERED QUESTIONS AND PROBLEMS 911

CHAPTER 16 6. 3 mA
8. The point at which the address appears
2. The hardware enhancements include internal timers, 10. 260 ns for the 16 MHz version operated at 10 MHz
additional interrupt inputs, chip selection logic, serial 12. MOV AX,1000H
communications ports, parallel pins, DMA controller,
and an interrupt controller. MOV DX,0FFFEH
OUT DX,AX
4. 10 MHz
14. 10 on most versions of the 80186/80188 including the
internal interrupts.

U2

SD0 34 D0 PA0 4
SD1 33 D1 PA1 3
SD2 32 D2 PA2 2
SD3 31 D3 PA3 1
SD4 30 D4 PA4 40
SD5 29 D5 PA5 39
SD6 28 D6 PA6 38
SD7 27 D7 PA7 37

IOR 5 RD PB0 18
IOW 36 WR PB1 19
SA0 A0 PB2 20
SA1 9 A1 PB3 21
RESET 8 RESET PB4 22
35 CS PB5 23
6 PB6 24
PB7 25
U1
PC0 14
SA2 1 I1 O1 19 PC1 15
SA3 2 I2 PC2 16
SA4 3 I3 O2 18 PC3 17
SA5 4 I4 O3 17 PC4 13
SA6 5 I5 O4 16 PC5 12
SA7 6 I6 O5 15 PC6 11
SA8 7 I7 O6 14 PC7 10
SA9 8 I8 O7 13
SA10 9 I9 O8 12
SA11 11 I10

SA12 16L8 82C55
SA13
SA14
SA15

FIGURE D–12

SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0

U2

SA0 10 A0 O0 11
SA1 9 A1 O1 12
SA2 8 A2 O2 13
SA3 7 A3 O3 15
SA4 6 A4 O4 16
SA5 5 A5 O5 17
SA6 4 A6 O6 18
SA7 3 A7 O7 19
SA8 A8
SA9 25 A9
SA10 24 A10
SA11 21 A11
SA12 23 A12
SA13 A13
SA14 2 A14
26
27

SMEMR 20 CE
22 OE
SA15 VPP
SA16 1
SA17
SA18 U1 27C256
SA19
LA20 1 I1 O1 19 10K
LA21 2 I2
LA22 3 I3 O2 18 VCC
LA23 4 I4 O3 17
5 I5 O4 16
6 I6 O5 15
7 I7 O6 14
8 I8 O7 13
9 I9 O8 12
11 I10

16L8

FIGURE D–13

912 APPENDIX D

U5

U1 1 CS VREF 8
2 WR1 RFB 9
WR2
18 IOUT2 12
IOUT1 11
SD0 2 1A1 1Y1 18 7 DI0 4 1 5 U9 Channel 800H
SD1 4 1A2 1Y2 16 6 DI1 AGND 3 Channel 810H
SD2 6 1A3 1Y3 14 5 DI2 2– 6 Channel 820H
SD3 8 1A4 1Y4 12 4 DI3 3+ Channel 830H
SD4 11 2A1 2Y1 9 16 DI4
SD5 13 2A2 2Y2 7 15 DI5 741
SD6 15 2A3 2Y3 5 14 DI6 7
SD7 17 2A4 2Y4 3 13 DI7

1 1G 17 XFER
19 2G 19 ILE

74ALS244 10 DGND

DAC0830

U6

U2 1 CS VREF 8
2 WR1 RFB 9
1 19 WR2
2 18 18 IOUT2 12
3 17 IOUT1 11
SA0 4 I1 O1 16 7 DI0 4 1 5 U10
SA1 5 I2 15 6 DI1 AGND 3
SA2 6 I3 O2 14 5 DI2 2– 6
SA3 7 I4 O3 13 4 DI3 3+
SA4 8 I5 O4 12 16 DI4
SA5 9 I6 O5 15 DI5 741
SA6 11 I7 O6 14 DI6 7
SA7 I8 O7 13 DI7
SA8 I9 O8
SA9 I10
17
SA10 16L8 19 XFER
SA11 ILE

SA12 10 DGND
SA13
1 U3A DAC0830
SA14 2
SA15 6 U7
4
5 1 CS VREF 8
2 WR1 RFB 9
74ALS20 WR2
18 IOUT2 12
IOUT1 11
VCC 7 DI0
6 DI1 AGND 3
10K 5 DI2 415 U11
4 DI3 6
9 U3B 16 DI4 2–
10 15 DI5 3+
14 DI6
IOW 12 13 DI7
13
8 17 XFER 741
74ALS20 19 ILE 7

10 DGND

DAC0830

U8

1 CS VREF 8
2 WR1 RFB 9
WR2
18 IOUT2 12
IOUT1 11
7 DI0 4 1 5 U12
6 DI1 AGND 3
5 DI2 2– 6
4 DI3 3+
16 DI4
15 DI5 741
14 DI6 7
13 DI7

17 XFER
19 ILE

10 DGND

DAC0830

FIGURE D–14 28. MOV AX,123
DX,0FF5AH
16. The interrupt control registers control a single interrupt. MOV DX,AX
18. The interrupt poll register acknowledges the inter- OUT AX,23
MOV DX,2
rupt, while the interrupt poll status register does not ADD DX,AX
acknowledge the interrupt. OUT AX,0C007H
20. 3 MOV DX,0FF58H
22. Timer 2 MOV DX,AX
24. It determines whether the enable counter bit functions. OUT
26. The ALT bit selects both compare registers so the
duration of the logic 1 and logic 0 output times can be 30. 2
programmed.
32. Place a logic 1 in both the CHG/NOCHG and

START/STOP bits of the control register.

34. 7

ANSWERS TO SELECTED EVEN-NUMBERED QUESTIONS AND PROBLEMS 913

36. Chip 18. The test registers are used to test the translation look-
aside buffer.
38. 15
20. The PE bit switches the microprocessor into
40. It determines the operation of the PCS5 and PCS6 protected mode if set and real mode if cleared.

pins. 22. Scaled-index addressing used a scaling factor of 1, 2,
4, or 8 times to scale addressing from byte, word,
42. MOV AX,1001H doubleword, or quadword.
DX,0FF90H
MOV DX,AX 24. (a) the address in the data segment at the location
OUT AX,1048H pointed to by EBX times 8 plus ECX (b) the address
MOV DX,AX in the data segment array DATA pointed to by the
OUT sum of EAX plus EBX (c) the address at data
segment location DATA (d) the address in the data
44. 1G segment pointed to by EBX

46. Verify for read access. 26. Type 13 (0DH)
28. The interrupt descriptor table and its interrupt
48. An RTOS is a real-time operating system that has a
descriptors
predictable and guaranteed time for threads access. 30. A selector appears in a segment register and it selects

CHAPTER 17 a descriptor from a descriptor table. It also contains
the requested privilege level of the request.
2. 64T 32. The global descriptor table register
4. See Figure D–15. 34. Because a descriptor addresses up to 4G of memory
6. The memory system has up to 4G bytes and the bank and there are 8K local and 8K global descriptor avail-
able at a time, 4G times 16K = 64T.
enable signals select one or more of the 8-bit-wide 36. The TSS holds linkages and registers of a task so
banks of memory. tasks can be switched efficiently.
8. The pipeline allows the microprocessor to send 38. The switch occurs when a logic 1 is placed into the
the address of the next memory location, while it PE bit of CR0.
fetches the data from the prior memory operation. 40. Virtual mode, which simulates DOS in protected
This allows the memory additional time to access mode, sets up 1M memory spans that can operate in
the data. the real mode.
10. 0000H–FFFFH 42. 4K
12. I/O has the same address as earlier models of the 44. The 80486 has an internal 8K cache and also contains
microprocessor. The difference is that the I/O is a coprocessor.
arranged as a 32-bit-wide space with four 8-bit banks 46. The register sets are virtually identical.
that are selected by the bank enable signals. 48. PCHK and DP0–DP3
14. The BS16 pin causes the microprocessor to function 50. 8K
with an 8-bit-wide data bus. 52. A burst is when four 32-bit numbers are read or writ-
16. The first four debug registers (DR0–DR3) contain ten between the cache and memory.
breakpoint addresses; registers DR4 and DR5 are 54. Built-in self test
reserved for Intel’s use; DR6 and DR7 are used to
control debugging. CHAPTER 18

FFFFFFFF 2. 64G bytes
4. These pins generate and check parity.
000FFFFF Protected 6. The burst ready pin is used to insert wait state into the
Mode
Real Mode bus cycle.
Memory Map Memory 8. 18.5 ns
Map 10. T2
12. An 8K byte data cache and an 8K-byte instruction
00000000 00000000
cache.
FIGURE D–15 14. Yes, if one is a coprocessor instruction and the integer

instructions are not dependent.

914 APPENDIX D 10. The read and write signals are developed by the chip

16. The SSM mode is used for power management in set instead of the microprocessor.
most systems.
12. 8 ns after the first quadword is accessed. The first
18. 38000H
20. The CMPXCH8B instruction compares the 64-bit quadword still requires 60 ns for access.

number in EDX:EAX with a 64-bit number stored in 14. Model-specific registers have been added for
memory. If they are equal, ECX:EBX is stored in
memory. If not equal, the contents of memory are SYSENTER_CS, STSENTER_SS, and SYSENTER_
moved into EDX:EAX.
22. ID, VIP, VIF, and AC ESP.
24. To access 4M pages, the page tables are dropped and
only the page directory is used with a 22-bit offset 16. The ECX register address the MSR number when the
address.
26. The Pentium Pro is an improved version of the RDMSR instruction executes. After execution,
Pentium that contains three integer units, an MMX
unit, and a 36-bit address bus. EDX:EAX contains the contents of the register
28. 36 address bits on A3 through A35 (A0–A2 are
encoded in the bank selection signals) 18. TESTS PROC NEAR
30. The access time in a 66 MHz Pentium is 18.5 ns and CPUID
in the Pentium Pro at 66 MHz access time is 17 ns. TESTS BT EDX,800H
32. SDRAM that is 72 bits wide is purchased for RET
ECC memory applications instead of 64-bit-wide ENDP
memory.
20. EDX to the EIP register and the value in ECX to the
CHAPTER 19
ESP register.
2. 512K, 1M, or 2M
4. The Pentium Pro cache is on the main board and the 22. Ring 3

Pentium 2 cache is in the cartridge and operates at a 24. Pentium Pro
high speed.
6. 64G bytes 26. The Pentium 4 or Core2 requires a power supply with
8. 242
an additional 12 V connector for the main board.

A Pentium 4–compliant supply must be used.

28. bool Hyper()

{

_asm

{

bool State = true;

mov eax,1

cpuid

mov temp1,31h

bt edx,28 ;check for hyper-

threading

jc Hyper1

mov State, 0

Hyper1:

}

return State;

}

INDEX

.COM. See Command file internal structure of, 536–541 8259A programmable interrupt controller
.LISTALL directive, 204 numeric execution unit of, 536 (PIC), 468–482, 487
.MODEL instruction, 84–85, 105, 148, 153 status register of, 536–540
.REPEAT-UNTIL construct, 206–207, 220 tag register of, 540–541 8284A clock generator, 307–310, 326
.UNTIL statement, 206–207, 220 8088/80188 (8-bit) memory interface, 8288 bus controller, 324–326
.WHILE statement, 205–206, 220
349–356, 374 pin functions of, 325
2-to-4 line decoder, 344 EEPROM with, 351–353 8289 bus arbiter, 509–513
3 1/2Љ disk floppy disk, 516–517, 529 EPROM with, 349–350
3-to-8 line decoder, 342–344 error correction with, 353–356 architecture of, 509–511
5 1/4Љ disk floppy disk, 514–516 flash memory with, 351–353 operation of, 511
32-bit addressing mode, 118 ROM with, 350–351 pin definitions for, 509–511
32-bit microprocessor, 8–9 8237 DMA controller, 492–506, 529 system illustrating, 511–513
64-bit addressing mode, 120–121 internal registers of, 494–497 16550 UART communications controller,
64-bit extension technology, 776 memory-to-memory transfer with, 499–504
4004 microprocessor, 5 pin definitions for, 492–494 475–482
4040 microprocessor, 5 printer interface processed with, 504–506 62256 DRAM, 336, 349–350
8080 microprocessor, 6–7 programming address and count registers 80186/80188/80286 microprocessors,
8085 microprocessor, 7, 10
8086 microprocessor, 7, 10 of, 498 627–676
8086/8088 hardware specifications, 302–327 software commands for, 497 AC operating characteristics of, 636
80X86 microprocessor connected to, architecture of, 627–636
8288 bus controller in, 324–326 block diagram of, 628–629
bus buffering/latching in, 310–315 498–499 80C188EB example interface with,
bus operation in, 315 8254 programmable communications interface,
bus timing in, 315–319, 326 655–662
clock generator, 307–310, 326 433–440, 448 chip selection unit in, 651–655
DC characteristics, 303–304 asynchronous serial data with, 433 DC operating characteristics of, 634
minimum v. maximum mode in, 306, functional description of, 433–434 DMA controller in, 649–651
pin functions for, 434–435 end-of-interrupt register in programming
323–326 pin-out for, 434
pin connections/functions, 304–307 programming of, 435–440 of, 643
pin-outs, 302–303 8254 programmable interval timer, features of, 629–634
power supply requirements, 303 interrupt controller in, 638–643
READY input with, 320–322, 326 423–432, 447 interrupt vectors with, 639
wait state with, 320–322, 326 address selection inputs for, 424 memory access time for, 634–636
8086/80186/80386SX (16-bit) memory DC motor speed/direction control with, pin-out of, 631–634
programming of enhancements with,
interface, 356–363, 374 429–432
16-bit bus control with, 356–357 functional description of, 423–424 637–655
separate bank decoders with, 357–359 generating waveform with, 427–428 real-time operating system with, 662–670
separate bank write strobes with, 357–359 internal structure for, 423 slave mode in programming of, 640
80X87 architecture for arithmetic coprocessor modes of operation for, 425–427 timers in, 643–649
control register of, 540 pin definitions for, 424 timing for, 634–636
control unit of, 536 pin-out for, 423 versions of, 628
programming of, 424–429 80286 microprocessor, 8, 670–675
reading counter with, 428–429 additional instructions from predecessors
82C55 keyboard interrupt, 462–465
of, 672–674
block diagram of, 671
hardware features of, 670–672

915

916 INDEX register, 158, 187 Application-specific integrated circuit
XADD, 161 (ASIC), 345
80286 microprocessor (continued ) Addition instruction (ADD), 156–161, 187
memory management unit of, 670 Address Architecture, 51–76
memory system of, 18–19 bus, 26–29 flat mode memory in, 72–74
virtual memory machine with, 674 fixed, 378 internal, 51–58
protected mode, 63–68, 74 memory paging in, 68–72, 74
80386 microprocessor, 677–718, 726–727 real mode memory, 58–63, 73 programming model for, 52–53, 73
input/output system of, 687–688 return, 208 protected mode addressing in, 63–68, 74
memory and I/O control signals in, segments/offsets in, 58–63, 73 real mode memory addressing for,
688–689 variable, 378 58–63, 73
memory management in, 695–702 Address latch enable (ALE), 306 registers for, 53–58, 73
memory paging mechanism of, 713–718, Address-size prefix, 113
727 Addressing Arithmetic coprocessor, 531–591
memory system of, 681–687 64-bit mode for, 120–121 arithmetic instructions for, 543–544
pin functions for, 679–680 32-bit mode of, 118 comparison instructions for, 544–545
pin-out of, 678 base-plus index, 79, 80, 91–93, 107 compatibility with microprocessor
protected mode in, 702–712 base relative-plus index, 79, 81, 96–97, 107 and, 532
special registers in, 692–694 data-addressing modes in, 77–100, 105 constant operations for, 546
timing in, 689–690 data structures with, 79–80 coprocessor control instruction for,
virtual 8086 mode in, 712–713 decoding for memory, 340–348, 374 546–548
wait states in, 691–692 direct, 86–87, 106 coprocessor instruction for, 548–549
direct data, 79, 80, 86–88, 106 data formats for, 532–536
80386DX/80486 (32-bit) memory interface, direct program, 100–101, 105 data transfer instructions for, 541–543
363–366, 374 displacement, 86–88, 106 instruction set for, 541–565
fixed-port, 138–139, 153 internal structure of, 536–541
32-bit memory interface with, 364–366 immediate, 78–80, 83–86, 107 interrupt vectors related to, 454
memory banks with, 363–364 indirect program, 101–102, 105 MMX technology and, 531, 570–581, 589
80486 microprocessor, 9, 10, 16, 677, modes of, 77–110 programming with, 565–569
program memory-addressing modes in, SSE technology and, 531, 581–587, 589
718–727 transcendental operations for, 545–546
architecture, 722–723 100–102, 105 80X87 architecture for, 536–541
memory system of, 723–726 R/M memory, 115–116
pin definitions for, 718–722 register, 78, 79, 81–83, 105–106 Arithmetic/logic instructions, 156–191
pin-out of, 718–719 register indirect, 79, 80, 88–91, 107 AND, 175–177, 188
XADD for, 161 register relative, 79, 80, 93–95, 107 addition, 156–161, 187
relative program, 101, 105 ASCII, 172–175, 188
A (auxiliary carry) flag, 56 RIP relative, 79, 81, 99 BCD, 172–173, 188
AAA instruction (ASCII adjust after scaled-index, 79, 81, 98–99, 107 bit scan, 185
special mode of, 116–117 bit test, 180–181
addition), 172 stack memory-addressing modes in, comparison, 165–166, 187
AAD instruction (ASCII adjust before division, 169–172, 188
102–105 Exclusive-OR, 178–180, 188
division), 172–174 variable-port, 139, 153 multiplication, 166–168, 188
AAM instruction (ASCII adjust after Advanced graphics port (APG), 19, 623–624 NEG, 181–182, 188
Advanced Micro Devices (AMD), 9 NOT, 181–182, 188
multiplication), 172, 174–175, 188 ALE. See Address latch enable operators, 25, 133, 153
AAS instruction (ASCII adjust after ALGOL (ALGOrithmic Language), 5 OR, 176–178, 188
ALIGN directive, 144, 145 rotate, 184–185, 188
subtraction), 172, 175 AMD. See Advanced Micro Devices shift, 182–184, 188
Abacus, 2 American National Standard Institute (ANSI), string comparison, 186–188
AC (alignment check) flag, 57 subtraction, 162–165, 187
Access rights byte, 65–66 223 TEST, 180, 188
Acknowledge signal, 416, 419 American Standard Code for Information
ADA, 5 ASCII adjust after addition. See AAA
ADC. See Add-with-carry instruction Interchange. See ASCII instruction
ADC080X analog-to-digital converter, Analog RGB video display, 524–529
Analog-to-digital converter. See ADC080X ASCII adjust after multiplication. See AAM
442–446, 448 instruction
ADD instruction. See Addition instruction analog-to-digital converter
Add-with-carry instruction (ADC), 157, Analytical Engine, 2, 5, 45 ASCII adjust after subtraction. See AAS
AND operation, 175–177, 188 instruction
160–161, 187 ANSI. See American National Standard
Addition. See also Add-with-carry ASCII adjust before division. See AAD
Institute instruction
instruction; Increment instruction APG. See Advanced graphics port
ADD, 156–161, 187 Application descriptor, 63 ASCII (American Standard Code for
array, 158–159 Information Interchange), 1, 35–37
ASCII adjust after, 172
carry with, 160–161, 187 codes returned by keyboard, 260–261
decimal adjust after, 172–173, 188
immediate, 158
increment, 159–160, 187
memory-to-register, 158

INDEX 917

conversion from binary to, 272–274, 299 interface, 592–626 CLC. See Clear carry
conversions to binary from, 274, 299 ISA, 592–602, 624 Clear carry (CLC), 217, 220
lookup tables for access to, 277 LPT, 612–614, 624 Clear interrupt flag (CTI), 215, 220
ASCII arithmetic, 172–175, 188 PCI, 19, 602–612, 624 CL.EXE, 223
ASIC. See Application-specific integrated Pentium III microprocessor, 771 CLI. See Disable interrupt
SATA, 19 Clock generator. See 8284A clock generator
circuit serial com ports, 614–617, 624 CLR. See Common language runtime
Assembler, 251–252. See also Microsoft USB, 19, 617–624 Cluster, 281
VESA, 19 CMC. See Complement carry
MACRO assembler Byte, 5, 25, 38–40, 131, 143–145, 153 CMOV (Conditional move) instruction,
Assembly language, 4. See also C/C++ Byte-sized data, 38–40
Byte swap instruction. See BSWAP (Byte 141–142, 153
assembler; Microsoft MACRO CMP. See Comparison instruction
assembler swap) instruction CMPS. See String compare
ASSUME directive, 144–146, 153 CMPXCHG. See Compare and exchange
AT attachment (ATA). See Integrated drive 82C55. See Programmable peripheral interface
electronics C/C++, 5 instruction
C/C++ assembler, 223–249. See also COBOL (COmputer Business Oriented
Babbage, Charles, 2, 5, 45
Bank Programming techniques Language), 5
32-bit applications with, 231–242, 247 Cold-start location, 350
8086/80186/80386SX (16-bit) memory Colossus, 4
interface with, 357–363 control button in, 236 Column address strobe, 336
design window in, 235 COM. See Serial com ports
80386DX/80486 (32-bit) memory interface developing Windows application in, Command file (.COM), 251–252
with, 363–364 Command processor, 20, 21
234–242 COMMAND.COM. See Command processor
Base address, 63–64 directly addressing I/O ports in, Common language runtime (CLR), 234
Base-plus index addressing, 79, 80, Common object file format, 252
233–234 Compact disk/read only memory (CD-ROM),
91–93, 107 I/O console keyboard/display example
Base relative-plus index addressing, 79, 81, 21, 521–522
for, 231–233 Compare and exchange instruction (CMPX-
96–97, 107 managed v. unmanaged program in, 240
BASIC, 5 16-bit DOS applications with, 224–231, 247 CHG), 166, 188
BCD. See Binary-coded decimal basic rules for, 224–226 Compare register, 645
BCD arithmetic, 172–173, 188 character strings in, 226–227 Comparison instruction (CMP),
BCH. See Binary-coded hexadecimal data structures in, 227–229
Big endian, 40 MASM inline commands not for, 226 165–166, 187
Binary-coded decimal (BCD), 5, 37–38, 46, mixed-language example program for, controlling program flow with, 203
Complement carry (CMC), 217, 220
172–173, 188, 272–274, 276–277, 299, 229–231 Complements, 34–35
533, 542. See also BCD arithmetic simple programs for, 224–226 Complex programmable logic device (CPLD),
arithmetic coprocessor using, 533 adding assembly to C++ programs in, 247
conversion from ASCII to, 274, 299 controlling program flow with, 202–203 345
conversions to ASCII from, 272–274, 299 linking assembly with C++ in, 242–246 Computer-aided drafting/design (CAD), 8
lookup tables conversion from, 276–277 mixed assembly/C++ object in, 242–247 Computerese, 1
Binary-coded hexadecimal (BCH), 33–34 C (carry) flag, 55 Conditional jump, 198–201, 219
Binary number, 29 CAD. See Computer-aided drafting/design Conditional loop, 202
Bit, 5 CALL instruction, 208–211, 220 Conditional move instruction. See CMOV
Bit scan forward (BSF), 185 far, 208–209, 220
Bit scan instructions, 185 hardware-generated, 213 (Conditional move) instruction
Bit scan reverse (BSR), 185 indirect memory addresses with, 210 Conditional set instructions, 200–201
Bit test instruction, 180–181 near, 208, 220 Control register, 540
Blu-ray DVD, 522 register operands with, 209–210 Control unit, 536
Bomar Brain, 3 software-generated, 213 Conventional memory. See Real memory
Bootstrap loader, 281 Carry flag bit, 217, 220 Convert byte to word (CBW), 169
BOUND instruction, 218, 220, 454, 455, 487 CBW. See Convert byte to word Convert doubleword to quadword (CDQ), 170
Breakpoint, 239, 454 CD-ROM memory. See Compact disk/read Convert word to doubleword (CWD), 170
BSF. See Bit scan forward Core2 (64-bit) memory interface,
BSR. See Bit scan reverse only memory
BSWAP (Byte swap) instruction, 140–141 CDQ. See Convert doubleword to quadword 366–370, 374
Bubble sort technique, 295–297 Centronics parallel printer interface, 384 Core2 microprocessors, 10, 14–16, 759,
Built-in self-test (BIST), 740 Chip enable, 330
Bus, 26–29 Chip select, 330 771–783
8086/8088 microprocessor with, 315–319, Chip selection unit 64-bit extension technology with, 776
326 64-bit mode for, 120–121
AGP, 19 80186/80188/80286 microprocessors with, CPUID instruction for, 776–779
defined, 17, 26 651–655 hyper-threading technology with, 775
DMA in sharing of, 506–513 memory interface with, 772–773
CISC (Complex instruction set computers), 7 model-specific registers with, 779–780

918 INDEX

Core2 microprocessors (continued ) MOVZX, 140, 153 ISA bus using, 594
multiple core technology with, 776 OUT, 138–140, 153 optical disk memory with, 521–522
performance-monitoring register with, 780 POP instruction as, 102–104, 107, 122, pen drives with, 517–518
register set with, 773–774 shared-bus operation of, 506–513
XADD for, 161 124–125, 152 video displays with, 517–529
PUSH instruction as, 102–104, 107, Direct program addressing, 100–101, 105
CPLD. See Complex programmable logic Direction flag. See D (direction) flag
device 122–124, 152 Directory names, 282
SAHF, 137–138 Disable interrupt (CLI), 128
CPU (Central processing unit). See segment override prefix with, 142, 153 Disk files, 280–294, 300
Microprocessor string, 130–136, 153 data encryption example program using,
XCHG, 137
CPUID instruction, 247, 742–744, 768–769 XLAT, 138, 153 297–299
Pentium 4/Core2 microprocessors with, Data segment, 89 FAT with, 280–282, 300
776–779 Data strobe, 417. See also Strobed output file names with, 282
Data structures, 79–80 MFT with, 280–282, 300
CRC. See Cyclic redundancy checks DB. See Define byte NTFS with, 280–282
CS (code) segment register, 57, 60, 73 DB25 connector, 384 numeric sort example program using,
CS:EIP, 60 DD. See Define doubleword directive
CS:IP, 60 DDK. See Microsoft Windows Driver 295–297
CTI. See Clear interrupt flag organization of, 281–282
CWD. See Convert word to doubleword Development Kit random access of, 291–293, 300
Cycle stealing. See Refresh cycles DDR. See Double-data rate root directory of, 281
Cyclic redundancy checks (CRC), 619 DEC. See Decrement instruction sequential access of, 282–291, 300
Cylinder, 514 Decimal. See also Binary-coded decimal time/date display example program using,

D (direction), 113, 152 (BCD) 294–295
D (direction) flag, 56, 130, 153 conversion from, 32–33, 46 Disk operating system (DOS), 19–21
DAA instruction (Decimal adjust after conversion to, 31–32, 46
fraction, 32–33 applications with C/C++ assembler for,
addition), 172–173, 188 Decimal adjust after addition. See DAA 224–231, 247
DAC0830 digital-to-analog converter,
instruction Displacement, 58
440–442, 445–446, 448 Decimal adjust after subtraction. See DAS Displacement addressing, 86–88, 106
ADC080X used with, 445–446 Distance, jump, 193
connecting to microprocessor of, 442 instruction DIV instruction, 169–172, 188
internal structure of, 441–442 Decrement instruction (DEC), 162–164, 187 Division, 169–172, 188
pin-out for, 441 Define byte (DB), 4
DAS instruction (Decimal adjust after subtrac- Define doubleword directive (DD), 42, 46, 8-bit, 169–170, 188
16-bit, 170, 188
tion), 172–173, 188 143–145, 153 32-bit, 170–171, 188
Data bus enable (DEN) Define quadword directive (DQ), 44, 46, 64-bit, 171–172, 188
ASCII adjust before, 172–174
80186/80188/80286 microprocessors, 634 143–144 DIV instruction, 169–172, 188
8086/8088 microprocessor, 306 Define ten byte (DT), 143–144 IDIV instruction, 169–172, 188
8288 bus controller, 325 Define word directive (DW), 41, 46, 143–145, DLL. See Dynamic link libraries
Data encryption example program, 297–299 DMA. See Direct memory access
Data formats, 35–44, 46 153 DMA controller, 649–651
ASCII, 1, 35–37, 172–175, 188, 260–261, DEN. See Data bus enable DMA read, 491
Descriptors, 63–67, 74 DMA request inputs, 594
272–274, 299 DMA write, 491
BCD, 5, 37–38, 46, 172–173, 188, application, 63 DOS. See Disk operating system
base address of, 63–64 DOS memory. See Real memory
272–274, 276–277, 299, 533, 542 global, 63 DOS protected mode interface
byte-sized, 5, 25, 38–40, 131, 143–145, 153 local, 63
doubleword-sized, 41–43, 46, 143–145, system, 63 (DPMI), 706
Destination, 102 Dot commands, 202. See also Specific
153, 170 DI register, 130, 153 Double, 44
implied bit in, 43 Digital-to-analog converter. See DAC0830 Double-data rate (DDR), 373
real numbers, 43–44 Double-density double-sided floppy disk
Unicode, 35–37 digital-to-analog converter
word-sized, 40–41 Digital Versatile Disk. See DVD (DSDD), 514–515, 517, 529
Data movement instructions, 111–155 DIMM. See Dual In-Line Memory Modules Double-precision number, 43
IN, 138–140, 153 DIP. See Dual in-line packages Doubleword, 25
assembler detail for, 142–151, 153 Direct addressing, 86–87, 106 Doubleword-sized data, 41–43
BSWAP, 140–141 Direct data addressing, 79, 80, 86–88, 106 DPMI. See DOS protected mode interface
CMOV, 141–142, 153 Direct memory access (DMA), 490–530 DQ. See Define quadword directive
LAHF, 137–138 DRAM. See Dynamic random access
load-effective address, 127–130, 152 8237 DMA controller for, 492–506, 529
machine language for, 112–120 basic operation of, 490–492 memory
MOV, 77–110, 112–121, 152 disk memory systems with, 513–522, 529
MOVSX, 140, 153 floppy disk memory with, 513–517, 529
hard disk memory with, 518–521

INDEX 919

DS (data) segment register, 57, 73 ES (extra) segment register, 57 FLD1 load instruction, 555
DT. See Define ten byte ESC. See Escape instruction FLDCW load control register
Dual In-Line Memory Modules (DIMM), Escape instruction (ESC), 218
Exchange and add (XADD), 161 instruction, 557
338, 340 Exchange instruction. See XCHG (Exchange) FLDENV load environment instruction, 557
Dual in-line packages (DIP), 303 Float, 44
Dump record, 741–742 instruction Floating-point number, 43
DVD (Digital Versatile Disk), 21 Exclusive-OR instruction (XOR), 178–180,
DW. See Define word directive arithmetic coprocessor using, 533–536
Dynamic link libraries (DLL), 257 188 converting from, 535
Dynamic random access memory (DRAM), Execution file, 251 converting to, 534–535
Extended data output (EDO), 373 storing in memory, 535–536
328, 333–340, 370–374 Extended memory system (XMS), 17–18 Floppy disk memory, 513–517, 529
address input timing for, 334 EXTERN statement, 243 3 1/2Љ disk, 516–517, 529
address input timing of TMS4464, 337 External label, 196 5 1/4Љ disk, 514–516
address multiplexer for, 334 EXTRN directive, 253, 299
address multiplexer of TMS4464, 337 double-density double-sided, 514–515,
controllers, 373 FABS absolute value instruction, 550 529
DIMM, 338, 340 FADD/FADDP/FIADD addition instruction,
double-data rate, 373 high-density, 515, 529
EDO memory with, 373 543, 550 MFM recording in, 514–516, 529
pin-out of 62256, 336 Far CALL, 208–209, 220 NRZ recording in, 515, 529
pin-out of TMS4464, 334, 336 Far jump, 193, 195–196, 219 FLOWMATIC, 4, 45
refresh cycles with, 370–371, 373 Far label, 196 FMUL/FMULP/FIMUL multiplication
RIMM, 340 FAT. See File allocation table
SIMM, 338–339 FCLEX/FNCLEX clear errors instruction, 551 instruction, 558
synchronous, 371–373 FCMOVcc condition move instruction, 552 FNOP no operation instruction, 558
FCOM/FCOMP/FCOMPP/FICOM/FICOMP Focus, setting, 262, 299
EAROM. See Electrically alterable ROM FORTRAN (FORmula TRANslator), 5, 45
EDO. See Extended data output compare instruction, 551 FPIC. See Field programmable
EEPROM. See Electrically erasable program- FCOMI/FUCOMI/COMIP/FUCOMIP
interconnect
mable ROM compare and load flags instruction, FPLD. See Field programmable
EFLAG register, 55, 73 545, 551
FCOS Cosine instruction, 552 logic device
Pentium microprocessor with, 739–740 FDECSTP decrement stack pointer FPREM partial remainder instruction, 559
Electrically alterable ROM (EAROM), 331 instruction, 552 Free-pointer, 60
Electrically erasable programmable ROM FDISI/FNDISI disable interrupts instruction, FRSTOR restore state instruction, 560
553 FS segment register, 57
(EEPROM), 331, 374 FDIV/FDIVP/FIDIV division instruction, 553 FSETPM set protected mode instruction,
8088/80188 (8-bit) memory interface with, FDIVR/FDIVRP/FIDIVR division reversed
instruction, 553 560
351–353 FENI/FNENI disable interrupts instruction, 554 FSIN sine instruction, 561
programmable peripheral interface FFREE free register instruction, 554 FSQRT square root instruction, 544, 561
Field programmable interconnect FSUB/FSUBP/FISUB subtraction instruction,
using, 421 (FPIC), 345
Electronic Numerical Integrator and Field programmable logic device (FPLD), 345 563
File allocation table (FAT), 280–282, 300 Functions, 208
Calculator. See ENIAC File names, 282 FWAIT wait instruction, 563
Embedded PC, 8 File pointer, 289–291 F2XM1 instruction, 550
Enable interrupt (SLI), 128 File run, 282 FXRSTOR instructions, 770
Ending address, 58 FINCSTP increment stack pointer instruction, FXSAVE instructions, 770
ENDP directive, 144, 146–147, 153 554
Enhanced graphics adapter (EGA), 525 FINIT/FNINT initialize coprocessor G bit. See Granularity bit
ENIAC (Electronic Numerical Integrator and instruction, 546–547, 555 1G-byte memory, 8
Fixed address, 378 GAL. See Gated array logic
Calculator), 4, 5, 45 Fixed-port addressing, 138–139, 153 Gate, 330
Enigma machine, 4 FLAG register, 55, 73 Gated array logic (GAL), 344
ENTER instruction, 218–219, 221 Flags, 55–57, 73 Gates, Bill, 5
EPIC (Explicitly Parallel Instruction interrupt, 457–458 GDT. See Global descriptor table
Flash memory, 17, 328, 331. See also ROM GDTR. See Global descriptor table register
Computing), 16 8088/80188 (8-bit) memory interface with, Global descriptor table (GDT), 696–700
EPROM. See Erasable programmable 351–353 Global descriptor table register (GDTR),
Flat mode memory, 72–74
read-only memory Flat model, 703 67–68
EQU directive, 144–146, 153 FLD/FILD/FBLD load data instruction, 555 Global descriptors, 63
Erasable programmable read-only memory Granularity bit (G bit), 64
Graphical user interface (GUI), 8
(EPROM), 328, 330–332, 374 Group of instructions. See Software
8088/80188 (8-bit) memory interface with, GS segment register, 57
GUI. See Graphical user interface
349–350.
pin-out of, 331
timing diagram of, 332

920 INDEX Initialization command words (ICW), Interrupt enable signal, 414, 416, 419
469–473 Interrupt mask register (IMR), 474–475
H. See Hexadecimal number Interrupt on overflow (INTO),
0H, 58 Input buffer full, 414, 419
Halt instruction (HLT), 217 Input/Output (I/O) system, 18, 23–25 215, 220, 455, 487
Handshaking, 382–386, 447 Interrupt-processed keyboard, 484–486
Hard disk memory, 518–521 80386 microprocessor’s, 687–688 Interrupt request (INTR), 414, 416, 418.435
Hardware description language (HDL), 345 address decoding for
Hardware-generated CALL, 213 8086/8088 microprocessor, 305
HDL. See Hardware description language 8-bit, 387–388 hardware generation of, 461–462
Hexadecimal data, 274–276 16-bit, 388–389 input edge-triggered using, 462
8-bit/16-bit wide I/O ports in, Interrupt request lines, 594
displaying, 274–276 Interrupt return instruction (IRET), 213–215,
reading, 274–275 389–392
Hexadecimal number (H), 31, 83. See also 32-bit wide I/O ports in, 392–395 220, 455, 487
DMA-controlled, 490–530 Interrupt service procedure (ISP), 213, 215
Binary-coded hexadecimal input devices for, 383–385 Interrupt vector table, 452, 453
HID. See Human interface device interface, 377–450 Intersegment jump, 193
Hidden refresh. See Refresh cycles isolated, 379 INTO. See Interrupt on overflow
High bank, 357 map of personal computer, 280–382 INTR. See Interrupt request
High-density floppy disk (HD), 515, memory-mapped, 379–380 Intrasegment jump, 193
output devices for, 385–386 IOPL (I/O privilege level) flag, 56
517, 529 Pentium II microprocessor’s, 767–768 IORC. See I/O read control
High memory, 59 Pentium Pro microprocessor’s, 755 IOWC. See I/O write control
HLDA, 490–491, 529 INS instruction, 135–136, 153 IRET. See Interrupt return instruction
HLT. See Halt instruction Instruction pointer, 60 ISA. See Industry standard architecture
HOLD, 490–491, 529 Int directive, 42 Isolated IO, 379
Hollerith cards, 3 INT instruction, 213, 214, 220, 455, 487 ISP. See Interrupt service procedure
Hollerith code, 3 INT3 instruction, 215, 455, 487 ISR. See In-service register
Hook, 458 Integer. See Signed integers
Horner’s algorithm, 238, 273 Integrated drive electronics (IDE), 520 Jacquard’s loom, 2
Human interface device (HID), 614 International Business Machines (IBM), JAVA, 5
Hyper-threading technology, 775 JMP. See Unconditional jump
3, 7 Jump, 192–202, 219
I (interrupt) flag, 56 Interrupt, 213–216, 220, 451–489
I/O port address, 23 conditional, 198–201, 219
I/O read control (IORC), 27, 46 80186/80188/80286 microprocessors loop, 201–202, 219
I/O system. See Input/Output (I/O) system with, 638 unconditional, 192–198, 219
I/O write control (IOWC), 27–28, 46
IBM. See International Business Machines 64-bit, 216 K, 5
iCOMP rating index, 11–12 8259A programmable controller for, Keyboard, 259–265
ICW. See Initialization command words
ID (identification) flag, 57 468–482, 487 ASCII codes returned in, 260–261
IDE. See Integrated drive electronics 82C55 keyboard, 462–465 filtering with KeyEventArgs in, 263
IDIV instruction, 169–172, 188 control, 215 reading in, 259–262
IDT. See Interrupt descriptor table daisy-chained, 466–468 setting focus in, 262, 299
IDTR. See Interrupt descriptor table register examples, 482–486 KeyEventArgs, 263
Immediate addressing, 78–80, 83–86, 107 expanding structure for, 465–468 KIP (Kilo-instructions per second), 5
IMR. See Interrupt mask register flag bits of, 457–458
IMUL instruction, 166–168, 188 hardware, 459–465 Label, 193–194, 196, 219
IN instruction, 138–140, 153, 377–379, 446 instructions, 214–215, 455 LAHF instruction, 137–138
In-service register (ISR) interrupt-processed keyboard example of, Lane, 610
Last-in, first-out (LIFO), 102
8259A using, 474–475 484–486 LCD. See Liquid crystal display
Increment instruction (INC), 157, non-maskable, 459 LDS, 127–129, 152
personal computer’s, 216 LDT. See Local descriptor table
159–160, 187 pins on microprocessor for, 459 LDTR. See Local descriptor table register
Indirect jump, 196–198, 219 protected mode operation of, 456–457 LEA, 127–128, 152
purpose of, 451–452 LEAVE instruction, 218, 221
index for, 197–198 real mode operation of, 455–456 LED. See Light-emitting diodes
register operands for, 196–197, 219 real-time clock example of, 482–484 LES, 127–129, 152
Indirect program addressing, 101–102, 105 time line on usage of, 452 LFS, 127–129, 152
Industry standard architecture (ISA), 379 trace procedure using, 457–458 LGS, 127–129, 152
8-bit bus input interface of, 598–601 vector, 213–214, 220, 452–455, 458–459 Libraries, 254–257
16-bit bus interface of, 601–602 Interrupt controller
8-bit bus output interface of, 593–598 80186/80188/80286 microprocessors with, creating, 254–257
bus, 592–602, 624 defined, 254
evolution of bus of, 593 638–643
I/O port assignments for bus of, 595 Interrupt descriptor table (IDT), 696–700
Interrupt descriptor table register (IDTR),

67–68

INDEX 921

LIFO. See Last-in, first-out address decoding for, 340–348, 374 block diagram of, 18
Light-emitting diodes (LED), 382–383, 386 addressing with R/M field, 115–116 bus/memory sizes of, 27
Linear address, 68 devices, 328–340, 373 I/O system of, 18, 23–25
Linker program, 251–252 EAROM, 331 logic operations of, 25
Liquid crystal display (LCD), 403–407 EEPROM, 331, 351–353, 374 memory of, 17–25
Little endian, 40 EPROM, 328, 330–332, 349–350, 374 personal computer using, 17–29
Load-effective address instructions, 127–130, flash, 17, 328, 331, 351–353 programming, 250–301
flat mode, 72–74 Microprocessor history, 2–17
152 floating-point number stored in, 535–536 electrical age in, 2–4
Local descriptor table (LDT), 696–700 floppy disk, 513–517, 529 mechanical age in, 2
Local descriptor table register (LDTR), 68 hard disk, 518–521 microprocessor age in, 5–7
Local descriptors, 63 high, 59 modern microprocessor in, 7–17
LOCAL directive, 259 interface, 328–376 programming advancements in, 4–5
Local variable, 258–259 Microsoft Corporation, 7
LOCK prefix, 218, 220 8088/80188 (8-bit), 349–356, 374 Microsoft MACRO assembler (MASM),
LODS instruction, 130–131, 153 8086/80186/80386SX (16-bit),
Logic operations. See Arithmetic/logic 142–151, 153
356–363, 374 ALIGN directive of, 144, 145
instructions address decoding for, 340–348, 374 ASSUME directive of, 144–146, 153
Lookup tables, 276–280, 299 devices for, 328–340, 373 controlling program flow with, 202
80386DX/80486 (32-bit), 363–366, 374 directives with, 143–147, 153
ASCII data access with, 277 Pentium - Core2 (64-bit), 366–370, 374 ENDP directive of, 144, 146–147, 153
BCD to seven-segment code conversion NOVRAM, 331 EQU directive of, 144–146, 153
optical disk, 521–522 full-segment definitions with, 148–150
with, 276–277 organization in MASM, 147–150 memory organization with, 147–150
example program using, 277–280 paging, 68–72, 74 .MODEL instruction of, 84–85, 105, 148,
XLAT instruction for, 276 Pentium 4 Core2 microprocessors use of,
Loop, 201–202, 219 153
conditional, 202 772–773 models available to, 148
.REPEAT-UNTIL, 206–207, 220 Pentium II microprocessor’s system of, ORG directive of, 144–146
.WHILE, 205–206, 220 PROC directive of, 144, 146–147, 153
Loop while equal (LOOPE), 202, 219 765–767 sample program with, 150–151
Loop while not equal (LOOPNE), 202, 219 Pentium microprocessor management of, storing data in memory segment with,
LOOPE. See Loop while equal
LOOPNE. See Loop while not equal 740–742 143–145, 153
Low bank, 357 Pentium Pro microprocessor system of, Microsoft Windows Driver Development Kit
Lower chip select, 651
LPT. See Parallel printer interface 754–755 (DDK), 223
74LS636, 354–356 pin connections to, 328–330, 373 Minimum/maximum mode
74LS138 decoder, 342–344 PROM, 330
74LS139 decoder, 344 RAM, 17, 21–22, 26, 328, 332–340, 373 8086/8088 microprocessor, 306, 323–326
LSS, 127–130, 152 8288 bus controller for, 324–326
dynamic, 328, 333–340, 370–374 MIPS (Millions of instructions per
1M-byte memory, 7 static, 328, 332–333, 373
Machine language, 4 real, 58 second), 7
RMM, 331 MMU. See Memory management unit
32-bit addressing mode using, 118 ROM, 21–22, 26, 328, 330–332, 350–351 MMX. See Multimedia extensions
immediate instruction using, 118–119 storing data with assembler to, 143–145, MOD field, 113–115, 152
MOV instruction with, 112–120 Mode of operation, 113
segment MOV instruction using, 119–120 153 Modified frequency modulation (MFM),
special mode of addressing using, 116–117 system area of, 17–18
Macros, 257–259, 299 TPA of, 17–21, 23 514–516, 519–520, 529
defined, 257 Windows systems, 22–23 RLL v., 519–520
definitions in module for, 259 XMS of, 17–18, 21–23 Modular programming, 251–259
local variables in, 258–259 Memory bank. See Bank assembler program for, 251–252
Managed program, 240 Memory management unit (MMU) EXTRN directive for, 253, 299
Masking, 176 80286 microprocessor with, 670, 675 libraries for, 254–257
MASM. See Microsoft MACRO assembler Memory-mapped IO, 379–380 linker program for, 251–252
Master file table (MFT), 280–282, 300 Memory page offset address, 70 macros for, 257–259, 299
MC6800 microprocessor, 5, 10 Memory paging, 68–72, 74 PUBLIC directive for, 253, 299
Memory, 17–25. See also Direct Memory paging mechanism, 68 Modulo 16, 59
Memory read control (MRDC), 27–28, 46, 341 Morse code, 245–246
memory access Memory write control (MWTC), 27, 46 Motorola Corporation, 5
80486 microprocessor system of, 723–726 MFM. See Modified frequency modulation Mouse, 269–271, 299
80386 microprocessor’s system of, MFT. See Master file table message handlers for, 269, 299
Microprocessor MouseDown event, 269, 271, 299
681–687, 695–702 architecture, 51–76 MouseEventArgs, 270
addition to register from, 158 arithmetic operations of, 25 MouseMove function, 269, 271, 299
assembler for, 142–151, 153

922 INDEX

MOV instruction. See also Addressing NRZ. See Non-return to zero commands for, 603
data addressing with, 77–110 NT (nested task) flag, 56 configuration space for, 605–607
data flow direction with, 78 NTFS. See New Technology File System interface for, 610
direct addressing with, 86 Number base, 30 PCI Express as, 610–612
machine language with, 112–120 Number systems, 29–35 pin-out for, 603–604
segment, 119–120 Pen drives, 517–518
segment-to-segment, 82 BCH, 33–34 Pentium - Core2 (64-bit) memory interface,
complements, 34–35
Move and sign-extend instruction. See conversion from decimal for, 32–33 366–370, 374
MOVSX (Move and sign-extend) conversion to decimal for, 31–32 Pentium 4 microprocessor, 10, 14–16, 759,
instruction digits of, 29–30
positional notation of, 30–31 771–783
Move and zero-extend instruction. See Numeric execution unit (NEU), 536 64-bit extension technology with, 776
MOVZX (Move and zero-extend) Numeric sort example program, 295–297 64-bit mode for, 120–121
instruction CPUID instruction for, 776–779
O (overflow) flag, 56 hyper-threading technology with, 775
MOVS instruction, 133–135, 151, 153 Object file, 251 memory interface with, 772–773
MOVSX (Move and sign-extend) instruction, Octal number, 29 model-specific registers with, 779–780
Octalword, 25 multiple core technology with, 776
140, 153 OCW. See Operation command words performance-monitoring register with, 780
MOVZX (Move and zero-extend) instruction, Offset address, 58 register set with, 773–774
OFFSET directive, 90 Pentium II microprocessor, 10, 12–14, 16,
140, 153 Opcode, 102, 113, 152
MRDC. See Memory read control Operands, 102 759–770, 782
MUL instruction, 166–168, 188 input/output system of, 767–768
Multimedia extensions (MMX), 531, common modifiers for, 133 memory system of, 765–767
Operation command words (OCW), 469, pin functions for, 760–765
570–581, 589 pin-out of, 761
data types with, 570–571 473–474 software changes with, 768–770
instruction set for, 571–581 Optical disk memory, 521–522
Optrex DMC 20481 LCD display, 403 CPUID instruction as, 768–769
arithmetic instructions in, 571 OR operation, 176–178, 188 FXSAVE/FXRSTOR instructions as, 770
comparison instructions in, 571–572 ORG directive, 144–146 SYSENTER/SYSEXIT instruction as,
conversion instructions in, 572 OUT instruction, 138–140, 153, 377–379, 446
data transfer instructions in, 572 Output buffer full, 416, 419 769–770
EMMS instructions in, 572 Output enable, 330 system timing with, 768
listing of, 572–580 OUTS instruction, 136, 153 Pentium III microprocessor, 10, 14, 16, 759,
logic instructions in, 572 OWORD (Octalword), 582
shift instructions in, 572 770–771, 782
programming example for, 572, 581 P (parity) flag, 55 bus for, 771
Multiple core microprocessors, 14–15 Page directory, 70–72 chip sets for, 770–771
Multiplication, 166–168, 188 Page table, 70–72 pin-out of, 771
8-bit, 167, 188 Paging Pentium microprocessor, 9–12, 729–746, 757
16-bit, 167–168 branch prediction logic for, 738
32-bit, 168 80386 microprocessor memory with, cache structure for, 738, 757
64-bit, 168, 188 713–718, 727 input/output system for, 735
ASCII adjust after, 172, 174–175, 188 memory system for, 734–735
IMUL instruction, 166–168, 188 Pentium microprocessor memory manage- new instructions in, 742–746
MUL instruction, 166–168, 188 ment with, 740 Pentium memory management for,
special immediate 16-bit, 167–168, 188
Multithreaded applications, 15–16 Paging registers, 69–70, 74 740–742
MWTC. See Memory write control PAL. See Programmable array logic pin functions for, 731–734
PAL 16L8, 547 pin-out of, 730
NAND gate decoder, 341–342 Paragraph, 58 special registers for, 738–740
Near CALL, 208, 220 Parallel printer interface (LPT), 612–614, 624 superscalar architecture for, 738, 757
Near jump, 193–195, 219 system timing for, 735–737
NEG instruction, 181–182, 188 connectors used for, 613 Pentium OverDrive, 10, 11
NEU. See Numeric execution unit details of, 612–613 Pentium Pro microprocessor, 10, 12, 16,
New Technology File System (NTFS), 280–282 pin-outs of, 612
Nibble, 5 using without ECP support, 613 746–758
NMI. See Non-maskable interrupt PASCAL, 2, 5 input/output system of, 755
No operation instruction (NOP), 217 PCB. See Peripheral control block internal structure of, 748–750
Non-maskable interrupt (NMI), 459 PCI bus (Peripheral component interconnect), memory system of, 754–755
Non-return to zero (NRZ), 515, 529 pin description for, 750–753
Nonvolatile RAM (NOVRAM), 331 19, 602–612, 624 pin-out of, 747
NOP. See No operation instruction address/data connections for, 603–605 special features of, 756
NOT instruction, 181–182, 188 BIOS for, 607–610 system timing of, 755–756
NOVRAM. See Nonvolatile RAM block diagram for computer with, 602 Pentium Xeon microprocessor, 12, 14
class codes for, 606 Performance-monitoring register, 780

INDEX 923

Peripheral component interconnect. Programmable logic array (PLA), 344 RDI destination index register, 54, 73
See PCI bus Programmable logic device (PLD), 344–348, RDX data register, 54, 73
RDY, 8284A input timing with, 320–322
Peripheral control block (PCB) 374 Read-mostly memory (RMM), 331
80186/80188/80286 microprocessors Programmable peripheral interface (PPI), Read-only memory. See ROM
with, 637–638 Read/write memory. See RAM
395–422, 447 READY input
Personal computer, microprocessor-based, description/specs for, 395–397
17–29 I/O port assignments for, 396 8086/8088 input timing with, 320–322, 326
key matrix interface using, 409–414 8086/8088 microprocessor, 305
block diagram of, 18 LCD display interfaced to, 403–407 Real memory, 58
I/O system map of, 380–382 mode 2 bidirectional operation with, Real mode operation, 58, 112
I/O system of, 18, 23–25 Real numbers, 43–44
interrupts in, 216 418–420 Real-time clock (RTC), 482–484
memory of, 17–25 mode 0 strobed input with, 414–416 80186/80188/80286 microprocessors
Physical address, 68 mode 1 strobed output with, 416–418
PIC. See 8259A programmable interrupt mode summary for, 420 example of, 647–649
pin-out diagram of, 396 Real-time operating system (RTOS), 662–670
controller port connections for, 421
PLA. See Programmable logic array programming of, 397–422 example system of, 663–666
PLD. See Programmable logic device serial EEPROM interface with, 421 initialization section of, 663
Pointer (PTR), 90 stepper motor interfaced to, 407–409 kernel of, 663
Polling. See Handshaking Programmable read-only memory (PROM), RESET section of, 663
POP instruction, 102–104, 107, 122, 124–125, threaded system of, 666–670
330 Reduced instruction set computer (RISC), 11
152 Programming model, 52–53, 73 Refresh cycles, 370–371, 373
Positional notation, 30–31 REG field, 113, 115, 152
PowerPC microprocessor, 10, 11 registers of, 53, 73 Register addressing, 78, 79, 81–83, 105–106
PPI. See Programmable peripheral interface Programming techniques, 250–301 assignments in, 115–116, 152
Printer interface, 8237 DMA controller Register indirect addressing, 79, 80,
data conversions, 271–280, 299
processed, 504–506 disk files, 280–294, 300 88–91, 107
PROC directive, 144, 146–147, 153 keyboard use, 259–265 Register relative addressing, 79, 80,
Procedures, 208–212, 220 modular, 251–259
mouse use, 269–271, 299 93–95, 107
CALL instruction with, 208–211, 220 timer use, 267–269 addressing array data with, 95
RET instruction with, 208, 211–212, 220 video display use, 259, 265–267 Register-size prefix, 113
Program control instructions, 192–222 PROM. See Programmable read-only memory Registers, 53–58, 73
BOUND, 218, 220 Protected mode addressing, 63–68, 74, 112 addition, 158, 187
CALL, 208–211, 220 program-invisible registers for, 67–68 DI, 130, 153
carry flag bit, 217, 220 selectors/descriptors in, 63–67, 74 multipurpose, 54
ENTER, 218–219, 221 Pseudo-operations, 143 paging memory, 69–70, 74
ESC, 218 PSP. See Program segment prefix Pentium 4/Core2 microprocessors use of,
flow with, 202–, 219 PTR. See Pointer
HLT, 217 PUBLIC directive, 253, 299 773–774
interrupt, 213–216, 220 PUSH instruction, 102–104, 107, program-invisible, 67–68
jump group of, 192–202, 219 programming model and, 53, 73
LEAVE, 218, 221 122–124, 152 scratchpad, 225
LOCK prefix in, 218, 220 segment, 57–58
NOP, 217 Quadword, 25, 53 SI, 130, 153
procedures as, 208–212, 220 special-purpose, 55–57
.REPEAT-UNTIL loop, 206–207, 220 R/M field, 113, 115–116, 152 Relational operators, 203
RET, 208, 211–212, 220 Radix, 238, 273 Relative jump. See Short jump
WAIT, 217, 220 Radix complements, 34 Relative program addressing, 101, 105
.WHILE loop, 205–206, 220 RAM (Read/write memory), 17, 21–22, 26. Relocatable data, 61
Program invisible, 52 Relocatable jump address, 195
Program-invisible registers, 67–68 See also Dynamic random access Relocatable program, 61
Program loader, 60 memory; Static random access REP. See Repeat prefix
Program memory-addressing modes, 100–102, memory REPE (Repeat while equal), 186, 188
Random access files, 291–293, 300 Repeat prefix (REP), 131–132, 153
105 creating, 291–292 Repeat while equal. See REPE
direct, 100–101, 105 reading, 292–293 Repeat while not equal. See REPNE
indirect, 101–102, 105 seek with, 292 REPNE (Repeat while not equal), 186, 188
relative, 101, 105 writing, 292–293 Requested privilege level (RPL), 65–66
Program segment prefix (PSP), 126 Raster line, 527–528 RET instruction (Return), 208, 211–212, 220
Program visible, 52 RAX accumulator register, 53, 54, 73 far, 211, 220
Programmable array logic (PAL), 344 RBP base pointer register, 54, 73 near, 211–212, 220
Programmable interrupt controller. See 8259A RBX base index register, 53, 54, 73
RCX count register, 54, 73
programmable interrupt controller

924 INDEX file pointer in, 289–291 STOSB (stores a byte) instruction, 131
reading file data in, 284–285 STOSD (stores a doubleword) instruction, 131
Retrace, 527–528 seek in, 289–291 STOSW (stores a word) instruction, 131
Return. See RET instruction writing to file in, 283–284 Streaming SIMD extensions (SSE), 531,
Return address, 208 Serial clock line (SCL), 353
REX (register extension), 120–121 Serial com ports, 614–617, 624 581–587, 589
RF (resume) flag, 56 baud rates allowed with, 615 control/status register of, 584
RFLAGS register, 55, 73 communication control with, 615–617 data formats for, 582
RIMM, 340 Serial data line (SDL), 353 floating-point data with, 582–583
Ring 0, 66 Set carry (STC), 217, 220 instruction set for, 583–584
Ring 3, 66 Set interrupt flag (STI), 215, 220 optimization with, 587
RIP instruction pointer register, 55, 73 Shift instructions, 182–184, 188 programming examples for, 584–587
RIP relative Addressing, 79, 81, 99 Short directive, 41 XMM registers used by, 582
RISC. See Reduced instruction set computer Short jump, 193–194, 219 String compare (CMPS), 186–188
RLL. See Run-length limited SI register, 130, 153 String comparison instructions, 186–188
RMM. See Read-mostly memory Signed integer division. See IDIV instruction String data transfers, 130–136, 153
ROM (Read-only memory), 21–22, 26. See Signed integer multiplication. See IMUL DI/SI registers for, 130, 153
direction flag for, 130, 153
also Electrically alterable ROM; instruction INS instruction for, 135–136, 153
Electrically erasable programmable Signed integers, 532–533 LODS instruction for, 130–131, 153
ROM; Erasable programmable SIMD. See Single instruction, multiple data MOVS instruction for, 133–135, 151, 153
read-only memory; Flash memory; OUTS instruction for, 136, 153
Nonvolatile RAM; Programmable extensions STOS instruction for, 131–133, 153
read-only memory; Read-mostly SIMM. See Single In-Line Memory Modules String scan (SCAS), 186, 188
memory Simple programmable logic device Strobed input, 414–416
8088/80188 (8-bit) memory interface with, Strobed output, 416–419
350–351 (SPLD), 344 SUB instruction, 162–165, 187
Root directory, 281 Single error correction/double error correction Subdirectory names, 282
Rotate instructions, 184–185, 188 Subtraction
Row address strobe, 336 (SECDED), 353 ASCII adjust after, 172, 175
RPG (Report Program Generator), 5 Single In-Line Memory Modules (SIMM), borrow with, 162, 164–165, 187
RPL. See Requested privilege level decimal adjust after, 172–173, 188
RSI source index register, 54, 73 338–339 decrement, 162–164, 187
RSP stack pointer register, 55, 73 Single instruction, multiple data extensions immediate, 162–163
RTC. See Real-time clock register, 162
RTOS. See Real-time operating system (SIMD), 531, 581 SUB instruction, 162–165, 187
Run-length limited (RLL), 519–520 Single-precision number, 43 Subtraction with borrow instruction (SBB),
SLI. See Enable interrupt
S (sign) flag, 56 SMM. See System memory-management mode 162, 164–165, 187
SAHF instruction, 137–138 Software, 25 Synchronous dynamic random access memory
SATA bus, 19 Software-generated CALL, 213
SBB. See Subtraction with borrow instruction Source, 102 (SDRAM), 371–373
Scaled-index addressing, 79, 81, 98–99, 107 Source module, 251 SYSENTER instruction, 769–770
SCAS. See String scan Special assembler directive, 90 SYSEXIT instruction, 769–770
SCL. See Serial clock line Special fully nested mode, 641 System descriptor, 63
Scratchpad registers, 225 Special-purpose computer, 4 System memory-management mode (SMM)
SDL. See Serial data line SPLD. See Simple programmable logic device
SDRAM. See Synchronous dynamic random SRAM. See Static random access memory Pentium microprocessor’s, 740–742
SS (stack) segment register, 57
access memory SSE. See Streaming SIMD extensions T (trap) flag, 56
SECDED. See Single error correction/double Stack, 60 Tabulating Machine Company, 3
Tag register, 540–541
error correction initializing, 124–126 Task state segment (TSS)
Seek Stack memory-addressing modes, 102–105
Stack segment, 89 80386 microprocessor’s, 700–702
random file access with, 292 Static memory. See Static random access TEST instruction, 180, 188
sequential file access with, 289–291 TI bit, 65
Segment address, 58–59 memory Time/date display example program, 294–295
Segment override prefix, 142, 153 Static random access memory (SRAM), 328, Timer, 267–269
Segment plus offset, 58–59
Segment registers, 57–58 332–333, 373 80186/80188/80286 microprocessors with,
Select, 330 AC characteristics of TMS4016, 334–335 643–649
Selectors, 63–67, 74 pin-out of, 333
Sequential access files, 282–291, 300 timing requirements for, 334–335 TLB. See Translation look-aside buffer
binary dump program example using, Status register, 536–540 TMS4464 DRAM
STC. See Set carry
285–289 Stepper motor, 407–409 address input timing of, 337
file creation for, 283 STI. See Set interrupt flag address multiplexer of, 337
STOS instruction, 131–133, 153 pin-out of, 334, 336
REP with, 131–132, 153

INDEX 925

TMS4016 SRAM software for USBN9604/3, 621–623 VM (virtual mode) flag, 56–57
AC characteristics of, 334–335 stop and wait flow control with, 620 Volatile memory. See Static random access
pin-out of, 333 Unmanaged program, 240
Unsigned integer division. See DIV instruction memory
TPA. See Transient program area Unsigned integer multiplication. See MUL Von Neumann machines, 4
Transient program area (TPA), 17–21,
instruction W-bit, 113, 152
23, 45 Upper chip select, 651 WAIT instruction, 217, 220
Translate instruction. See XLAT (Translate) USB. See Universal serial bus Wait state, 320–322, 326
Using namespace System::IO statement, 283 What you See is what you get (WYSIWYG), 8
instruction WIN32, 64
Translation look-aside buffer (TLB), 70, 74 Variable address, 378 Windows systems
Transparent refresh. See Refresh cycles Variable graphics array (VGA), 8, 525, 529
TSS. See Task state segment Variable-port addressing, 139, 153 memory in, 22–23
TTL RGB video displays, 523–524, 529 Verilog HDL. See VHDL Word, 25
Turing, Alan, 4 VESA local bus (VL bus), 19 WORD directive, 41, 46
VGA. See Variable graphics array Word-sized data, 40–41
Unconditional jump (JMP), 192–198, 219 VHDL (Verilog HDL), 345, 348 WORM. See Write once/read mostly
distance with, 193 Video display, 259, 265–267 Write enable, 330
far, 193, 195–196, 219 Video displays, 517–529 Write once/read mostly (WORM), 521
indirect, 196–198, 219 WYSIWYG. See What you see is what you get
intersegment, 193 analog RGB, 524–529
intrasegment, 193 EGA, 525 XADD. See Exchange and add
label with, 193–194, 196, 219 horizontal scanning rate with, 528 XCHG (Exchange) instruction, 137
near, 193–195, 219 interlaced v. noninterlaced, 528 Xeon microprocessor, 12, 14
short, 193–194, 219 raster line with, 527–528 XLAT (Translate) instruction, 138, 153
retrace with, 527–528
Unicode data, 35–37 TTL RGB, 523–524, 529 lookup tables using, 276
Universal serial bus (USB), 19, 617–624 VGA, 525, 529 XMM registers, 582
VIF (virtual interrupt ) flag, 57 XMS. See Extended memory system
bus node with, 620–621 VIP (virtual interrupt pending) flag, 57 XOR. See Exclusive-OR instruction
commands for, 618–620 Visual C++ Express. See C/C++ assembler
connector for, 617–618 VL bus. See VESA local bus Z (zero) flag, 56
data for, 617–619 Zuse, Konrad, 3–4, 45
packet types found on, 620
pin-out for, 617–624