85MHz LVDS 18 Bit COLOR HOST-LCD PANEL INTERFACE

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Version 2.10 THine

PRELIMINARY THC63LVDM63A/THC63LVDF64A

85MHz LVDS 18 Bit COLOR
HOST-LCD PANEL INTERFACE

General Description Features

The THC63LVDM63A transmitter converts 21 21:3 Data channel compression at up to
bits of CMOS/TTL data into LVDS(Low 223 Megabytes per sec throughput
Voltage Differential Signaling) data stream. A Wide Frequency Range: 20 - 85 MHz
phase-locked transmit clock is transmitted in suited for VGA,SVGA,XGA and SXGA
parallel with the data streams over a fourth Narrow bus (8 lines) reduces cable size
LVDS link. The THC63LVDM63A can be 345mV swing LVDS devices for
programmed for rising edge or falling edge Low EMI
clocks through a dedicated pin. Supports Spread Spectrum Clock Generator
The THC63LVDF64A receiver convert the On chip Input Jitter Filtering
LVDS data streams back into 21 bits of PLL requires No External Components
CMOS/TTL data with falling edge clock. At a Single 3.3V supply with 110mW(TYP)
transmit clock frequency of 85MHz, 18 bits of Low Power CMOS Design
RGB data and 3 bits of LCD timing and control Power-Down Mode
data (HSYNC, VSYNC, CNTL1) are Low profile 48 Lead TSSOP Package
transmitted at a rate of 595 Mbps per LVDS data Clock Edge Programmable for Transmitter
channel. Improved Replacement for the National
DS90CF363/364

THC63LVDM63A THC63LVDF64A

TA0-6 7 TA+/- RA+/- 7 RA0-6
7 7 RB0-6 CMOS/TTL
CMOS/TTL TB0-6 7 TB+/- RB+/-
INPUTS TC0-6 DATA RC+/- OUTPUTS
7 RC0-6
TC+/- (LVDS)
RECEIVER
(140 To 595 Mbit/ On Each PLL CLOCK OUT
LVDS Channel)
(20 To 85MHz)
TRANSMITTER PLL TCLK+/- RCLK+/- /PDWN
CLK IN
(20 To 85MHz) CLOCK RECEIVER
(LVDS) DEVICE
R/F (20 To 85MHz) THC63LVDF64A

/PDWN ----

OPTIONS

CLOCK TRANSMITTER
TRIGGERING DEVICE

www.DataShFaelleintg4EUdg.ce om THC63LVDM63A(R/F pin=GND)

Rising Edge THC63LVDM63A(R/F pin=Vcc)

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PIN OUT

TRANSMITTER DEVICE RECEIVER DEVICE

THC63LVDM63A THC63LVDF64A

TA4 1 48 TA3 RC3 1 48 VCC
VCC 2 47 TA2 RC4 2 47 RC2
TA5 3 46 GND GND 3 46 RC1
TA6 4 45 TA1 RC5 4 45 RC0
GND 5 44 TA0 RC6 5 44 GND
TB0 6 43 N/C N/C 6 43 RB6
TB1 7 42 LVDS GND LVDS GND 7 42 VCC
VCC 8 41 TA- RA- 8 41 RB5
TB2 9 40 TA+ RA+ 9 40 RB4
TB3 10 39 TB- RB- 10 39 RB3
GND 11 38 TB+ RB+ 11 38 GND
TB4 12 37 LVDS VCC LVDS VCC 12 37 RB2
TB5 13 36 LVDS GND LVDS GND 13 36 VCC
14 35 TC- RC- 14 35 RB1
R/F 15 34 TC+ RC+ 15 34 RB0
TB6 16 33 TCLK- RCLK- 16 33 RA6
TC0 17 32 TCLK+ RCLK+ 17 32 GND
GND 18 31 LVDS GND LVDS GND 18 31 RA5
TC1 19 30 PLL GND PLL GND 19 30 RA4
TC2 20 29 PLL VCC PLL VCC 20 29 RA3
TC3 21 28 PLL GND PLL GND 21 28 VCC
VCC 22 27 /PDWN /PDWN 22 27 RA2
TC4 23 26 CLK IN CLKOUT 23 26 RA1
TC5 24 25 TC6 RA0 24 25 GND
GND

PACKAGE

48 Lead Molded Thin Shrink Small Outline Package, JEDEC

12.5 ± 0.1 Unit: millimeters
48
25

8.1 ± 0.1 6.1 ± 0.1

4.05

1 24
(1.0)
1.2 MAX

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0.20 TYP
0.10 ± 0.05
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Electrical Characteristics

Vcc = 3.0 - 3.6V, Ta = -10 - +70 ˚C

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CMOS/TTL DC SPECIFICATIONS IOH=-4mA 2.0 Vcc V
IOL=4mA GND 0.8 V
VIH High Level Input Voltage 0V VIN Vcc
VIL Low Level Input Voltage R/F pin,VIH=Vcc 2.4 V
VOH High Level output Voltage VOUT=0V 0.4 V
VOL Low Level Output Voltage ± 10 µA
IIN Input Current 100 µA
IPD Pull Down Current -50 µA
IOS Output Short Circuit Current

LVDS DRIVER DC SPECIFICATIONS

VOD Differential Output Voltage RL=100Ω 250 350 450 mV
∆VOD Change in VOD between 35 mV
Complimentary Output States
1.375 V
VOC Common Mode Voltage 1.125 1.25 35 mV
∆VOC Change in VOC between
-24 mA
Complimentary Output States ±10 µA

IOS Output Short Circuit Current VOUT=0V,RL=100Ω
IOZ Output TRI-STATE Current /PDWN=0V,

VOUT=0V to Vcc

LVDS RECEIVER DC SPECIFICATIONS

VTH Differential Input High Threshold VOC=+1.2V -100 +100 mV
VTL Differential Input low Threshold ±10 mV
IIN Input Current VIN=+2.4V/ 0V µA
Vcc=3.6V

Absolute Maximum Ratings (Note 1)

Supply Voltage (Vcc) -0.3 to +4V

CMOS/TTL Input Voltage -0.3V to (Vcc + 0.3V)

CMOS/TTL Output Voltage -0.3V to (Vcc + 0.3V)

LVDS Receiver Input Voltage -0.3V to (Vcc + 0.3V)

LVDS Driver Output Voltage -0.3V to (Vcc + 0.3V)

Output Short Circuit Duration continuous

Junction Temperature +150˚C

Storage Temperature Range -65˚C to 150˚C

Lead Temperature(Soldering, 4 sec.) +260˚C

Maximum Power Dissipation @25˚C 1.4W

wwwN.Dotea1ta:"ASbhsoeleutte4MUa.xcimoumm Ratings" are those values beyond which the safety of the

device cannot be guaranteed. They are not ment to imply that the device should
be operated at these limits. The tables of "Electrical Characteristics"
specify conditions for device operation.

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Supply Current

Vcc = 3.0 - 3.6V, Ta = -10 - +70 ˚C

SYMBOL PARAMETER CONDITIONS TYP MAX UNITS

ITCCG Transmitter Supply Current RL=100Ω,CL=5pF, f=65MHz 33 41 mA
Vcc=3.3V, f=85MHz 37 45 mA
35 43 mA
16 Grayscale Pattern 39 47 mA

ITCCW Transmitter Supply Current RL=100Ω,CL=5pF, f=65MHz 10 µA
Vcc=3.3V, f=85MHz

Worst Case Pattern

ITCCS Transmitter Power Down /PDWN =0 V
Supply Current

IRCCG Receiver Supply Current CL=8pF, Vcc=3.3V, f=65MHz 33 43 mA
16 Grayscale Pattern f=85MHz 44 54 mA
IRCCW Receiver Supply Current f=65MHz 58 75 mA
CL=8pF, Vcc=3.3V, f=85MHz 70 87 mA
Worst Case Pattern
IRCCS Receiver Power Down 10 µA
Supply Current /PDWN =0 V

16 Grayscale Pattern

CLK IN
Tx0/Rx0
Tx1/Rx1
Tx2/Rx2
Tx3/Rx3
Tx4/Rx4
Tx5/Rx5
Tx6/Rx6

Worst Case Pattern

CLK IN
EVEN TxIN/RxIN
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Switching Characteristics

Vcc = 3.0 - 3.6V, Ta = -10 - +70 ˚C

SYMBOL PARAMETER MIN TYP MAX UNITS

TRANSMITTER 11.76
0.35T
t TCIT CLK IN Transition Time 0.35T 5.0 ns
T 50.0 ns
t TCP CLK IN Period 2.5 0.5T 0.65T ns
2.5 0.5T 0.65T ns
t TCH CLK IN High Time 2T/7 ns
-0.2 ns
t TCL CLK IN Low Time T/7-0.2 0.6 1.5 ns
2T/7-0.2 0.0 0.2 ns
t TCD CLK IN to TCLK+/- Delay 3T/7-0.2 T/7 T/7+0.2 ns
4T/7-0.2 2T/7 2T/7+0.2 ns
t TS TTL Data Setup to CLK IN 5T/7-0.2 3T/7 3T/7+0.2 ns
6T/7-0.2 4T/7 4T/7+0.2 ns
t TH TTL Data Hold from CLK IN 5T/7 5T/7+0.2 ns
6T/7 6T/7+0.2 ns
t LVT LVDS Transition Time ns
10.0 ms
t TOP1 Output Data Position 0 (T=11.76ns)

t TOP0 Output Data Position 1 (T=11.76ns)

t TOP6 Output Data Position 2 (T=11.76ns)

t TOP5 Output Data Position 3 (T=11.76ns)

t TOP4 Output Data Position 4 (T=11.76ns)

t TOP3 Output Data Position 5 (T=11.76ns)

t TOP2 Output Data Position 6 (T=11.76ns)

t TPLL Phase Lock Loop Set

RECEIVER

t RCP CLK OUT Period 11.76 T 50.0 ns
4T/7 ns
t RCH CLK OUT High Time 3T/7-2.5 3T/7 5.0 ns
4T/7-3.5 5T/7 5.0 ns
t RCL CLK OUT Low Time 0.4 ns
-0.4 3.0 T/7+0.4 ns
t RCD RCLK+/- to CLK OUT Delay T/7-0.4 3.0 2T/7+0.4 ns
2T/7-0.4 0.0 3T/7+0.4 ns
t RS TTL Data Setup to CLK OUT 3T/7-0.4 T/7 4T/7+0.4 ns
4T/7-0.4 2T/7 5T/7+0.4 ns
t RH TTL Data Hold from CLK OUT 5T/7-0.4 3T/7 6T/7+0.4 ns
6T/7-0.4 4T/7 10 ns
t TLH TTL Low to High Transition Time 5T/7 ns
6T/7 ns
t THL TTL High to Low Transition Time ns
ms
t RIP1 Input Data Position 0 (T=11.76ns)

t RIP0 Input Data Position 1 (T=11.76ns)

t RIP6 Input Data Position 2 (T=11.76ns)

t RIP5 Input Data Position 3 (T=11.76ns)

t RIP4 Input Data Position 4 (T=11.76ns)

t RIP3 Input Data Position 5 (T=11.76ns)

wtwRwIP.D2 ataSheInept4utUD.caotamPosition 6 (T=11.76ns)

t RPLL Phase Lock Loop Set

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AC TIMING DIAGRAMS THine

TRANSMITTER DEVICE t TCL 2.0V
0.8V
t TCP
t TCH

CLK IN 2.0V 2.0V 2.0V
0.8V
0.8V

Tx0-Tx6 2.0V t TS t TH
0.8V
DATA VALID 2.0V
0.8V

t TCD

Tx+/- Tx6 Tx5 Tx4 Tx3 Tx2 Tx1 Tx0

TCLK+ Vdiff=0V

t TOP1
t TOP0
t TOP6
t TOP5
t TOP4
t TOP3
t TOP2

Note:
1) CLK IN: for THC63LVDM63A(R/F=GND), denoted as solid line,

for THC63LVDM63A(R/F=Vcc), denoted as dashed line
2) Vdiff = (TA+) - (TA-), .... (TCLK+) - (TCLK-)

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AC TIMING DIAGRAMS

RECEIVER DEVICE

t RIP2
t RIP3
t RIP4
t RIP5
t RIP6
t RIP0
t RIP1

Rx+/- Rx6 Rx5 Rx4 Rx3 Rx2 Rx1 Rx0

RCLK+ Vdiff=0V
CLK OUT 2.0V
Rx0-Rx6 t RCD t RCL
t RCH
0.8V 0.8V
2.0V 2.0V

t RCP t RS t RH

2.0V DATA VALID 2.0V
0.8V 0.8V

Note:
1) Vdiff = (RA+) - (RA-), .... (RCLK+) - (RCLK-)

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AC TIMING DIAGRAMS

TRANSMITTER DEVICE TRANSITION TIMES

TTL Input 90% 90%
10%
CLK IN 10% t TCIT
t TCIT
LVDS Output 80%
Vdiff = (TA+)-(TA-) 80%
TA+ Vdiff 20% t LVT 20%
5pF 100Ω
t LVT
TA-
LVDS output load

RECEIVER DEVICE TRANSITION TIMES

TTL Output 80% 80%
20%
TTL Output TTL Output 20% t TLH
8pF t THL

TTL output load

PHASE LOCK LOOP SET TIME

TRANSMITTER DEVICE

/PDWN 2V 3.6V
VCC 3.0V Vdiff=0V
CLK IN
t TPLL
TCLK+/-

RECEIVER DEVICE 2V 3.6V
/PDWN 3.0V 2V
VCC
t RPLL
RCLK+/-
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CLK OUT

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TOPShine Electronics Corp. THine

5th. FI.,No. 68, Chou-Tze St.,Nei Hu Dist.,
Taipei 114, Taiwan, R. O. C.
Tel: 02-8797-3667
www.DFaaxt:a0S2h-8e7e9t74-U36.7c7om