Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 89 Subsystem Configuration Example Figure 63 illustrates a configuration example of EP3 subsystem. With this configuration, the system can process E3 and T3 electrical traffic. It can provide one group of 1:3 protection for EPE3x3 boards. The EPE3x3 board in slot 1 is the protection board; and the EPE3x3 boards in slots 2, 3, 4 are working boards. FIGURE 63. CONFIGURATION EXAMPLE OF EP3 S UBSYSTEM B I E 3 x 3 1 E S E 3 x 3 2 3 4 5 6 SCI PWR PWR 11 12 13 14 15 16 NCPI 7 8 9 10 17 Fan plug-in box 1 2 3 4 5 SC CS CS 11 12 13 14 15 16 SC NCP 6 7 8 9 10 17 O L 16 x 1 O L 16 x 1 O L 16 x 1 E P E 3 x 3 E P E 3 x 3 E P E 3 x 3 E P E 3 x 3 O L 16 x 1 E S E 3 x 3 E S E 3 x 3 E S E 3 x 3 E S E 3 x 3 E P E 3 x 3 E P T 3 x 3
ZXMP S330 (V1.3) Hardware Descriptions 90 Confidential and Proprietary Information of ZTE CORPORATION EOS Subsystem Overview Provides Ethernet electrical interfaces or Ethernet optical interfaces. Provides 1:N (N≤5) protection for Ethernet processor board that processes Ethernet electrical traffic. Connects the traffic between LANs, and the traffic between LAN and WAN, through the SDH system. The EOS subsystem comprises SFEx6, EIFEx4, OIS1x4, and BIFE boards. Different board combinations can implement different functions, as listed in Table 50. T ABLE 50. C OMBINATIONS OF B OARDS IN EOS S UBSYSTEM Function Boards Involved Remarks Process Ethernet electrical traffic SFEx6 and EIFEx4 - Provide 1:N (N≤5) protection for SFEx6 board that processes Ethernet electrical traffic SFEx6, EIFEx4, and BIFE - Process Ethernet optical traffic SFEx6 and OIS1x4 Provides no protection for SFEx6 board that processes Ethernet optical traffic Note: ZXMP S330 supports at most two groups of 1:N (N≤5) protection for SFEx6 boards that process Ethernet electrical traffic. Subsystem Functions Composition
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 91 The grey part in Figure 64 shows the positions of boards in EOS subsystem. Table 51 lists the available slots for the boards. FIGURE 64. EOS S UBSYSTEM B OARD P OSITIONS Service interface board Service interface board Service interface board Service interface board Service interface board Service interface board PWR Service interface board Service interface board Service interface board Service interface board Service interface board SCI PWR Service interface board NCPI Service board CS Service board Service board Service board Service board Service board CS Service board Service board Service board Service board Service board SC SC Service board NCP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 T ABLE 51. AVAILABLE SLOTS OF B OARDS IN EOS S UBSYSTEM Board ID Available Slots Remarks SFEx6 Lower-layer service board slots 1 to 6 and slots 11 to 16 The protection board can be inserted in any slot of lowerlayer service board slots 3 to 6 and slots 11 to 14. EIFEx4, OIS1x4 Upper-layer service interface board slots 1 to 6 and slots 11 to 16. - BIFE Upper-layer service interface board slots 3 to 6 and slots 11 to 14. It is used when the 1:N (N≤5) protection is required for SFEx6 boards that process Ethernet electrical traffic. It is inserted in the service interface board slot corresponding to the protection SFEx6 board. SFEx6 Board SFEx6 board is the smart fast Ethernet board. It implements switching, mapping, and demapping of traffic between Ethernet interfaces. It has the following functions: Supports four user ports (LAN interfaces) at the user side. Can process four channels of optical or electrical Ethernet traffic. Optical interfaces are provided by the OIS1x4 board, and electrical interfaces are provided by EIFEx4 board. Position in Subrack Functions
ZXMP S330 (V1.3) Hardware Descriptions 92 Confidential and Proprietary Information of ZTE CORPORATION Provides six system ports (WAN interfaces) at the system side, and each with bandwidth of N×2.176 M. f Each WAN interface can be allocated with one to forty-six VC-12s, i.e., 2 M to 100 M, using virtual concatenation method as per the requirement. f Up to 252 VC-12s can be allocated to all the WAN interfaces at the system side. f Traffic of any WAN interface at the system side is carried by N (N= 1 to 46) bound VC-12s. f The bindings are configured in the EMS. Multiple bound VC-12s are mapped into VC-4 using the virtual concatenation method. Four LAN interfaces (user ports) can switch between each other at the L2 (the second layer of OSI model) line rate. In the transparent transmission mode, the four LAN interfaces and the first to fourth WAN interfaces can implement pure transparent transmission of fixed connections. Supports two VLAN modes: port-based VLAN and TAG-based VLAN. f All the ports together support 4094 VLAN IDs. f In the EMS, user can configure VLAN, flow control, address learning, spanning tree, QoS, and Trunk. Drops timeslots from AU bus, and maps traffic into the corresponding AU timeslots. Provides path protection for traffic. Extracts/inserts path overheads. Figure 65 shows the SFEx6 board functional blocks. FIGURE 65. F UNCTIONAL BLOCK DIAGRAM OF SFEX6 B OARD Traffic processing unit Control unit Clock allocation unit Power supply unit System clock, frame head L2 switching unit Ethernet interface unit Optical/electrical interface board Functional Blocks
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 93 Table 52 describes the functional blocks. T ABLE 52. DESCRIPTIONS OF SFEX6 B OARD F UNCTIONAL BLOCKS Functional Block Functions L2 switching unit Implements layer-2 switching between user port and system port. Ethernet interface unit Connects L2 switching unit with optical interface board OIS1x4 or electrical interface board EIFEx4. Traffic processing unit Drops timeslots from AU bus, recovers the virtual concatenation, deframes to extract Ethernet traffic and submits it to the L2 switching unit for processing. Maps Ethernet traffic to the corresponding AU timeslot through GFP packet encapsulation. Implements path protection for traffic. Extracts/inserts path overheads. Clock allocation unit Allocates system clock to the clock required by the board itself. Notifies SC board about clock alarm. Control unit Communicates the NCP board and other boards. Supports online upgrade of the board software. Power supply unit Filters and distributes the power required by the board itself Note: User port refers to physical port connected to the local Ethernet service user. System port refers to internal Ethernet logical port connected with SDH.
ZXMP S330 (V1.3) Hardware Descriptions 94 Confidential and Proprietary Information of ZTE CORPORATION SFEx6 board front panel is shown in Figure 66. FIGURE 66. SFEX6 B OARD F RONT P ANEL 1. Running status indicator (RUN) 2. Master/standby indicator (M/S) 3. Alarm indicator (ALM) There are three indicators on the front panel, which are in turn the RUN (green) indicator, the M/S (green) indicator, and the ALM (red) indicator from top to bottom. M/S indicator is ON if the board is in active status; it is OFF if the board is in standby status. Table 53 lists possible status of the RUN and ALM indicators. T ABLE 53. DESCRIPTIONS OF RUN AND ALM I NDICATORS RUN Status ALM Status Meaning Flickers at 1 Hz periodically Constantly off Running normally Flickers at 1 Hz periodically Constantly on Flickers at 1 Hz periodically Flickers at 1 Hz periodically Constantly on Flickers at 5 Hz periodically Constantly on Flickers at 1 Hz periodically Flickers at 5 Hz periodically Flickers at 5 Hz periodically Flickers at 5 Hz periodically Flickers at 1 Hz periodically Flickers at 5 Hz periodically Constantly on Fault or alarm occurs during running None Front Panel Indicators Interface
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 95 Refer to the Overview section of EOS subsystem. EIFEx4 Board Provides four Ethernet electrical interface pairs. When 1:N (N≤5) protection for SFEx6 board is needed, EIFEx4 board works with BIFE board to implement the protection. When 1:N (N≤5) protection for SFEx6 board is not needed, EIFEx4 board only provides Ethernet electrical interfaces. At the receive side, EIFEx4 board receives Ethernet electrical signal from the outside, extracts the electrical signal, and then sends the signal to SFEx6 board via the motherboard for processing. At the transmit side, EIFEx4 board receives the signal sent by SFEx6 board via the motherboard, and then sends the signal to the outside. In the case of 1:N (N≤5) protection for SFEx6 board, EIFEx4 board determines whether to send the signal to the working SFEx6 board or to the protection SFEx6 board according to the control signal from CS board. None None The interfaces on the EIFEx4 board are Ethernet electrical interfaces of RJ45 sockets, as shown in Figure 67, with ascending numberings from top to bottom. FIGURE 67. I NTERFACES OF EIFEX4 B OARD 1. Ethernet electrical interfaces Position in Subrack Functions Working Principle Front Panel Indicator Interfaces
ZXMP S330 (V1.3) Hardware Descriptions 96 Confidential and Proprietary Information of ZTE CORPORATION The electrical interfaces have the following features: Support the 10 M/100 M adaptive Ethernet port and comply with the IEEE 802.3 Recommendation Support the auto-negotiation, duplex, and semi-duplex work modes with transmission distance not less than 100 m. A 100 M port needs to use unshielded twisted-pair above CAT5, and a 10 M port needs to use unshielded twisted-pair above CAT3. Refer to the Overview section of EOS subsystem. BIFE Board BIFE board is the bridge interface board. It has the following functions: Functions as a bridge between the protection SFEx6 board and the interface switching board (EIFEx4) corresponding to the faulty SFEx6 board. Used only when 1:N (N≤5) protection for SFEx6 board is required. Inserted in the service interface board slot corresponding to the protection SFEx6 board. When fault occurs to a working SFEx6 board, according to the control signal sent by CS board, BIFE board bridges the signals sent/received by the EIFEx4 board which corresponds to the faulty SFEx6 board to the protection SFEx6 board for processing. None None None Refer to the Overview section of EOS subsystem. OIS1x4 Board OIS1x4 board is the optical interface board. It has the following functions: Provides the service processing board (SFEx6 or AP1x4 board) with four STM-1 optical receive interfaces and four STM-1 optical transmit interfaces. Optical transmit interfaces can shut down the laser. Position in Subrack Functions Working Principle Front Panel Indicator Interface Position in Subrack Functions
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 97 At the receive side, OIS1x4 board receives optical signal inputted from the outside. Then it converts the optical signal into electrical signal and extracts the line signal. Finally, it sends the processed electrical signal to the service processing board via the motherboard for processing. At the transmit side, OIS1x4 board receives electrical signal sent by the service processing board via the motherboard. Then, it converts the electrical signal into optical signal. Finally, it transmits the optical signal to the outside. None None The interfaces on the OIS1x4 board are Ethernet optical interfaces with LC/PC connectors, as shown in Figure 68, with the ascending numberings from top to bottom. FIGURE 68. I NTERFACES OF OIS1X4 B OARD 1. Ethernet optical interfaces The optical interfaces employ the SFP optical module. When working as Ethernet optical interfaces, they support the 100 M duplex work mode. Refer to the Overview section of EOS subsystem. Working Principle Front Panel Indicator Interfaces Position in Subrack
ZXMP S330 (V1.3) Hardware Descriptions 98 Confidential and Proprietary Information of ZTE CORPORATION Subsystem Configuration Example Figure 69 shows a configuration example of EOS subsystem. With this configuration, the system can process 100 M Ethernet optical traffic. It can provide one group of 1:3 protection for SFEx6 boards. The SFEx6 board in slot 3 is the protection board; and the SFEx6 boards in slots 1, 2, 4 are working boards. FIGURE 69. CONFIGURATION EXAMPLE FOR EOS S UBSYSTEM 1 E I F E x 4 2 3 4 5 6 SCI PWR PWR 11 12 13 14 15 16 NCPI 7 8 9 10 17 Fan plug-in box 1 2 3 4 5 SC CS CS 11 12 13 14 15 16 SC NCP 6 7 8 9 10 17 O L 16 x 1 O L 16 x 1 O L 16 x 1 S F E x 6 O L 16 x 1 S F E x 6 S F E x 6 S F E x 6 S F E x 6 S F E x 6 E I F E x 4 O I S 1 x 4 O I S 1 x 4 E I F E x 4 B I F E
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 99 ATM Subsystem Overview ATM subsystem converges or aggregates ATM traffic to SDH transmission network. It comprises AP1x4 board and OIS1x4 board. Figure 70 illustrates ATM subsystem board positions in the subrack. FIGURE 70. ATM S UBSYSTEM B OARD P OSITIONSService interface board Service interface board Service interface board Service interface board Service interface board Service interface board PWR Service interface board Service interface board Service interface board Service interface board Service interface board SCI PWR Service interface board NCPI Service board CS Service board Service board Service board Service board Service board CS Service board Service board Service board Service board Service board SC SC Service board NCP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Slots for AP1x4 board: slots 1 to 6 and slots 11 to 16 at subrack lower layer. Slot for OIS1x4 board: upper-layer service interface board slot corresponding to AP1x4 board. AP1x4 Board AP1x4 board is the ATM processor board. It has the following functions: Provides four 155 Mbit/s optical interfaces at the ATM side, and four 155 Mbit/s non-concatenated data flows at the system side. User can select one to four VC-4 channels to transmit ATM traffic. It can extract the line clock which can serve as the clock source for equipment. Subsystem Functions Composition Position in Subrack Functions
ZXMP S330 (V1.3) Hardware Descriptions 100 Confidential and Proprietary Information of ZTE CORPORATION Supports four ATM traffic types: Constant Bit Rate (CBR) traffic, real-time Variable Bit Rate (rt-VBR) traffic, non realtime Variable Bit Rate (nrt-VBR) traffic, and Unspecified Bit Rate (UBR) traffic. Supports VP/VC local exchange. Supports VP protection switching upon alarms such as VPAIS, LOS, LOF, OOF, LAIS, and LCD. Figure 71 shows the functional blocks of AP1x4 board. FIGURE 71. F UNCTIONAL BLOCK DIAGRAM OF AP1X4 B OARD CS board Clock processing unit ATM traffic processing unit Control unit SC board ATM traffic Ethernet interface (for debugging, or communication with maintenance console) OIS1x4 board Table 54 describes the functional blocks. T ABLE 54. DESCRIPTION OF AP1X4 B OARD F UNCTIONAL BLOCKS Functional Block Functions ATM traffic processing unit Processes ATM traffic: At the receive side, it receives the 155 Mbit/s electrical signal from OIS1x4 board, separates the ATM cell, converts the ATM traffic into STM-1 frame, and sends STM-1 frame to CS board. At the transmit side, it receives ATM traffic from CS board, synthesizes it into ATM cell, and sends the ATM cell to OIS1x4 board for output. Restores clock: Uses the system clock from the clock processing unit as reference, and restores the synchronization clock from the received optical signals. Converts between buses: Implements the conversion between the ATM bus and the traffic bus. Clock processing unit Receives clock signal from SC board and sends it to ATM traffic processing unit to serve as the receive reference of line traffic and as the synchronization clock for data transmission Functional Blocks
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 101 Functional Block Functions Control unit Implements initialization and real-time monitoring of the board, processes the EMS commands and reports current alarms of the board. Provides interfaces and channels to communicate with NCP board. In addition, it provides a 10 M Ethernet interface for debugging or communication with the maintenance console. Figure 72 shows the AP1x4 board front panel. FIGURE 72. AP1X4 B OARD F RONT P ANEL 1. Running status indicator (RUN) 2. Work indicator (M/S) 3. Alarm indicator (ALM) There are three indicators on the front panel, which are in turn the RUN (green) indicator, the M/S (green) indicator, and the ALM (red) indicator from top to bottom. The M/S indicator is ON if the board is running normally. Front Panel Indicators
ZXMP S330 (V1.3) Hardware Descriptions 102 Confidential and Proprietary Information of ZTE CORPORATION Table 55 lists possible status of the RUN and ALM indicators. T ABLE 55. DESCRIPTIONS OF RUN AND ALM I NDICATORS RUN Status ALM Status Meaning Flickers at 1 Hz periodically Constantly off Running normally Flickers at 1 Hz periodically Constantly on Flickers at 1 Hz periodically Flickers at 1 Hz periodically Constantly on Flickers at 5 Hz periodically Constantly on Flickers at 1 Hz periodically Flickers at 5 Hz periodically Flickers at 5 Hz periodically Flickers at 5 Hz periodically Flickers at 1 Hz periodically Flickers at 5 Hz periodically Constantly on Fault or alarm occurs during running None Refer to the Overview section of the ATM subsystem. For information about OIS1x4 board, refer to the OIS1x4 Board section of EOS subsystem. Subsystem Configuration Example Figure 73 shows a configuration example of ATM subsystem. With this configuration, the system can process ATM traffic. FIGURE 73. CONFIGURATION EXAMPLE OF ATM S UBSYSTEM 1 2 3 4 5 6 SCI PWR PER 11 12 13 14 15 16 NCPI 7 8 9 10 17 Fan plug-in box 1 2 3 4 5 SC CS CS 11 12 13 14 15 16 SC NCP 6 7 8 9 10 17 O L 16 x 1 O L 16 x 1 O L 16 x 1 O L 16 x 1 A P 1 x 4 O I S 1 x 4 Interface Position in Subrack Related Information
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 103 RPR Subsystem Overview Maps Ethernet traffic to RPR. Implements the unique functions of RPR. Uses the channel bandwidth resource of SDH/MSTP ring network to provide the dual-ring topology required by RPR, and to interconnect the rings. RPR subsystem comprises RSEB, EIFEx4, and OIS1x4 boards. Different board combinations can implement different functions, as listed in Table 56. T ABLE 56. C OMBINATIONS OF RPR S UBSYSTEM B OARDS Function Boards Involved Process RPR traffic (GE optical interface, FE electrical interface) RSEB and EIFEx4 Process RPR service (GE optical interface, FE optical interface) RSEB and OIS1x4 Note: EIFEx4 board provides RSEB board with electrical interfaces. OIS1x4 board provides RSEB board with optical interfaces. Refer to the EIFEx4 Board section and the OIS1x4 Board section for details about these two boards. The grey part in Figure 74 shows the positions of boards in RPR subsystem. FIGURE 74. RPR S UBSYSTEM B OARD P OSITIONS Service interface board Service interface board Service interface board Service interface board Service interface board Service interface board PWR Service interface board Service interface board Service interface board Service interface board Service interface board SCI PWR Service interface board NCPI Service board CS Service board Service board Service board Service board Service board CS Service board Service board Service board Service board Service board SC SC Service board NCP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Subsystem Functions Composition Position in Subrack
ZXMP S330 (V1.3) Hardware Descriptions 104 Confidential and Proprietary Information of ZTE CORPORATION Slots for RSEB board: slots 1 ~ 6 and 11 ~ 16 for service board at subrack lower layer. Slots for EIFEx4/OIS1x4 board: upper-layer service interface board slot corresponding to RSEB board. RSEB Board Supports the Q in Q identification; uses the outmost 802.1Q identifier as the VLAN identifier to isolate users; participates in learning, searching, and isolating traffic on the ring network. Supports different users by identifying them with VID (VLAN ID). Every user can have multiple VLAN IDs, so that he can be completely isolated not only at local site but also between different sites, and thus satisfies the requirement of different user for data security. Every user can have traffic of different priorities (including class A, B, and C). And VLAN ID varies with the traffic class. The bandwidth and peak-value rate of traffic with a certain priority can be configured. Supports the fairness algorithm. Supports the topology discovery and protection function, and passthrough mode. Supports the configuration of EMS, query of alarm and performance, and other queries (including port running status and RPR ring topology relation diagram). The RPR ring bandwidth can be configure; supports VC4-xv and VC3-xv virtual concatenation; supports the bandwidthadjustable RPR ring with granularity of VC-4. Supports the Bypass RPR MAC function: traffic is only switched by Ethernet and is not switched by RPR MAC. There are two kinds of RSEB board: RSEB-RPR and RSEBEOS. f RSEB-RPR board is the ordinary RSEB board. It provides the RPR networking function. f RSEB-EOS board implements the pure EOS function with two GE interfaces (RPR system ports) by using Bypass RPR MAC switching. Functions
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 105 The functional block diagram of RSEB board is shown in Figure 75. FIGURE 75. F UNCTIONAL BLOCK DIAGRAM OF RSEB BOARD RPR p ro ce s sing unit (RPR MAC) Span 1 Span 2 802 .3 Eth e rne t switching u nit Lo ca l tra ffic GE/FE in te rfa ce s EO S unit (POS/ EO S) EO S s ys te m p o rt FE in te rfa ce RPR s ys tem po rt (VCG RPR SP AN p o rt) VC G (EO S) p o rt Acce s s side System side GE in te rfa ce ... Ethernet traffic accesses to RPR network through four FE interfaces, two GE interfaces, or four EOS system ports. Traffic at these interfaces/ports is aggregated to the system GE interface (RPR system port) via the Ethernet switching unit, and then is sent to the RPR processing unit to implement all the functions of the RPR MAC adaptation layer. Refer to Appendix A Terminologies for the illustrations of RPR system port, VCG (RPR Span) port, and EOS system port. The functional blocks of RSEB board are described in Table 57. T ABLE 57. F UNCTIONAL BLOCKS OF RSEB B OARD Functional Block Functions 802.3 Ethernet switching unit Implements the switching and aggregate of traffic among user ports, RPR system ports, and EOS system ports: Aggregates traffic of user port and EOS system port to RPR system port Receives frames from RPR system port and allocates them to various user ports or EOS system ports RPR processing unit Implements all the functions of RPR MAC adaptation layer, classifies the traffic, limits the rate, and determines the route. It implements all the RPR MAC functions described in IEEE 802.17 Recommendation, adjusts the bandwidth using fairness algorithm, forwards traffic, and performs protection. In order to improve the bandwidth of local traffic added to the ring, 802.3 Ethernet switching unit and RPR processing unit are connected through two GE interfaces, and the two units balance the traffic between the two GE interfaces according to the configured VLAN ID. Functional Blocks
ZXMP S330 (V1.3) Hardware Descriptions 106 Confidential and Proprietary Information of ZTE CORPORATION Functional Block Functions EOS unit Provides the RPR MAC with two ring ports for adapting RPR data frame onto SDH physical layer; provides the GFP encapsulation, VC-4 virtual container; supports virtual concatenation, with the maximum bandwidth of 2.5 Gbit/s (16×VC-4) Provides the 802.3 Ethernet switching unit with EOS function to process traffic on RPR ring or to aggregate Ethernet traffic; provides four system ports, GFP encapsulation, VC-12 virtual container; supports virtual concatenation, LCAS protocol, with the system total bandwidth of 155 Mbit/s (63×VC-12) The interfaces provided by EOS unit to the outside are 77 Mbit/s AU-4 buses (16 groups in total) The front panel of RSEB board is shown in Figure 76. FIGURE 76. F RONT P ANEL OF RSEB B OARD 1. Indicators 2. GE optical interface pair 1 3. GE optical interface pair 2 4. Laser warning sign 5. Laser level sign There are five indicators on RSEB front panel: RUN: Running status indicator. It is green. It flickers slowly and periodically if the board runs normally. M/S indicator: Work indicator. It is green. It is constantly ON if the board runs normally. ALM indicator: Alarm indicator. It is red. It is constantly OFF if the board has no alarm; otherwise, it is constantly ON. Front Panel Indicators
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 107 LA1: GE optical interface status indicator. It is green. It indicates the status of the first GE optical interface pair. The indicator is constantly ON if the optical interface pair is in LINK status. The indicator flickers if the optical interface pair is transmitting or receiving packet. LA2: GE optical interface status indicator. It is green. It indicates the status of the second GE optical interface pair. The indicator is constantly ON if the optical interface pair is in LINK status. The indicator flickers if the optical interface pair is transmitting or receiving packet. There are two GE optical receive interfaces and two GE optical transmit interfaces on RSEB front panel. Their connectors are all LC/PC type. The laser warning sign warns the operator not to look straight at optical interface when plugging/unplugging fiber pigtail, lest eyes would be hurt. The laser level sign marks the laser level. Refer to the EIFEx4 Board section and the OIS1x4 Board section for details about these two boards. Subsystem Configuration Example Figure 77 shows a configuration example of RPR subsystem. With this configuration, the RPR system can process RPR traffic. FIGURE 77. CONFIGURATION EXAMPLE OF RPR S UBSYSTEM 1 2 3 4 5 6 S C I 11 12 13 14 15 16 N C P I P W R P W R 7 8 9 10 17 Fan plug-in box 1 2 3 4 5 S C C S C S 11 12 13 14 15 16 N C P S C 6 7 8 9 10 17 O L 16 x 1 O I S 1 x 4 R S E B O L 16 x 1 O L 16 x 1 Interfaces and Signs Related Information
ZXMP S330 (V1.3) Hardware Descriptions 108 Confidential and Proprietary Information of ZTE CORPORATION PWR Board PWR board is the power supply board. It has the following functions: Provides power to subrack. Supports 1+1 hot backup. Can prevent reverse connection of power supply Detects over/under-voltage and board-in-position signals. PWR board consists of four units: over-voltage/over-current protection unit with input lightning protection and reverse connection protection features, filter unit, isolated output unit, and voltage monitor unit. The power distribution box outputs the -48 V power supply to PWR board via air switch. PWR board filters out EMI and ripples using filter circuit, and then supplies the power to subrack. The grey part in Figure 78 shows the PWR board positions in subrack. PWR boards can be inserted in slot 8 and slot 9 at upper layer of subrack. FIGURE 78. PWR B OARD P OSITIONS IN S UBRACKService interface board Service interface board Service interface board Service interface board Service interface board Service interface board PWR Service interface board Service interface board Service interface board Service interface board Service interface board SCI PWR Service interface board NCPI Service board CS Service board Service board Service board Service board Service board CS Service board Service board Service board Service board Service board SC SC Service board NCP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Functions Working Principle Position in Subrack
Chapter 3 - Boards Confidential and Proprietary Information of ZTE CORPORATION 109 Figure 79 illustrates the PWR board front panel. FIGURE 79. PWR B OARD F RONT P ANEL 1. Power input interface PWR board provides a power input interface, which uses a Dtype connector with three jacks. The signals of these jacks from top to bottom are: -48 VGND, PGND, -48 V. -48 VGND is connected to the -48 VGND busbar of power distribution box. PGND is connected to the copper busbar at the side of cabinet. -48 V is connected to the output terminal of air switch. Front Panel Interface
Confidential and Proprietary Information of ZTE CORPORATION 111 Appendix A Terminologies 1. EDFA If an ordinary optical fiber is doped with some other element such as erbium or praseodymium, it would be able to amplify the laser at a certain waveband. The full name of EDFA is Erbium Doped Fiber Amplifier. At the heart of the EDFA, the fiber is doped with erbium, a rare earth element that happens to have the appropriate energy levels in its atomic structure for amplifying light at 1550 nm. When light at 1550 nm travels through the erbium doped fiber, it causes stimulated emission. In this way, the 1550 nm optical input signal gains strength. The basic components of EDFA include the gain medium (erbium doped fiber of various types), pump source, optical passive components (optical isolator, optical multiplexer, optical demultiplexer, optical fiber connector), control unit and control interface. Among which the optical isolator prevents reverse light from influencing the EDFA; the optical fiber connector facilitates the connections among EDFA, communication system, and optical lines; the optical coupler separates part of signals from the input and output optical lines, and sends these signals to the optical monitor. 2. RPR system port It is also known as RPR port. For user data frames, the RPR ring network only has one entrance/exit. The RPR system port is actually a channel for RPR ring network to add/drop the user traffic. The traffic received at the RPR system port and sent to the user port is called the dropped traffic; while the traffic received at the user port and sent to the RPR system port is called the added traffic.
ZXMP S330 (V1.3) Hardware Descriptions 112 Confidential and Proprietary Information of ZTE CORPORATION 3. RPR Span port It is also known as VCG (RPR Span) port. It refers to the port that supports reception/transmission of RPR frames from the 802.17 network. RPR has a dual-ring structure, which is similar to the topology of SDH bidirectional MS ring. It consists of two ringlets with opposite directions, among which the clockwise ringlet is called ring 0 and the counterclockwise ringlet is called ringlet 1. Each RPR ringlet must provide two Span ports: Span1 port and Span2 port. The Span ports implement the encapsulation/unencapsulation and mapping/demapping between RPR frames and SDH VCG. Each Span port corresponds to one VCG, with the maximum bandwidth tunable and the granularity being VC-3 or VC-4. The Span1 port of every equipment is connected with the Span2 port of its adjacent equipment to build the RPR ring network. The relationship between the board’s Span ports and the ring network is shown in Figure 80. FIGURE 80. RELATIONSHIP BETWEEN THE B OARD ’S SPAN P ORTS AND THE RING NETWORK Span1 Node Span2 Add Drop Transit Ringlet 0 Ringlet 1 Ringlet 1 Ringlet 0 4. EOS system port It is also known as VCG (EOS) port. It refers to the port that supports the reception/transmission of Ethernet frames from the 802.3 network, This port is similar to the system port on the EOS board of SFE series. It receives the Ethernet frames and encapsulates them, then maps them to the VCG. Each system port corresponds to one VCG, with the maximum bandwidth of FE. In networking, the EOS system ports can connect with each other or connect with the system port on EOS board of SFE series.
Appendix A - Terminologies Confidential and Proprietary Information of ZTE CORPORATION 113 5. 802.1Q identifier In Ethernet, the 802.1Q identifier is an ID to isolate users. It is supported by data equipment with relatively powerful function such as switches and routers. This ID includes a 3-bit QoS ID (also called 802.1p priority) and a 12-bit VID. QoS ID is used to assign the frame priority (totally there are 8 priorities), so that the frame can be transferred prior to other frame with less priority during switching. The 12-bit VID is used to isolate users. Users with different VIDs belong to different broadcast areas and cannot directly communicate with each other unless transited by the third layer equipment. 6. Q in Q It is 802.1Q in 802.1Q. It refers to adding one layer of 802.1Q ID in front of the existed user 802.1Q ID, and isolating users of the same operator without modifying the original user ID, thus implementing the two-layer isolation (the user uses one isolation layer, and the operator uses the other one). This method is also called the Vlan Stack or Double Vlan.
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Confidential and Proprietary Information of ZTE CORPORATION 115 Appendix B Abbreviations Abbreviation Full Name A AIS Alarm Indication Signal APS Automatic Protection Switching AU Administrative Unit AUG Administrative Unit Group AU-n Administrative Unit, level n AU-PTR Administrative Unit Pointer C CBR Constant Bit Rate C-n Container, level n CPU Central Processing Unit CRC Cyclic Redundancy Check CV Coding Violation D DCC Data Communications Channel E ECC Embedded Control Channel EDFA Erbium Doped Fiber Amplifier EMI Electro Magnetic Interference EOS Ethernet Over SDH F FAS Frame Alignment Signal FE Fast Ethernet FPGA Field Programmable Gate Array G GE Gigabit Ethernet
ZXMP S330 (V1.3) Hardware Descriptions 116 Confidential and Proprietary Information of ZTE CORPORATION Abbreviation Full Name GFP Generic Framing Procedure H HW Highway I IP Internet Protocol ITU-T International Telecommunication UnionTelecommunication Standardization Sector L L2 Layer 2 LAIS Line Alarm Indication Signal LAN Local Area Network LCAS Link Capacity Adjustment Scheme LCD Loss of Cell Delineation LOF Loss Of Frame LOP Loss Of Pointer LOS Loss Of Signal M MCU N Micro Control Unit NE Network Element O OOF Out of Frame P PDH Plesiochronous Digital Hierarchy PGND Protection Ground R RAI Remote Alarm Indication S SDH Synchronous Digital Hierarchy SMCC Subnetwork Management Control Center STM-N Synchronous Transport Module, level N (N=1, 4, 16, 64) T TCP Transport Control Protocol TU Tributary Unit TUG-m Tributary Unit Group, level m TU-m Tributary Unit, level m
Appendix B - Abbreviations Confidential and Proprietary Information of ZTE CORPORATION 117 Abbreviation Full Name U UBR Unspecified Bit Rate V VBR Variable Bit Rate VC Virtual Channel VC Virtual Container VCI Virtual Channel Indicator VC-n Virtual Container, level n VLAN Virtual Local Area Network VP Virtual Path VPI Virtual Path Indicator VPG Virtual Path Group
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Confidential and Proprietary Information of ZTE CORPORATION 119 Figures Figure 1. ZXMP S330 Cabinet Outlines ...................................2 Figure 2. Basic Fittings of a 2200 mm High ZXMP S330 Cabinet 3 Figure 3. Grounding Terminals and Grounding Copper Busbar of ZXMP S330 Cabinet ............................................................5 Figure 4. Basic Configuration of ZXMP S330 Equipment............6 Figure 5. Structural Parts of ZXMP S330 ................................9 Figure 6. Subrack Structure ............................................... 11 Figure 7. Structure of Fan Plug-in Box ................................. 13 Figure 8. Structure of Fan Box............................................ 14 Figure 9. FAN Board Location in ZXMP S330 System .............. 15 Figure 10. Structure of Dustproof Unit ................................. 16 Figure 11. Structure of Power Distribution Box...................... 17 Figure 12. Jacks of DB9 (Female) Socket ............................. 18 Figure 13. Board Slots of ZXMP S330 Subrack ...................... 24 Figure 14. Typical Structures of Electrical Interface/Switching Board and Optical Interface Board ...................................... 26 Figure 15. Typical Structures of Functional/Service Board....... 27 Figure 16. Motherboard Diagram ........................................ 28 Figure 17. Indicator Board Alarm Interface........................... 29 Figure 18. Positions of NCP and NCPI Boards in ZXMP S330 Subrack .......................................................................... 31 Figure 19. Connections Between NCP Unit and Other Boards... 31 Figure 20. Functional Block Diagram of NCP Board ................ 33 Figure 21. NCP Board Front Panel ....................................... 35 Figure 22. Functional Block Diagram of NCPI Board ............... 37 Figure 23. NCPI Board Interfaces ........................................ 38 Figure 24. Position of SC Unit in Subrack ............................. 40 Figure 25. Connections Among SC Unit and Other Boards....... 40 Figure 26. Functional Block Diagram of SC Board .................. 41 Figure 27. Front Panel of SC Board...................................... 42
ZXMP S330 (V1.3) Hardware Descriptions 120 Confidential and Proprietary Information of ZTE CORPORATION Figure 28. 75 Ω SCI Board ................................................. 44 Figure 29. Connections among CS Board and Other Boards .... 46 Figure 30. Functional Block Diagram of CS Board .................. 47 Figure 31. Front Panel of CS Board ..................................... 48 Figure 32. Position of CS Boards in ZXMP S330 Subrack......... 49 Figure 33. Connections among OL16x1 Board and Other Boards ..................................................................................... 50 Figure 34. Functional Block Diagram of OL16x1 Board ........... 51 Figure 35. Front Panel of OL16x1 Board............................... 52 Figure 36. Position of OL16x1 Board in Subrack .................... 53 Figure 37. Connections among OL1/4x4 Board and Other Boards ..................................................................................... 54 Figure 38. Functional Block Diagram of OL1/4x4 Board .......... 55 Figure 39. Front Panel of OL1/4x4 Board ............................. 56 Figure 40. Position of OL1/4x4 Board in Subrack ................... 57 Figure 41. Positions of Boards in OL1/4 Subsystem ............... 59 Figure 42. Connection Relations Among the Boards in OL1/4 Subsystem ...................................................................... 60 Figure 43. Functional Block Diagram of LP1x1/LP1x2 Boards... 61 Figure 44. LP1x1/LP1x2 Board Front Panel ........................... 62 Figure 45. Functional Block Diagram of LP4x1/LP4x2 Boards... 64 Figure 46. LP4x1/LP4x2 Board Front Panel ........................... 65 Figure 47. OIS1x2/OIS4x2 Board Interfaces ......................... 67 Figure 48. ESS1x2 Board Interfaces .................................... 69 Figure 49. Configuration Example of OL1/4 Subsystem .......... 70 Figure 50. Connection Relations among OA Board and Other Boards............................................................................ 71 Figure 51. Functional Block Diagram of OA Board .................. 72 Figure 52. Front Panel of OBA Board ................................... 73 Figure 53. Available Slots of OA Board................................. 74 Figure 54. Positions of EP1 Subsystem Boards ...................... 75 Figure 55. Functional Block Diagram of EPE1x21/EPT1x21/EPE1B Boards............................................................................ 77 Figure 56. Front Panel of EPE1x21/EPT1x21/EPE1B Board ...... 78 Figure 57. ESE1x21 Board Interface .................................... 80 Figure 58. Configuration Example of EP1 Subsystem ............. 82 Figure 59. Positions of EP3 Subsystem Boards ...................... 83
Figures Confidential and Proprietary Information of ZTE CORPORATION 121 Figure 60. Functional Block Diagram of EPE3x3/EPT3x3/ EP3x3 Board ............................................................................. 85 Figure 61. Front Panel of EPE3x3/EPT3x3/EP3x3 Board .......... 86 Figure 62. ESE3x3 Board Interfaces .................................... 87 Figure 63. Configuration Example of EP3 Subsystem.............. 89 Figure 64. EOS Subsystem Board Positions .......................... 91 Figure 65. Functional Block Diagram of SFEx6 Board ............. 92 Figure 66. SFEx6 Board Front Panel .................................... 94 Figure 67. Interfaces of EIFEx4 Board.................................. 95 Figure 68. Interfaces of OIS1x4 Board ................................. 97 Figure 69. Configuration Example for EOS Subsystem............ 98 Figure 70. ATM Subsystem Board Positions .......................... 99 Figure 71. Functional Block Diagram of AP1x4 Board ........... 100 Figure 72. AP1x4 Board Front Panel .................................. 101 Figure 73. Configuration Example of ATM Subsystem ........... 102 Figure 74. RPR Subsystem Board Positions ......................... 103 Figure 75. Functional Block Diagram of RSEB Board............. 105 Figure 76. Front Panel of RSEB Board ................................ 106 Figure 77. Configuration Example of RPR Subsystem ........... 107 Figure 78. PWR Board Positions in Subrack......................... 108 Figure 79. PWR Board Front Panel..................................... 109 Figure 80. Relationship between the Board’s Span Ports and the Ring Network ................................................................. 112
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Confidential and Proprietary Information of ZTE CORPORATION 123 Tables Table 1. Chapter Summary ...................................................i Table 2. Typographical Conventions ...................................... ii Table 3. Mouse Operation Conventions ................................. iii Table 4. Cabinet Dimensions and Weights ..............................1 Table 5. ZXMP S330 Basic Fitting Descriptions ........................4 Table 6. Configuration of ZXMP S330 in a Single Cabinet..........7 Table 7. ZXMP S330 Configuration with other ZTE SDH Equipment in a Single Cabinet ..............................................7 Table 8. Dimensions and Weights of ZXMP S330 Structural Parts .......................................................................................9 Table 9. Brief Descriptions of Different Subrack Parts............. 12 Table 10. Signal Definitions of DB9 (Female) Socket .............. 18 Table 11. Units and Subsystems of ZXMP S330..................... 21 Table 12. Boards of ZXMP S330 .......................................... 22 Table 13. Description of Interfaces on the Motherboard.......... 29 Table 14. Signal Definitions of Alarm Output Interface Jacks ... 29 Table 15. Signal Definitions of Power Alarm Interface Jacks .... 30 Table 16. Description of NCP Board Functional Blocks ............ 33 Table 17. Indicators on NCP Board Front Panel ..................... 35 Table 18 Descriptions of RUN and ALM Indicators .................. 36 Table 19. Interfaces and Buttons on NCP Board Front Panel.... 36 Table 20. Description of NCPI Board Functional Blocks ........... 37 Table 21. Functions of NCPI Board Interfaces ....................... 38 Table 22. Signal Definitions of Jacks on Alarm Output Interface to Column Head Cabinet .................................................... 38 Table 23. Signal Definitions of Jacks on F1 Interface/External Alarm Input Interface........................................................ 39 Table 24. Description of SC Board Functional Blocks .............. 42 Table 25. Descriptions of RUN and ALM Indicators ................. 43 Table 26. Description of the M/S Indicator on the SC Board .... 43
ZXMP S330 (V1.3) Hardware Descriptions 124 Confidential and Proprietary Information of ZTE CORPORATION Table 27. Description of Interfaces on 75 Ω SCI Board ........... 44 Table 28. Cross-connect Capacity of CS Boards..................... 46 Table 29. Descriptions of CS Board Functional Blocks............. 47 Table 30. Descriptions of RUN and ALM Indicators ................. 48 Table 31. Functional Blocks of OL16x1 Board........................ 51 Table 32. Functional Blocks of OL1/4x4 Board ...................... 55 Table 33. Descriptions of OL1/4x4 Board Positions in ZXMP S330 Subrack .......................................................................... 57 Table 34. Board Combinations in OL1/4 Subsystem ............... 58 Table 35. Available Slots of Boards in OL1/4 Subsystem......... 59 Table 36. Description of LP1x1/LP1x2 Board Functional Blocks 61 Table 37. Descriptions of RUN and ALM Indicators ................. 63 Table 38. Description of LP4x1/LP4x2 Board Functional Blocks 64 Table 39. Descriptions of RUN and ALM Indicators ................. 65 Table 40. Description of OA Board Functional Blocks .............. 73 Table 41. Combinations of Boards in EP1 Subsystem ............. 75 Table 42. Available Slots of Boards in EP1 Subsystem ............ 76 Table 43. Description of EPE1x21/EPT1x21/EPE1B Board Functional Blocks.............................................................. 77 Table 44. Descriptions of RUN and ALM Indicators ................. 78 Table 45. Signal Definitions of Pins on ESE1x21 Board Electrical Interface ......................................................................... 80 Table 46. Combinations of Boards in EP3 Subsystem ............. 83 Table 47. Available Slots of Boards in EP3 Subsystem ............ 84 Table 48. Functional Blocks of EPE3x3/EPT3x3/EP3x3 Board ... 85 Table 49. Descriptions of RUN and ALM Indicators ................. 86 Table 50. Combinations of Boards in EOS Subsystem............. 90 Table 51. Available Slots of Boards in EOS Subsystem ........... 91 Table 52. Descriptions of SFEx6 Board Functional Blocks ........ 93 Table 53. Descriptions of RUN and ALM Indicators ................. 94 Table 54. Description of AP1x4 Board Functional Blocks ....... 100 Table 55. Descriptions of RUN and ALM Indicators ............... 102 Table 56. Combinations of RPR Subsystem Boards .............. 103 Table 57. Functional Blocks of RSEB Board ......................... 105