Wafer edge / bevel treatment of device wafers by means of CMP

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 Dresden
VDE VERLAG GMBH · Berlin-Offenbach

Wafer edge / bevel treatment of device wafers by means of CMP

Anngret Wieters, Peter Thieme

Process Development CMP, Qimonda Dresden GmbH & Co. OHG, Koenigsbruecker Str. 180
D-01099 Dresden, Germany

E- mail: anngret.wieters@qimonda.com

At wafer edge several defects are observed such as flaking, delaminating films, etch
damages, metal contaminations and particles etc. These damages and defects are
reported and known as root cause for wafer yield loss in edge regions of device wafers.
In this paper a special chemical- mechanical polishing (CMP) process was investigated
as a very effective method to reduce defect sources at wafer edge of device wafers. In
order to see the impact of bevel polish in DRAM production different positions in the
process flow with focus on front-end (FEOL) and mid-of- line (MOL) have been tested
on different technology nodes. With a bevel inspection the cleanness of the polished
bevel was determined.
In the following report we will describe the test setup and explain the test results. We
will show the effect on cleanness of bevel and entire wafer as well as the impact on
yields. Based on our observations the potentials and limitations of bevel polish in
comparison to other techniques such as plasma etch treatment or wet clean treatment for
yield enhancement will be discussed.

Keywords: Chemical- mechanical Polishing, Bevel Polish, Wafer Edge, Bevel
Inspection , Bevel Treatment, Wafer Bevel Region

1. Introduction

As semiconductor manufactures are pushing to expand the used silicon area to the geometrical
limit the influence of wafer edge on process performance of different process steps becomes
more and more important.
The wafer edge is subdivided into three regions - the top bevel, the crown (apex) and the
bottom bevel [1]. The wafer edge of prime silicon wafers is polished at wafer suppliers
facilities prior the device manufacturing process. During the device manufacturing process
several defects, damages and pollutions occur at wafer edge caused by film deposition,
etching, annealing and wafer handling. These edge defects and particles are easily transferred
to wafer front side during semiconductor processes e.g. wet bench processes. It is further
known that wafer edge is a primary source of yield lowering defects. Therefore the cleanness
at wafer edge (top and bottom) appreciates in value with respect to line width shrink.
For clearing the wafer edge a new polish technique was used. With this polish a clearing
down to wafer substrate and a smoothing of wafer edge is feasible. Edge polishing can
eliminate defects and prepare the edge for a better subsequent process yield.

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 Dresden
VDE VERLAG GMBH · Berlin-Offenbach

2. Experimental
The used bevel polisher consists of three independent polish modules including three polish
heads. Two of these polish heads are applied to clean top and bottom bevel and the third one
for polishing the notch. The head design allows a polish zone control up to 5mm on front and
back edge. The clearance of the edge defects and substances is done by an abrasive tape. The
usage of chemicals is possible, but in our work just DI water was used. After polishing the
wafer is cleaned and dried with the integrated cleaner.
To investigate the impact of bevel polish in DRAM production bevel polish was utilized
before CMP processes in front-end and mid-of line. After that all wafers got standard
processing until end of line. To characterize the defect level at wafer edge pre and post bevel
polish a bevel inspection was done. Furthermore an extended defect measurement was
performed and the polish result was reviewed with an optical microscope. Beside these we
saw over standard measurements like film thickness and step height to see if there are effects
from bevel polish.

3. Results and discussion
In our experiment bevel polish was tested at different positions in DRAM manufacturing
process flow. Different film stacks at wafer edge region have to be removed. The target of
bevel polish was to clear the wafer down to substrate at apex as well as upper and lower bevel.
In the following pictures the results of bevel polish prior shallow trench isolation chemical
mechanical polishing (STI CMP) are seen as example.

Figure 1: Typical situation at wafer edge prior to STI CMP: left side without bevel polish,
right side with bevel polish.

exposed Si

Figure 2: Optical microscope pictures of top view of wafer edge region pre (right) and post
(left) bevel polish to see exposed silicon area.

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 Dresden
VDE VERLAG GMBH · Berlin-Offenbach

The exposed silicon zone where the wafer is cleared down to silicon is about 0,5mm and an
even transition zone to the inner part of wafer was generated. The total polish zone is lower
than 1,7mm.
The results of bevel inspection right after bevel polish showed a clear reduction of bevel
defects for all bevel polished wafers for each position in process flow.

Defect count

w/o bevel polish w/ bevel polish

Figure 3: Defect count of bevel region without and with bevel polish

The bevel inspection in subsequent steps shows higher adder counts for bevel polished wafers
compared to non polished wafers but lower total bevel defect count. Due to the smooth
surface after bevel polish the bevel inspection is more sensitive to new defects generated in
subsequent process steps. In opposition to the expectations there was no impact of bevel
polish to wafer defect count visible. That means there was no increase or decrease in defect
count on wafer level seen as well as no change in defect types. Only bevel polish prior a CMP
process in mid of line module showed a reduction of defects at wafer edge region which was
not touched by the bevel polish itself. At this position in process bevel polish changes the
surface condition at bevel region. The material interfering with etch chemistry / gases of
subsequent etch process causing typical defects was removed.
The film thickness as well as step height measurements after the following CMP processes
indicating no impact of bevel polish to the CMP polish profiles.
The evaluation of the electrical results showed a clear positive effect of bevel polish on all
defect density sensitive parameters. In addition to this a clear improvement for defect
sensitive yields was obtained. The best response to bevel polish in yield was seen for chips in
wafer edge region. During our experiments it turned out that yield gain by bevel polish
reduces when base yield level increases. One possible reason might be that at a certain yield
level are less issues to repair at wafer edge.
Comparing bevel polish to other bevel treatments like bevel plasma etch it is likewise a
suitable method of cleaning the wafer edge region. In our experiments the impact of bevel
polish on wafer yields was more effective than using bevel plasma etch. Another advantage of
bevel polish is the capability of notch cleaning which is not possible with other bevel
treatments. An improvement of beve l defects was achieved with both methods. For applying
bevel polishing in device manufacturing process it has to take into account that it is not

International Conference on Planarization/CMP Technology · October 25 – 27, 2007 Dresden
VDE VERLAG GMBH · Berlin-Offenbach

suitable for open structures. The test of a wet etch treatment of bevel region was not
successful. The use of diluted chemicals was without any effect and the usage of concentrated
chemicals led to lift off issues.

4. Conclusion

With bevel polish a clearing of wafer edge regions top, bevel and bottom is possible. Bevel
polish in DRAM production is applicable at different positions in process flow in FEOL and
MOL for non opened structures. The bevel inspection afterwards showed a significant drop in
defect count at wafer edge region. Smooth surface after bevel polish allows sensitive
inspection of bevel region at later processes. A clear positive impact on defect density
sensitive electrical parameters and on wafer yields especially at wafer edge region was seen.
Further experiments will include bevel polish in synergy with bevel plasma etch to find the
optimum position in process flow and to obtain the best yield improvement.

References

[1] Alexander E. Braun, Semiconductor International, Jan. 2006