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Appendix A

Xilinx Development System Files

This appendix gives an alphabetic listing of the files used by the Xilinx development
system.

Name Type Produced By Description
BIT Data
BitGen Download bitstream file for
devices containing all of the
configuration information from the
NCD file

BGN ASCII BitGen Report file containing information
BLD ASCII about a BitGen run

NGDBuild Report file containing information
about an NGDBuild run, including
the subprocesses run by NGDBuild

DATA C File TRCE File created with the –stamp option
to TRCE that contains timing
model information

DC ASCII Synopsys FPGA Synopsys setup file containing
Compiler constraints read into the Xilinx
Development System

DLY ASCII PAR File containing delay information
for each net in a design

DRC ASCII BitGen Design Rule Check file produced
by BitGen

EDIF (various ASCII CAE vendor’s EDIF 2 EDIF netlist. The Xilinx
file extensions)
0 0 netlist writer. Development System accepts an

EDIF 2 0 0 Level 0 netlist file

EDN ASCII NGD2EDIF Default extension for an EDIF
2 0 0 netlist file

ELF ASCII Used for NetGen This file populates the Block RAMs
specified in the .bmm file.

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Name Type Produced By Description
EPL ASCII FPGA Editor
FPGA Editor command log file.
EXO Data PROMGen The EPL file keeps a record of all
FLW FPGA Editor commands executed
INI ASCII Provided with and output generated. It is used to
GYD ASCII software recover an aborted FPGA Editor
HEX session
IBS Xilinx software
PROM file in Motorola’s
JED ASCII CPLDfit EXORMAT format
LOG Hex
PROMGen File containing command
LL Command sequences for XFLOW programs

MEM ASCII IBISWriter Script that determines what FPGA
MCS Command Editor commands are performed
MDF when the FPGA Editor starts up
JEDEC CPLDfit
CPLD guide file
ASCII XFLOW
TRACE Output file from PROMGEN that
contains a hexadecimal
ASCII BitGen representation of a bitstream

ASCII User (with text Output file from IBISWriter that
Data editor) consists of a list of pins used by the
design, the signals internal to the
PROMGen device that connect to those pins,
and the IBIS buffer models for the
ASCII MAP IOBs connected to the pins

Programming file to be
downloaded to a device

Log file containing all the messages
generated during the execution of
XFLOW (xflow.log)

TRACE (macro.log)

Optional ASCII logic allocation file
with a .ll extension. The logic
allocation file indicates the
bitstream position of latches, flip-
flops, and IOB inputs and outputs.

User-edited memory file that
defines the contents of a ROM

PROM-formatted file in Intel’s
MCS-86 format

A file describing how logic was
decomposed when the design was
mapped. The MDF file is used for
guided mapping.

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Name Type Produced By Description
MFP ASCII Floorplanner
Map Floorplanner File, which is
MOD ASCII TRACE generated by the Floorplanner,
MRP ASCII MAP specified as an input file with the
MSK Data BitGen –fp option. The MFP file is
NAV XML essentially used as a guide file for
NGDBuild mapping.
NCD Data
MAP, PAR, FPGA File created with the –stamp option
NCF ASCII Editor in TRCE that contains timing
NGA Data model information
NGC Binary CAE Vendor toolset
NGD Data NetGen MAP report file containing
XST information about a technology
NGM Data NGDBuild mapper command run

MAP File used to compare relevant bit
locations when reading back
configuration data contained in an
operating Xilinx device

Report file containing information
about an NGDBuild run, including
the subprocesses run by
NGDBuild. From this file, the user
can click any linked net or instance
names to navigate back to the net or
instance in the source design.

Flat physical design database
correlated to the physical side of
the NGD in order to provide
coupling back to the user’s original
design

Vendor-specified logical
constraints files

Back-annotated mapped NCD file

Netlist file with constraint
information.

Generic Database file. This file
contains a logical description of the
design expressed both in terms of
the hierarchy used when the design
was first created and in terms of
lower-level Xilinx primitives to
which the hierarchy resolves.

File containing all of the data in the
input NGD file as well as
information on the physical design
produced by the mapping. The
NGM file is used for
back-annotation.

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Name Type Produced By Description
NGO Data Netlist Readers
NKY File containing a logical description
NLF Data BitGen of the design in terms of its original
NMC ASCII NetGen components and hierarchy

OPT Binary FPGA Editor Encryption key file
PAD
PAR ASCII XFLOW NetGen log file that contains
ASCII PAR information on the NetGen run
PCF
ASCII PAR Xilinx physical macro library file
PIN containing a physical macro
PNX ASCII MAP, FPGA Editor definition that can be instantiated
PRM into a design
ASCII NetGen
RBT ASCII CPLDfit Options file used by XFLOW
RPT
ASCII PROMGen File containing a listing of all
RCV I/O components used in the design
SCR ASCII BitGen and their associated primary pins
ASCII PIN2UCF
PAR report file containing
ASCII FPGA Editor execution information about the
ASCII PAR command run. The file shows
FPGA Editor or the steps taken as the program
XFLOW converges on a placement and
routing solution

File containing physical constraints
specified during design entry (that
is, schematics) and constraints
added by the user

Cadence signal-to-pin mapping file

File used by the IBISWriter
program to generate an IBIS model
for the implemented design.

File containing a memory map of a
PROM file showing the starting
and ending PROM address for each
BIT file loaded

“Rawbits" file consisting of ASCII
ones and zeros representing the
data in the bitstream file

Report file generated by PIN2UCF
when conflicting constraints are
discovered. The name is
pinlock.rpt.

FPGA Editor recovery file

FPGA Editor or XFLOW command
script file

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Name Type Produced By Description
SDF
SVF ASCII NetGen File containing the timing data for a
TCL design. Standard Delay Format File
TDR
TEK ASCII NetGen Assertion file written for Formality
TV equivalency checking tool
TVHD
TWR ASCII User (with text TCL script file
TWX editor)

UCF ASCII DRC Physical DRC report file
URF
Data PROMGen PROM-formatted file in
V Tektronix’s TEKHEX format
VHD
VM6 ASCII NetGen Verilog test fixture file
VXC
ASCII NetGen VHDL testbench file
XCT
ASCII TRACE Timing report file produced by
XTF TRACE

XPI XML TRACE Timing report file produced by
TRACE. From this file, the user can
click any linked net or instance
names to navigate back to the net or
instance in the source design.

ASCII User (with text User-specified logical constraints
editor) file

ASCII User (with text User-specified rules file containing
editor) information about the acceptable
netlist input files, netlist readers,
and netlist reader options

ASCII NetGen Verilog netlist

ASCII NetGen VHDL netlist

Design CPLDfit Output file from the CPLDfit

ASCII NetGen Assertion file written for
Conformal-LEC equivalence
checking tool

ASCII PARTGen File containing detailed
information about architectures
and devices

ASCII Previous releases of Xilinx netlist format file
Xilinx Development
System

ASCII PAR File containing PAR run summary

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Appendix B

EDIF2NGD, and NGDBuild

EDIF2NGD This appendix describes the netlist reader program, EDIF2NGD, and how this program
interacts with NGDBuild. This appendix contains the following sections:

• “EDIF2NGD”
• “NGDBuild”
• “Netlist Launcher (Netlister)”
• “NGDBuild File Names and Locations”

This program is compatible with the following families:
• Virtex™, Virtex™-E
• Virtex™-II
• Virtex™-II Pro, Virtex™-II Pro X
• Virtex™-4
• Virtex™-5
• Spartan™-II, Spartan™-IIE
• Spartan™-3, Spartan™-3A, Spartan™-3E
• CoolRunner™ XPLA3, CoolRunner™-II
• XC9500™, XC9500XL™, XC9500XV™

The EDIF2NGD program allows you to read an EDIF (Electronic Design Interchange
Format) 2 0 0 file into the Xilinx development system toolset. EDIF2NGD converts an
industry-standard EDIF netlist to an NGO file—a Xilinx-specific format. The EDIF file
includes the hierarchy of the input schematic. The output NGO file is a binary database
describing the design in terms of the components and hierarchy specified in the input
design file. After you convert the EDIF file to an NGO file, you run NGDBuild to create an
NGD file, which expands the design to include a description reduced to Xilinx primitives.

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The following figure shows the flow through EDIF2NGD.

Schematic Synthesis
Drawing Vendor Tools

EDIF 2 0 0
Writer

EDIF 2 0 0 Netlist

CAE VENDOR
TOOLS

XILINX
DEVELOPMENT
SYSTEM

NCF
Netlist Constraints File

EDIF2NGD

NGO

X6994

EDIF2NGD Design Flow

You can run EDIF2NGD in the following ways:

• Automatically from NGDBuild
• From the UNIX or DOS command line, as described in the following sections
Note: When creating net or symbol names, do not use reserved names. Reserved names are the
names of symbols for primitives and macros in the Libraries Guides and net names GSR, RESET,
GR, and PRELOAD. If you use these names, EDIF2NGD issues an error.

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EDIF2NGD Syntax

The following command reads your EDIF netlist and converts it to an NGO file:

edif2ngd [options] edif_file ngo_file

options can be any number of the EDIF2NGD options listed in “EDIF2NGD Options”. They
do not need to be listed in any particular order. Separate multiple options with spaces.

edif_file is the EDIF 2 0 0 input file to be converted. If you enter a file name with no
extension, EDIF2NGD looks for a file with the name you specified and an .edn extension.
If the file has an extension other than .edn, you must enter the extension as part of edif_file.

Note: For EDIF2NGD to read a Mentor Graphics EDIF file, you must have installed the Mentor
Graphics software component on your system. Similarly, to read a Cadence EDIF file, you must have
installed the Cadence software component.

ngo_file is the output file in NGO format. The output file name, its extension, and its
location are determined in the following ways:

• If you do not specify an output file name, the output file has the same name as the
input file, with an .ngo extension.

• If you specify an output file name with no extension, EDIF2NGD appends the .ngo
extension to the file name.

• If you specify a file name with an extension other than .ngo, you get an error message
and EDIF2NGD does not run.

• If you do not specify a full path name, the output file is placed in the directory from
which you ran EDIF2NGD.

If the output file exists, it is overwritten with the new file.

EDIF2NGD Input Files

EDIF2NGD uses the following files as input:

• EDIF file—This is an EDIF 2 0 0 netlist file. The file must be a Level 0 EDIF netlist, as
defined in the EDIF 2 0 0 specification. The Xilinx Development System toolset can
understand EDIF files developed using components from any of these libraries:
♦ Xilinx Unified Libraries (described in the Libraries Guides)
♦ XSI (Xilinx Synopsys Interface) Libraries
♦ Any Xilinx physical macros you create
Note: Xilinx tools do not recognize Xilinx Unified Libraries components defined as macros; they
only recognize the primitives from this library. The third-party EDIF writer must include definitions
for all macros.

• NCF file—This Netlist Constraints File is produced by a vendor toolset and contains
constraints specified within the toolset. EDIF2NGD reads the constraints in this file
and adds the constraints to the output NGO file.
EDIF2NGD reads the constraints in the NCF file if the NCF file has the same base name
as the input EDIF file and an .ncf extension. The name of the NCF file does not have to
be entered on the EDIF2NGD command line.

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EDIF2NGD Output Files

The output of EDIF2NGD is an NGO file—a binary file containing a logical description of
the design in terms of its original components and hierarchy.

EDIF2NGD Options

This section describes the EDIF2NGD command line options.

–a (Add PADs to Top-Level Port Signals)

The –a option adds PAD properties to all top-level port signals. This option is necessary if
the EDIF2NGD input is an EDIF file in which PAD symbols were translated into ports. If
you do not specify a –a option for one of these EDIF files, the absence of PAD instances in
the EDIF file causes EDIF2NGD to read the design incorrectly. Subsequently, MAP
interprets the logic as unused and removes it.

In all Mentor Graphics and Cadence EDIF files, PAD symbols are translated into ports. For
EDIF files from either of these vendors, the –a option is set automatically; you do not have
to enter the –a option on the EDIF2NGD command line.

–aul (Allow Unmatched LOCs)

By default (without the –aul option), EDIF2NGD generates an error if the constraints
specified for pin, net, or instance names in the NCF file cannot be found in the design. If
this error occurs, an NGO file is not written. If you enter the –aul option, EDIF2NGD
generates a warning instead of an error for LOC constraints and writes an NGO file.

You may want to run EDIF2NGD with the –aul option if your constraints file includes
location constraints for pin, net, or instance names that have not yet been defined in the
HDL or schematic. This allows you to maintain one version of your constraints files for
both partially complete and final designs.
Note: When using this option, make sure you do not have misspelled net or instance names in your
design. Misspelled names may cause inaccurate placing and routing.

–f (Execute Commands File)

–f command_file

The –f option executes the command line arguments in the specified command_file. For
more information on the –f option, see “–f (Execute Commands File)” in Chapter 1.

–intstyle (Integration Style)

–intstyle {ise | xflow | silent}

The –intstyle option reduces screen output based on the integration style you are running.
When using the –intstyle option, one of three modes must be specified: ise, xflow, or silent.
The mode sets the way information is displayed in the following ways:

–intstyle ise
This mode indicates the program is being run as part of an integrated design
environment.

–intstyle xflow
This mode indicates the program is being run as part of an integrated batch flow.

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–intstyle silent
This mode limits screen output to warning and error messages only.
Note: The -intstyle option is automatically invoked when running in an integrated environment, such
as Project Navigator or XFLOW.

–l (Libraries to Search)

–l libname
The –l option specifies a library to search when determining what library components
were used to build the design. This information is necessary for NGDBuild, which must
determine the source of the design’s components before it can resolve the components to
Xilinx primitives.

You may specify multiple –l options on the command line. Each must be preceded with –l;
you cannot combine multiple libname specifiers after one –l. For example, –l xilinxun
synopsys is not acceptable, while –l xilinxun –l synopsys is acceptable.

The allowable entries for libname are the following.
• xilinxun (For Xilinx Unified library)
• synopsys
Note: You do not have to enter xilinxun with a –l option. The Xilinx Development System tools
automatically access these libraries. You do not have to enter synopsys with a –l option if the EDIF
netlist contains an author construct with the string “Synopsys.” In this case, EDIF2NGD automatically
detects that the design is from Synopsys.

–p (Part Number)

–p part
The –p option specifies the part into which your design is implemented. The –p option can
specify an architecture only, a complete part specification (device, package, and speed), or
a partial specification (for example, device and package only).

The syntax for the –p option is described in “–p (Part Number)” in Chapter 1. Examples of
part entries are XCV50-TQ144 and XCV50-TQ144-5.

If you do not specify a part when you run EDIF2NGD, you must specify one when you run
NGDBuild.

You can also use the –p option to override a part name in the input EDIF netlist or a part
name in an NCF file.

–r (Ignore LOC Constraints)

The –r option filters out all location constraints (LOC=) from the design. If the output file
already exists, it is overwritten with the new file.

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NGDBuild

This program is compatible with the following families:

• Virtex™, Virtex™-E
• Virtex™-II
• Virtex™-II Pro, Virtex™-II Pro X
• Virtex™-4
• Virtex™-5
• Spartan™-II, Spartan™-IIE
• Spartan™-3, Spartan™-3A, Spartan™-3E
• CoolRunner™ XPLA3, CoolRunner™-II
• XC9500™, XC9500XL™, XC9500XV™

NGDBuild performs all the steps necessary to read a netlist file in EDIF format and create
an NGD file describing the logical design. The NGD file resulting from an NGDBuild run
contains both a logical description of the design reduced to NGD primitives and a
description in terms of the original hierarchy expressed in the input netlist. The output
NGD file can be mapped to the desired device family.

Converting a Netlist to an NGD File

The following figure shows the NGDBuild conversion process.

Netlist NGC Netlist PLD
(EDIF) (XST File) Netlist

Files NCF
Referenced in Netlist Netlist Constraints File

Netlist Reader
(EDIF2NGD)

NGO
Top-Level

NGO NMC NGC
For Files Physical Macros Core Modules
Referenced in Netlist Referenced in Netlist Referenced in Netlist

UCF URF
User Constraints File User Rules File

Netlister NGDBuild
Launcher

NGD BLD X10291
Generic Database Build Report

NGDBuild and the Netlist Readers

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NGDBuild performs the following steps to convert a netlist to an NGD file:

1. Reads the source netlist

To perform this step, NGDBuild invokes the Netlist Launcher (Netlister), a part of the
NGDBuild software which determines the type of the input netlist and starts the
appropriate netlist reader program. If the input netlist is in EDIF format, the Netlist
Launcher invokes EDIF2NGD. If the input netlist is in another format that the Netlist
Launcher recognizes, the Netlist Launcher invokes the program necessary to convert
the netlist to EDIF format, then invokes EDIF2NGD. The netlist reader produces an
NGO file for the top-level netlist file.

If any subfiles are referenced in the top-level netlist (for example, a PAL description
file, or another schematic file), the Netlist Launcher invokes the appropriate netlist
reader for each of these files to convert each referenced file to an NGO file.

The Netlist Launcher is described in “Netlist Launcher (Netlister)”. The netlist reader
programs are described in “EDIF2NGD”.

2. Reduces all components in the design to NGD primitives

To perform this step, NGDBuild merges components that reference other files by
finding the referenced NGO files. NGDBuild also finds the appropriate system library
components, physical macros (NMC files) and behavioral models.

3. Checks the design by running a Logical DRC (Design Rule Check) on the converted
design

The Logical DRC is a series of tests on the logical design. It is described in Chapter 5,
“Logical Design Rule Check.”

4. Writes an NGD file as output

When NGDBuild reads the source netlist, it detects any files or parts of the design that
have changed since the last run of NGDBuild. It updates files as follows:

• If you modified your input design, NGDBuild updates all of the files affected by the
change and uses the updated files to produce a new NGD file.

The Netlist Launcher checks timestamps (date and time information) for netlist files
and intermediate NGDBuild files (NGOs). If an NGO file has a timestamp earlier than
the netlist file that produced it, the NGO file is updated and a new NGD file is
produced.

• NGDBuild completes the NGD production if all or some of the intermediate files
already exist. These files may exist if you ran a netlist reader before you ran
NGDBuild. NGDBuild uses the existing files and creates the remaining files necessary
to produce the output NGD file.

Note: If the NGO for an netlist file is up to date, NGDBuild looks for an NCF file with the same base
name as the netlist in the netlist directory and compares the timestamp of the NCF file against that of
the NGO file. If the NCF file is newer, EDIF2NGD is run again. However, if an NCF file existed on a
previous run of NGDBuild and the NCF file was deleted, NGDBuild does not detect that EDIF2NGD
must be run again. In this case, you must use the –nt on option to force a rebuild. The –nt on
option must also be used to force a rebuild if you change any of the EDIF2NGD options.

Syntax, files, and options for NGDBuild are described in Chapter 6, “NGDBuild.”

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Bus Matching

When NGDBuild encounters an instance of one netlist within another netlist, it requires
that each pin specified on the upper-level instance match to a pin (or port) on the lower-
level netlist. Two pins must have exactly the same name in order to be matched. This
requirement applies to all FPGAs and CPLDs supported for NGDBuild.

If the interface between the two netlists uses bused pins, these pins are expanded into
scalar pins before any pin matching occurs. For example, the pin A[7:0] might be expanded
into 8 pins namedA[7] through A[0]. If both netlists use the same nomenclature (that is, the
same index delimiter characters) when expanding the bused pin, the scalar pin names will
match exactly. However, if the two netlists were created by different vendors and different
delimiters are used, the resulting scalar pin names do not match exactly.

In cases where the scalar pin names do not match exactly, NGDBuild analyzes the pin
names in both netlists and attempts to identify names that resulted from the expansion of
bused pins. When it identifies a bus-expanded pin name, it tries several other bus-naming
conventions to find a match in the other netlist so it can merge the two netlists. For
example, if it finds a pin named A(3) in one netlist, it looks for pins named A(3), A[3], A<3>
or A3 in the other netlist.

The following table lists the bus naming conventions understood by NGDBuild.

Bus Naming Conventions Example
Naming Convention DI(3)
busname(index) DI<3>
busname<index> DI[3]
busname[index] DI3
busnameindex

If your third-party netlist writer allows you to specify the bus-naming convention, use one
of the conventions shown in the preceding table to avoid “pin mismatch” errors during
NGDBuild. If your third-party EDIF writer preserves bus pins using the EDIF “array”
construct, the bus pins are expanded by EDIF2NGD using parentheses, which is one of the
supported naming conventions.

Note: NGDBuild support for bused pins is limited to this understanding of different naming
conventions. It is not able to merge together two netlists if a bused pin has different indices between
the two files. For example, it cannot match A[7:0] in one netlist to A[15:8] in another.

In the Xilinx UnifiedPro library for Virtex, some of the pins on the block RAM primitives
are bused. If your third-party netlist writer uses one of the bus naming conventions listed
in the preceding table or uses the EDIF array construct, these primitives are recognized
properly by NGDBuild. The use of any other naming convention may result in an
“unexpanded block” error during NGDBuild.

Netlist Launcher (Netlister)

The Netlist Launcher, which is part of NGDBuild, translates an EDIF netlist to an NGO file.
NGDBuild uses this NGO file to create an NGD file.

Note: The NGC netlist file does not require Netlist Launcher processing. It is equivalent to an NGO
file.

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When NGDBuild is invoked, the Netlist launcher goes through the following steps:

1. The Netlist Launcher initializes itself with a set of rules for determining what netlist
reader to use with each type of netlist, and the options with which each reader is
invoked.

The rules are contained in the system rules file (described in “System Rules File”) and
in the user rules file (described in “User Rules File”).

2. NGDBuild makes the directory of the top-level netlist the first entry in the Netlist
Launcher’s list of search paths.

3. For the top-level design and for each file referenced in the top-level design, NGDBuild
queries the Netlist Launcher for the presence of the corresponding NGO file.

4. For each NGO file requested, the Netlist Launcher performs the following actions:

♦ Determines what netlist is the source for the requested NGO file

The Netlist Launcher determines the source netlist by looking in its rules database
for the list of legal netlist extensions. Then, it looks in the search path (which
includes the current directory) for a netlist file possessing a legal extension and the
same name as the requested NGO file.

♦ Finds the requested NGO file

The Netlist Launcher looks first in the directory specified with the –dd option (or
current directory if a directory is not specified). If the NGO file is not found there
and the source netlist was not found in the search path, the Netlist Launcher looks
for the NGO file in the search path.

♦ Determines whether the NGO file must be created or updated

If neither the netlist source file nor the NGO file is found, NGDBuild exits with an
error.

If the netlist source file is found but the corresponding NGO file is not found, the
Netlist Launcher invokes the proper netlist reader to create the NGO file.

If the netlist source file is not found but the corresponding NGO file is found, the
Netlist Launcher indicates to NGDBuild that the file exists and NGDBuild uses
this NGO file.

If both the netlist source file and the corresponding NGO file are found, the netlist
file’s time stamp is checked against the NGO file’s timestamp. If the timestamp of
the NGO file is later than the source netlist, the Netlist Launcher returns a “found”
status to NGDBuild. If the timestamp of the NGO file is earlier than the netlist
source, or the NGO file is not present in the expected location, then the Launcher
creates the NGO file from the netlist source by invoking the netlist reader specified
by its rules.

Note: The timestamp check can be overridden by options on the NGDBuild command line. The
–nt on option updates all existing NGO files, regardless of their timestamps. The –nt off option
does not update any existing NGO files, regardless of their timestamps.

5. The Netlist launcher indicates to NGDBuild that the requested NGO files have been
found, and NGDBuild can process all of these NGO files.

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Netlist Launcher Rules Files

The behavior of the Netlist Launcher is determined by rules defined in the system rules file
and the user rule file. These rules determine the following:
• What netlist source files are acceptable
• Which netlist reader reads each of these netlist files
• What the default options are for each netlist reader
The system rules file contains the default rules supplied with the Xilinx Development
System software. The user rules file can add to or override the system rules.

User Rules File

The user rules file can add to or override the rules in the system rules file. You can specify
the location of the user rules file with the NGDBuild –ur option. The user rules file must
have a .urf extension. See “–ur (Read User Rules File)” in Chapter 6 for more information.

User Rules and System Rules

User rules are treated as follows:
• A user rule can override a system rule if it specifies the same source and target files as

the system rule.
• A user rule can supplement a system rule if its target file is identical to a system rule’s

source file, or if its source file is the same as a system rule’s target file.
• A user rule that has a source file identical to a system rule’s target file and a target file

that is identical to the same system rule’s source file is illegal, because it defines a
loop.

User Rules Format

Each rule in the user rules file has the following format:
RuleName = <rulename1>;

<key1> = <value1>;

<key2> = <value2>;

.

.

.

<keyn> = <valuen>;

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Following are the keys allowed and the values expected:

Note: The value types for the keys are described in “Value Types in Key Statements”.

• RuleName—This key identifies the beginning of a rule. It is also used in error
messages relating to the rule. It expects a RULENAME value. A value is required.

• NetlistFile—This key specifies a netlist or class of netlists that the netlist reader takes
as input. The extension of NetlistFile is used together with the TargetExtension to
identify the rule. It expects either a FILENAME or an EXTENSION value. If a file
name is specified, it should be just a file name (that is, no path). Any leading path is
ignored. A value is required.

• TargetExtension—This key specifies the class of files generated by the netlist reader. It
is used together with the extension from NetlistFile to identify the rule. It expects an
EXTENSION value. A value is required.

• Netlister—This key specifies the netlist reader to use when translating a specific
netlist or class of netlists to a target file. The specific netlist or class of netlists is
specified by NetlistFile, and the class of target files is specified by TargetExtension. It
expects an EXECUTABLE value. A value is required.

• NetlisterTopOptions—This key specifies options for the netlist reader when
compiling the top-level design. It expects an OPTIONS value or the keyword NONE.
Included in this string should be the keywords $INFILE and $OUTFILE, in which the
input and output files is substituted. In addition, the following keywords may appear.

♦ $PART—The part passed to NGDBuild by the –p option is substituted. It may
include architecture, device, package and speed information. The syntax for a
$PART specification is the same as described in “–p (Part Number)” in Chapter 1.

♦ $FAMILY—The family passed to NGDBuild by the –p option is substituted. A
value is optional.

♦ $DEVICE—The device passed to NGDBuild by the –p option is substituted. A
value is optional.

♦ $PKG—The package passed to NGDBuild by the –p option is substituted. A value
is optional.

♦ $SPEED—The speed passed to NGDBuild by the –p option is substituted. A value
is optional.

♦ $LIBRARIES—The libraries passed to NGDBuild. A value is optional.

♦ $IGNORE_LOCS—Substitute the –r option to EDIF2NGD if the NGDBuild
command line contained a –r option.

♦ $ADD_PADS—Substitute the –a option to EDIF2NGD if the NGDBuild command
line contained a –a option.

The options in the NetlisterTopOptions line must be enclosed in quotation marks.

• NetlisterOptions—This key specifies options for the netlist reader when compiling
sub-designs. It expects an OPTIONS value or the keyword NONE. Included in this
string should be the keywords $INFILE and $OUTFILE, in which the input and
output files is substituted. In addition, any of the keywords that may be entered for
the NetlisterTopOptions key may also be used for the NetlisterOptions key.

The options in the NetlisterOptions line must be enclosed in quotation marks.

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• NetlisterDirectory—This key specifies the directory in which to run the netlist reader.
The launcher changes to this directory before running the netlist reader. It expects a
DIR value or the keywords $SOURCE, $OUTPUT, or NONE, where the path to the
source netlist is substituted for $SOURCE, the directory specified with the -dd option
is substituted for $OUTPUT, and the current working directory is substituted for
NONE. A value is optional.

• NetlisterSuccessStatus—This key specifies the return code that the netlist reader
returns if it ran successfully. It expects a NUMBER value or the keyword NONE. The
number may be preceded with one of the following: =, <, >, or !. A value is optional.

Value Types in Key Statements

The value types used in the preceding key statements are the following:

• RULENAME—Any series of characters except for a semicolon “;” and white space
(for example, space, tab, newline).

• EXTENSION—A “.” followed by an extension that conforms to the requirements of
the platform.

• FILENAME—A file name that conforms to the requirements of the platform.
• EXECUTABLE—An executable name that conforms to the requirements of the

platform. It may be a full path to an executable or just an executable name. If it is just
a name, then the $PATH environment variable is used to locate the executable.
• DIR—A directory name that conforms to the requirements of the platform.
• OPTIONS—Any valid string of options for the executable.
• NUMBER—Any series of digits.
• STRING—Any series of characters in double quotes.

System Rules File

The system rules are shown following. The system rules file is not an ASCII file, but for the
purpose of describing the rules, the rules are described using the same syntax as in the user
rules file. This syntax is described in “User Rules File”.

Note: If a rule attribute is not specified, it is assumed to have the value NONE.

#####################################################
# edif2ngd rules
#####################################################

RuleName = EDN_RULE;
NetlistFile = .edn;
TargetExtension = .ngo;
Netlister = edif2ngd;
NetlisterTopOptions = "[$IGNORE_LOCS] [$ADD_PADS] [$QUIET] [$AUL] {-l
$LIBRARIES} $INFILE $OUTFILE";
NetlisterOptions = "-noa [$IGNORE_LOCS] {-l $LIBRARIES} $INFILE
$OUTFILE";
NetlisterDirectory = NONE;
NetlisterSuccessStatus = 0;

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RuleName = EDF_RULE;
NetlistFile = .edf;
TargetExtension = .ngo;
Netlister = edif2ngd;
NetlisterTopOptions = "[$IGNORE_LOCS] [$ADD_PADS] [$QUIET] [$AUL] {-l
$LIBRARIES} $INFILE $OUTFILE";
NetlisterOptions = "-noa [$IGNORE_LOCS] {-l $LIBRARIES} $INFILE
$OUTFILE";
NetlisterDirectory = NONE;
NetlisterSuccessStatus = 0;

RuleName = EDIF_RULE;
NetlistFile = .edif;
TargetExtension = .ngo;
Netlister = edif2ngd;
NetlisterTopOptions = "[$IGNORE_LOCS] [$ADD_PADS] [$QUIET] [$AUL] {-l
$LIBRARIES} $INFILE $OUTFILE";
NetlisterOptions = "-noa [$IGNORE_LOCS] {-l $LIBRARIES} $INFILE
$OUTFILE";
NetlisterDirectory = NONE;
NetlisterSuccessStatus = 0;

RuleName = SYN_EDIF_RULE;
NetlistFile = .sedif;
TargetExtension = .ngo;
Netlister = edif2ngd;
NetlisterTopOptions = NONE;
NetlisterOptions = "-l synopsys [$IGNORE_LOCS] {-l $LIBRARIES} $INFILE
$OUTFILE";
NetlisterDirectory = NONE;
NetlisterSuccessStatus = 0;

Rules File Examples

The following sections provide examples of system and user rules. The first example is the
basis for understanding the ensuing user rules examples.

Example 1: EDF_RULE System Rule

As shown in the “System Rules File”, the EDF_RULE system rule is defined as follows.

RuleName = EDF_RULE;
NetlistFile = .edf;
TargetExtension = .ngo;
Netlister = edif2ngd;
NetlisterTopOptions = "[$IGNORE_LOCS] [$ADD_PADS] [$QUIET] [$AUL] {-l
$LIBRARIES} $INFILE $OUTFILE";
NetlisterOptions = "-noa [$IGNORE_LOCS] {-l $LIBRARIES} $INFILE
$OUTFILE";
NetlisterDirectory = NONE;
NetlisterSuccessStatus = 0;

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The EDF_RULE instructs the Netlist Launcher to use EDIF2NGD to translate an EDIF file
to an NGO file. If the top-level netlist is being translated, the options defined in
NetlisterTopOptions are used; if a lower-level netlist is being processed, the options
defined by NetlisterOptions are used. Because NetlisterDirectory is NONE, the Netlist
Launcher runs EDIF2NGD in the current working directory (the one from which
NGDBuild was launched). The launcher expects EDIF2NGD to issue a return code of 0 if it
was successful; any other value is interpreted as failure.

Example 2: User Rule

Following is a another example of a User Rule:

// URF Example 2
RuleName = OTHER_RULE; // end-of-line comments are also allowed
NetlistFile = .oth;
TargetExtension = .edf;
Netlister = other2edf;
NetlisterOptions = "$INFILE $OUTFILE";
NetlisterSuccessStatus = 1;

The user rule OTHER_RULE defines a completely new translation, from a hypothetical
OTH file to an EDIF file. To do this translation, the other2edf program is used. The options
defined by NetlisterOptions are used for translating all OTH files, regardless of whether
they are top-level or lower-level netlists (because no explicit NetlisterTopOptions is given).
The launcher expects other2edf to issue a return code of 1 if it was successful; any other
value be interpreted as failure.

After the Netlist Launcher uses OTHER_RULE to run other2edf and create an EDIF file, it
uses the EDF_RULE system rule (shown in the preceding section) to translate the EDIF file
to an NGO file.

Example 3: User Rule

Following is a another example of a User Rule:

// URF Example 3
RuleName = EDF_LIB_RULE;
NetlistFile = .edf;
TargetExtension = .ngo;
NetlisterOptions = "-l xilinxun $INFILE $OUTFILE";

Because both the NetlistFile and TargetExtension of this user rule match those of the
system rule EDF_RULE (shown in “Example 1: EDF_RULE System Rule”), the
EDF_LIB_RULE overrides the EDF_RULE system rule. Any settings that are not defined
by the EDF_LIB_RULE are inherited from EDF_RULE. So EDF_LIB_RULE uses the same
netlister (EDIF2NGD), the same top-level options, the same directory, and expects the
same success status as EDF_RULE. However, when translating lower-level netlists, the
options used are only “–l xilinxun $INFILE $OUTFILE.” (There is no reason to use “–l
xilinxun” on EDIF2NGD; this is for illustrative purposes only.)

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Example 4: User Rule

Following is a another example of a User Rule:

// URF Example 4
RuleName = STATE_EDF_RULE;
NetlistFile = state.edf;
TargetExtension = .ngo;
Netlister = state2ngd;

Although the NetlistFile is a complete file name, this user rule also matches the system rule
EDF_RULE (shown in “Example 1: EDF_RULE System Rule”), because the extensions of
NetlistFile and TargetExtension match. When the Netlist Launcher tries to make a file
called state.ngo, it uses this rule instead of the system rule EDF_RULE (assuming that
state.edf exists). As with the previous example, the unspecified settings are inherited from
the matching system rule. The only change is that the fictitious program state2ngd is used
in place of EDIF2NGD.

Note that if EDF_LIB_RULE (from the example in “Example 3: User Rule”) and this rule
were both in the user rules file, STATE_EDF_RULE includes the modifications made by
EDF_LIB_RULE. So a lower-level state.edf is translated by running state2ngd with the “-l
xilinxun” option.

NGDBuild File Names and Locations

Following are some notes about file names in NGDBuild:

• An intermediate file has the same root name as the design that produced it. An
intermediate file is generated when more than one netlist reader is needed to translate
a netlist to a NGO file.

• Netlist root file names in the search path must be unique. For example, if you have the
design state.edn, you cannot have another design named state in any of the directories
specified in the search path.

• NGDBuild and the Netlist Launcher support quoted file names. Quoted file names
may have special characters (for example, a space) that are not normally allowed.

• If the output directory specified in the call to NGDBuild is not writable, an error is
displayed and NGDBuild fails.

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Glossary

Click on a letter, or scroll down to view the entire glossary.
ABCDEFGHIJLMNOPRSTUVW

A

ABEL

Advanced Boolean Expression Lanaguage (ABEL) is a high-level
language (HDL) and compilation system produced by Data I/O
Corporation.

adder

An adder is a combinatorial circuit that computes the sum of two or
more numbers.

address

An address is the identification of a storage location, such as a register
or a memory cell.

checked for syntax errors.

architecture

Architecture is the common logic structure of a family of
programmable integrated circuits. The same architecture can be
realized in different manufacturing processes. Examples of Xilinx
architectures are the XC9500 devices.

anno

Anno is used to refer to the general back-annotation process.

area constraints

Area constraints are created by the user or a process such as synthesis
to direct the optimization process that takes place during design
implementation.

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ASIC Application-specific integrated circuit (ASIC), is a full-custom circuit.
attributes In which every mask is defined by the customer or a semi-custom
circuit (gate array) where only a few masks are defined.

Attributes are instructions placed on symbols or nets in an FPGA or
CPLD schematic to indicate their placement, implementation,
naming, directionality, or other properties.I

B

back-annotation

Back-annotation is the translation of a routed or fitted design to a
timing simulation netlist.

behavioral design

Behavioral design is a technology-independent, text-based design that
incorporates high-level functionality and high-level information flow.

behavioral design method

A behavioral design method defines a circuit in terms of a textual
language rather than a schematic of interconnected symbols.

behavioral simulation

Also known as functional simulation. Behavioral simulation is usually
performed on designs that are entered using a hardware definition
language (HDL).

This type of simulation takes place during the pre-synthesis stage of
HDL design. Functional simulation checks that the HDL code
describes the desired design behavior.

Behavioral simulation is a simulation process that is performed by
interpreting the equations that define the design. The equations do not
need to be converted to the logic that represents them.

binary

Binary is a numbering system based on base 2 with only two digits, 0
and 1.

Unsigned binary refers to non-negative binary representation.

bit

A bit is a a binary digit representing 0 or 1.

BIT file

A BIT file is the same as a bitstream file. See bitstream.

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BitGen

Is a program that produces a bitstream for Xilinx device configuration.
BitGen takes a fully routed NCD (Circuit Description) file as its input
and produces a configuration bitstream, a binary file with a.bit
extension.

bitstream

A bitstream is a stream of data that contains location information for
logic on a device, that is, the placement of Configurable Logic Blocks
(CLBs), Input/Output Blocks (IOBs), (TBUFs), pins, and routing
elements. The bitstream also includes empty placeholders that are
filled with the logical states sent by the device during a readback. Only
the memory elements, such as flip-flops, RAMs, and CLB outputs, are
mapped to these placeholders, because their contents are likely to
change from one state to another. When downloaded to a device, a
bitstream configures the logic of a device and programs the device so
that the states of that device can be read back.

A bitstream file has a .bit extension.

block

A block is a group of one or more logic functions.
A block is a schematic or symbol sheet. There are four types of blocks.
-- A Composite block indicates that the design is hierarchical.
-- A Module block is a symbol with no underlying schematic.
-- A Pin block represents a schematic pin.
-- An Annotate block is a symbol without electrical connectivity that is

used only for documentation and graphics.

bonded

Bonded means connected by a wire.

boundary scan

Boundary scan is the method used for board-level testing of electronic
assemblies. The primary objectives are the testing of chip
I/O signals and the interconnections between ICs.

It is the method for observing and controlling all new chip I/O signals
through a standard interface called a Test Access Port (TAP). The
boundary scan architecture includes four dedicated I/O pins for
control and is described in IEEE spec 1149.1.

BSDLAnno

A program that automatically modifies a BSDL file for post-
configuration interconnect testing.

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buffer A buffer is an element used to increase the current or drive of a weak
signal and, consequently, increase the fanout of the signal. A storage
BUFT element.
bus
byte A BUFT is a 3-state buffer.

A group of two or more signals that carry closely-associated signals in
an electronic design.

A binary word consisting of eight bits. When used to store a number
value, a byte can represent a number from 0 to 255.

C

CAE

Computer Aided Engineering. The original term for electronic design
automation (EDA). Now, often refers to the sofware tools used to
develop the manufacturing tooling for the production of electronic
system such as for the panelization of circuit boards.

CAE tool

A Computer-Aided Engineering tool (CAE). Usually refers to
programs such as Innoveda, Cadence, or Mentor Graphics that are
used to perform design entry and design verification.

capacitance

Capacitance is the property that measures the storage of electrically
separated charges.

It is also the load on a net.

carry path

The carry path is the computation of the carries in addition or
subtraction from one CLB to another.

cell

A cell is a hierarchical description of an FPGA device.

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checksum

A checksum is a summation of bits or digits generated according to an
arbitrary formula used for checking data integrity. To verify that the
data represented by a checksum number has been entered correctly,
verify that the checksum number generated after processing is the
same as the initial number.

CLB

The Configurable Logic Block (CLB). Constitutes the basic FPGA cell.
It includes two 16-bit function generators (F or G), one 8-bit function
generator (H), two registers (flip-flops or latches), and
reprogrammable routing controls (multiplexers).

CLBs are used to implement macros and other designed functions.
They provide the physical support for an implemented and
downloaded design. CLBs have inputs on each side, and this
versatility makes them flexible for the mapping and partitioning of
logic.

CCLK pin

The CCLK pin is the XChecker pin that provides the configuration
clock for the device or devices during a download.

clock

A clock is a signal that represents the time that a wave stays at a High
or Low state. The rising and falling edges of a clock square wave
trigger the activity of the circuits.

clock buffer

A clock buffer is an element used to increase the current or drive of a
weak clock signal and consequently increase its fanout.

clock enable

A clock enable is a binary signal that allows or disallows synchronous
logic to change with a clock signal. When enabled, this control signal
permits a device to be clocked and to become active. There are four
different states. The two active High states are CE 0 disabled and CE
1 enabled. The two active Low states are CE 0 enabled and CE 1
disabled.

clock skew

Clock skew is the time differential between 2 or more destination pins
in a path.

CMOS

Complementary Metal Oxide Semiconductor (CMOS). Is an advanced
IC manufacturing process technology characterized by high
integration, low cost, low power, and high performance.

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combinatorial logic

Combinatorial logic refers to any primitives with the exception of
storage elements such as flip-flops.

compiler

A compiler is a language interpreter. The Synopsys compiler
interprets HDL and makes concurrent process implementations for
target architectures.

component

A component is an instantiation or symbol reference from a library of
logic elements that can be placed on a schematic.

COMPXLIB

A tool for compiling the Xilinx simulation libraries with the tools
provided by simulator vendors.

configuration

Configuration is the process of loading design-specific bitstreams into
one or more FPGA devices to define the functional operation of the
logical blocks, their interconnections, and the chip I/O.

This concept also refers to the configuration of a design directory for a
particular design library.

constraints

Constraints are specifications for the implementation process. There
are several categories of constraints: routing, timing, area, mapping,
and placement constraints.

Using attributes, you can force the placement of logic (macros) in
CLBs, the location of CLBs on the chip, and the maximum delay
between flip-flops. PAR does not attempt to change the location of
constrained logic.

constraints file

A constraints file specifies constraints (location and path delay)
information in a textual form. An alternate method is to place
constraints on a schematic.

contention

Contention is the state in which multiple conflicting outputs drive the
same net.

counter

A counter is a circuit, composed of registers, that counts pulses, often
reacting or causing a reaction to a predetermined pulse or series of
pulses. Also called a divider, sometimes accumulator.

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CPLDfit programmable logic device that can be programmed with a schematic
D or a behavioral design. CPLDs constitute a type of complex PLD based
on EPROM or EEPROM technology. They are characterized by an
architecture offering high speed, predictable timing, and simple
software.

The basic CPLD cell is called a macrocell, which is the CPLD
implementation of a CLB. It is composed of AND gate arrays and is
surrounded by the interconnect area.

CPLDs consume more power than FPGA devices, are based on a
different architecture, and are primarily used to support behavioral
designs and to implement complex counters, complex state machines,
arithmetic operations, wide inputs, and PAL crunchers.

A program that reads in an NGD file and fits the design into the
selected CPLD architecture.

daisy chain

A daisy chain is a series of bitstream files concatenated in one file. It
can be used to program several FPGAs connected in a daisy chain
board configuration.

dangling bus

A dangling bus connects to a component pin or net at one end and
unconnects at the other. A small filled box at the end of the bus
indicates a dangling bus.

dangling net

A dangling net connects to a component pin or net at one end and
unconnects at the other. A small filled box at the end of the net
indicates a dangling net.

Data2MEM

A program that transforms CPU execution code, or pure data, into
Block RAM initialization records.

debugging

Debugging is the process of reading back or probing the states of a
configured device to ensure that the device is behaving as expected
while in circuit.

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decimal

Decimal refers to a numbering system with a base of 10 digits starting
with zero.

decoder

A decoder is a symbol that translates n input lines of binary
information into 2n output lines. It is the opposite of an encoder.

Delay Locked Loop (DLL)

A digital circuit used to perform clock management functions on and
off-chip.

density

Density is the number of gates on a device.

design implementation

Design implementation is a design implementation specification as
opposed to the functional specification of the design. The
implementation specification refers to the actual implementation of
the design from low-level components expressed in bits. The
functional specification refers to the definition of the design or circuit
function.

device

A device is an integrated circuit or other solid-state circuit formed in
semiconducting materials during manufacturing.

digital

Digital refers to the representation of information by code of discrete
elements, as opposed to the continuous scale of analog representation.

DONE pin

The DONE pin is a dual-function pin. As an input, it can be configured
to delay the global logic initialization or the enabling of outputs. As an
output, it indicates the completion of the configuration process.

downloading

Downloading is the process of configuring or programming a device
by sending bitstream data to the device.

DRC

The Design Rule Checker (DRC). A program that checks the (NCD)
file for design implementations for errors.

DSP

Digital Signal Processing (DSP). A powerful and flexible technique of
processing analog (linear) signals in digital form used in CoreGen.

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E

EDA

Electronic Design Automation (EDA). A generic name for all methods
of entering and processing digital and analog designs for further
processing, simulation, and implementation.

edge decoder

An edge decoder is a decoder whose placement is constrained to
precise positions within a side of the FPGA device.

EDIF

EDIF is the Electronic Data Interchange Format, an industry standard
file format for specifying a design netlist. It is generated by a third-
party design-entry tool. In the Xilinx M1 flow, EDIF is the standard
input format.

effort level

Effort level refers to how hard the Xilinx Design System (XDS) tries to
place a design. The effort level settings are.

High, which provides the highest quality placement but requires the
longest execution time. Use high effort on designs that do not route or
do not meet your performance requirements.

Medium, which is the default effort level. It provides the best trade-off
between execution time and high quality placement for most designs.

Low, which provides the fastest execution time and adequate
placement results for prototyping of simple, easy-to-route designs.
Low effort is useful if you are exploring a large design space and only
need estimates of final performance.

ENRead

Mentor Graphics EDIF netlist reader. Translates an EDIF netlist into an
EDDM single object.

entity

An entity is a set of interconnected components.

EPROM

An EPROM is an erasable PROM, which can be reprogrammed many
times. Previous programs are simply erased by exposing the chip to
ultra-violet light.

An EEPROM, or electrically erasable PROM, is another variety of
EPROM that can be erased electrically.

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F

FD

FD is a D flip-flop used in CLBs. Contrast with IFD.

FDSD

FDSD is a D flip-flop with Set Direct.

FIFO

A FIFO is a serial-in/serial-out shift register.

fitting

Fitting is the process of putting logic from your design into physical
macrocell locations in the CPLD. Routing is performed automatically,
and because of the UIM architecture, all designs are routable.

fitter

The fitter is the software that maps a PLD logic description into the
target CPLD.

flat design

A flat design is a design composed of multiple sheets at the top-level
schematic.

flattening

Flattening is the process of resolving all of the hierarchy references in
a design. If a design contains several instantiations of a logic module,
the flattened version of that design will duplicate the logic for each
instantiation. A flattened design still contains hierarchical names for
instances and nets.

flip-flop

A flip-flop is a simple two-state logic buffer activated by a clock and
fed by a single input working in combination with the clock. The states
are High and Low. When the clock goes High, the flip-flop works as a
buffer as it outputs the value of the D input at the time the clock rises.

The value is kept until the next clock cycle (rising clock edge). The
output is not affected when the clock goes Low (falling clock edge).

floorplanning

Floorplanning is the process of choosing the best grouping and
connectivity of logic in a design.

It is also the process of manually placing blocks of logic in an FPGA
where the goal is to increase density, routability, or performance.

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G The flow is an ordered sequence of processes that are executed to
produce an implementation of a design.

FMAP

An FMAP is a symbol that defines mapping into a 4-input function
generator (F or G).

FPGA

Field Programmable Gate Array (FPGA), is a class of integrated
circuits pioneered by Xilinx in which the logic function is defined by
the customer using Xilinx development system software after the IC
has been manufactured and delivered to the end user. Gate arrays are
another type of IC whose logic is defined during the manufacturing
process. Xilinx supplies RAM-based FPGA devices.

FPGA applications include fast counters, fast pipelined designs,
register intensive designs, and battery powered multi-level logic.

function generator

A function generator is a look-up table or black box with three or four
inputs implementing any combinational functions of (22)4 or 256
functions or (22)2 or 65556 functions. The output is any value resulting
from the logical functions executed within the box. The function
generator implements a complete truth table, allowing speedy
prediction of the output.

functional simulation

Functional simulation is the process of identifying logic errors in your
design before it is implemented in a Xilinx device. Because timing
information for the design is not available, the simulator tests the logic
in the design using unit delays. Functional simulation is usually
performed at the early stages of the design process.

gate A gate is an integrated circuit composed of several transistors and
gate array capable of representing any primitive logic state, such as AND, OR,
XOR, or NOT inversion conditions. Gates are also called digital,
switching, or logic circuits.

A gate array is part of the ASIC chip. A gate array represents a certain
type of gate repeated all over a VLSI-type chip. This type of logic
requires the use of masks to program the connections between the
blocks of gates.

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global buffers

Global buffers are low-skew, high-speed buffers that connect to long
lines. They do not map logic.

There is one BUFGP and one BUFGS in each corner of the chip.
Primary buffers must be driven by an IOB. Secondary buffers can be
driven by internal logic or IOBs.

global Set/Reset net

A global Set/Reset net is a high-speed, no-skew dedicated net, which
reduces delays and routing congestion. This net accesses all flip-flops
on the chip and can reinitialize all CLBs and IOBs.

global 3-state net

A global 3-state net is a net that forces all device outputs to high-
impedance state unless boundary scan is enabled and executes an
EXTEST instruction.

GND pin

The GND pin is Ground (0 volts).

group

A group is a collection of common signals to form a bus. In the case of
a counter, for example, the different signals that produce the actual
counter values can be combined to form an alias, or group.

guide file

A guide file is a previously placed and routed NCP file that can be
used in a subsequent place and route operation.

guided design

Guided design is the use of a previously implemented version of a file
for design mapping, placement, and routing. Guided design allows
logic to be modified or added to a design while preserving the layout
and performance that have been previously achieved.

H

HDL

Hardware Description Language. A language that describes circuits in
textual code. The two most widely accepted HDLs are VHDL and
Verilog.

An HDL, or hardware description language, describes designs in a
technology-independent manner using a high level of abstraction. The
most common HDLs in use today are Verilog and VHDL.

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R hexadecimal

I Hexadecimal is a numbering system with a base of 16 digits (0, 1, 2, 3,
4, 5, 6, 7, 8, 9, A, B, C, D, E, F)

hierarchical annotation

Hierarchical annotation is an advance method of running logical
annotation that requires three things: 1) .ncd file, 2) .ngm file, and 3)
KEEP_HIERARCHY constraint placed on explicit hierarchy blocks
prior to mapping. When this is done, the back-annotation guarantees
to preserve the user’s hierarchy.

hierarchical design

A hierarchical design is a design composed of multiple sheets at
different levels of your schematic.

hold time

Hold time is the time following a clock event during which the data
input to a latch or flip-flop must remain stable in order to guarantee
that the latched data is correct.

Hprep6

A program that takes an implemented CPLD design (VM6) file from
CPLDfit and generates a JEDEC (JED) programming file.

IBUF An IBUF acts as a protection for the chip, shielding it from eventual
IC current overflows.

IEEE Integrated Circuit (IC) is a single piece of silicon on which thousands
IFD or millions of transistors are combined. ICs are the major building
impedance blocks of modern electronic systems.

Institute of Electrical and Electronics Engineers.Pronounced I triple E.

IFD is an IOB flip-flop.

Impedance is the sum of all resistance and reactance of a circuit to the
flow of alternating current.

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implementation

Implementation is the mapping, placement and routing of a design. A
phase in the design process during which the design is placed and
routed.

incremental design

Incremental design refers to the implementation and verification of a
small design change using a guide file.

indexes

Indexes are the left-most and right-most bits of a bus defining the bus
range and precision.

inertial delay

If the pulse width of a signal is smaller than the path delay (from an
input port to an output port) then an inertial delay does not propogate
the pulse event through to the output port. This is known as pulse
swallowing.

input

An input is the symbol port through which data is sourced.

input pad registers and latches

Input pad registers and latches are D-type registers located in the I/O
pad sections of the device. Input pad registers can be used instead of
macrocell resources.

instance

An instance is one specific gate or hierarchical element in a design or
netlist. The term "symbol" often describes instances in a schematic
drawing. Instances are interconnected by pins and nets. Pins are ports
through which connections are made from an instance to a net. A
design that is flattened to its lowest level constituents is described
with primitive instances.

instantiation

Instantiation is the act of placing a symbol that represents a primitive
or a macro in a design or netlist.

Integrated Synthesis Environment (ISE)

ISE is an integrated tool suite that enables you to produce, test, and
implement designs for Xilinx FPGAs or CPLDs.

interconnect

Interconnect is the metal in a device that is used to implement the nets
of the design.

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R interconnect line

J An interconnect line is any portion of a net.
L
IOB (input/output block)

An IOB is a collection or grouping of basic elements that implement
the input and output functions of an FPGA device.

I/O pads

I/O pads are the input/output pads that interface the design logic
with the pins of the device.

JEDEC

JEDEC is a CPLD file format used for downloading device bitmap
information to a device programmer.

latch

A latch is a two-state buffer fed by two inputs, D and L. When the L
input is Low, it acts as a transparent input; in this case, the latch acts
as a buffer and outputs the value input by D. When the L input is
High, it ignores the D input value.

library

A library is a set of macros, such as adders, buffers, and flip-flops that
is part of the Xilinx interface. A library is used to create schematic
designs.

load

A load is an input port.

logic

Logic is one of the three major classes of ICs in most digital electronic
systems: microprocessors, memory, and logic. Logic is used for data
manipulation and control functions that require higher speed than a
microprocessor can provide.

logical annotation

The method of back-annotation that uses the old .ngm and .ncd to
attempt to back-annotate the physical information (physical delays)
back into the logical (.ngd) file.

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logic allocation file

A logic allocation file, design.ll file, designates a file used for probing.
The file provides bit locations of the values of RAM, I/O, latches, and
flip-flops.

logic optimization

Logic optimization is the process that decreases the area or increases
the speed of a design.

longline

A longline connects to a primary global net or to any secondary global
net. Each CLB has four dedicated vertical longlines. These lines are
very fast.

look-up table (LUT)

A Look-Up Table (LUT), implements Boolean functions.
See function generator.

low

Low is a logical state for which no output is generated.

LSB

An LSB, or least significant bit, is the left-most bit of the bus bounds or
indexes. In one-hot and twos-complement encoding, the LSB is the
right-most bit.

M

macro A macro is a component made of nets and primitives, flip-flops, or
macrocell latches that implements high-level functions, such as adders,
mapping subtracters, and dividers. Soft macros and Relationally Placed Macros
(RPMs) are types of macros.

A macrocell is the CPLD logic cell, which is made of gates only. A
macrocell can implement both combinational and registered
equations. High-density function block macrocells also contain an
arithmetic logic unit (ALU) for implementing arithmetic functions.

Mapping is the process of assigning a design’s logic elements to the
specific physical elements that actually implement logic functions in a
device.

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R MCS-86 (Intel)

N MCS-86 (Intel) is a PROM format supported by the Xilinx tools. Its
maximum address is 1 048 576. This format supports PROM files of up
to (8 x 1 048 576) = 8 388 608 bits.

microprocessor

A silicon chip that contains a CPU. Microprocessors control the logic
of almost all digital devices, e.g. PCs, workstations, clock radios, and
fuel-injection systems for automobiles.

modular design

Modular design refers to the parallel development of pieces, or
“modules,” of a design being independently worked on and then later
merged into one FPGA design.

MSB

The Most Significant Bit (MSB) is the right-most bit of the bus bounds
or indexes. In one-hot binary and twos-complement encoding, the
MSB is the left-most bit.

MultiLINX

A cable designed to function as a download, read back, verification
and logic probing tool for the larger Xilinx devices. MultiLINX
functions as a USB device to send and receive data from host.

multiplexer

A multiplexer is a reprogrammable routing control. This component
selects one input wire as output from a selection of wires.

NCD A Native Circuit Description (NCD). The physical database format for
net Xilinx implementation software tools.

A logical connection between two or more symbol instance pins. After
routing, the abstract concept of a net is transformed to a physical
connection called a wire.
An electrical connection between components or nets. It can also be a
connection from a single component. It is the same as a wire or a
signal.

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netlist A netlist is a text description of the circuit connectivity. It is basically a
list of connectors, a list of instances, and, for each instance, a list of the
network signals connected to the instance terminals. In addition, the netlist
NetGen contains attribute information.

NGDBuild A network is a collection of logic elements and the wires (nets or
NGM connections) that define how they interconnect.

A program that reads in applicable Xilinx implementation files,
extracts design data, and generates netlists that are used with
supported third-party simulation, equivalence checking, and static
timing analysis tools.

A program that converts all input design netlists and then writes the
results into a single merged file.

A design file produced by MAP that contains information about the
logical design and information about how the logical design
corresponds to the physical design.

O

optimization

Optimization is the process that decreases the area or increases the
speed of a design.

oscillator

An oscillator is a bi-stable circuit that can be used as a clock. The stable
states are 0 and 1.

P

package A package is the physical packaging of a chip, for example, PG84,
pad VQ100, and PC48.

A pad is the physical bonding pad on an integrated circuit. All signals
on a chip must enter and leave by way of a pad. Pads are connected to
package pins in order for signals to enter or leave an integrated circuit
package.

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PAL

A PAL is a programmable logic device that consists of a
programmable AND matrix whose outputs drive fixed OR gates. This
was one of the earliest forms of programmable logic. PALs can
typically implement small functions easily (up to a hundred gates)
and run very fast, but they are inefficient for large functions.

Parallel Cable III

Parallel Cable III is a cable assembly which contains a buffer to protect
your PCs parallel port and a set of headers to connect to your target
system.

partial reconfiguration

Partial Reconfiguration refers to a portion of an FPGA design being
reconfigured while the remainder of the design is still operational.

Partition

A Partition is design unit placed on an instance in a design to enable
design preservation.

path

A path is a connected series of nets and logic elements. A path has a
start point and an end point that are different depending on the type
of path. The time taken for a signal to propagate through a path is
referred to as the path delay.

path delay

Path delay is the time it takes for a signal to propagate through a path.

period

The period is the number of steps in a clock pattern multiplied by the
step size.

physical annotation

Physical annotation uses just the .ncd file. In this mode, a timing
simulation model is generated from the physical device components.

PIM

Physically Implemented Module

pin

A pin can be a symbol pin or a package pin. A package pin is a
physical connector on an integrated circuit package that carries
signals into and out of an integrated circuit. A symbol pin, also
referred to as an instance pin, is the connection point of an instance to
a net.

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PIP (programmable interconnect points)

Programmable interconnect points, or PIP, provide the routing paths
used to connect the inputs and outputs of IOBs and CLBs into logic
networks.

A PIP is made of a CMOS transistor, which you can turn on and off to
activate the PIP.

placing

Placing is the process of assigning physical device cell locations to the
logic in a design.

PLD

A Programmable Logic Device (PLD), is composed of two types of
gate arrays: the AND array and the OR array, thus providing for sum
of products algorithmic representations. PLDs include three distinct
types of chips: PROMs, PALs, and PLAs. The most flexible device is
the PLA (programmable logic array) in which both the AND and OR
gate arrays are programmable. In the PROM device, only the OR gate
array is programmable. In the PAL device, only the AND gate array is
programmable. PLDs are programmed by blowing the fuses along the
paths that must be disconnected.

FPGAs and CPLDs are classes of PLDs.

post-synthesis simulation

This type of simulation is usually done after the HDL code has been
expanded into gates. Post-synthesis simulation is similar to behavioral
simualtion since design behavior is being checked. The difference is
that in post-synthesis simulation the synthesis tool’s results are being
checked. If post-synthesis and behavioral simulation match, then the
HDL synthesis tool has interpreted the HDL code correctly.

primitive

A basic logic element, such as a gate (AND, OR, XOR, NAND, or
NOR), inverter, flip-flop, or latch.

A logic element that directly corresponds, or maps, to one of these
basic elements.

programming

Programming is the process of configuring the programmable
interconnect in the FPGA.

PROM

A PROM is a programmable read-only memory.

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R PROM file

R A PROM file consists of one or more BIT files (bitstreams) formed into
one or more datastreams. The file is formatted in one of three
industry-standard formats: Intel MCS86 HEX, Tektronics TEKHEX, or
Motorola EXORmacs. The PROM file includes headers that specify the
length of the bitstreams as well as all the framing and control
information necessary to configure the FPGAs. It can be used to
program one or more devices.

propagation

Propagation is the repetition of the bus attributes along a data path so
that they only need to be defined on one bus in a data path.

pull-down resistor

A pull-down resistor is a device or circuit used to reduce the output
impedance of a device, often a resistor network that holds a device or
circuit output at or less than the zero input level of a subsequent
digital device in a system.

pull-up resistor

A pull-up resistor is a device or method used to keep the output
voltage of a device at a high level, often a resistor network connected
to a positive supply voltage.

RAM Random Access Memory (RAM) is a read/write memory that has an
readback access time independent of the physical location of the data.
register RAM can be used to change the address values (161) of the function
generator it is a part of.

Readback is the process of reading the logic downloaded to an FPGA
device back to the source. There are two types of readback.
A readback of logic usually accompanied by a comparison check to
verify that the design was downloaded in its entirety.
A readback of the states stored in the device memory elements to
ensure that the device is behaving as expected.

A register is a set of flip-flops used to store data. It is an accumulator
used for all arithmetic operations.

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resistance The property — based on material, dimensions, and temperature of
conductors — that determines the amount of current produced at a
resistor given difference in potential. A material’s current impedance that
ROM dissipates power in the form of heat.
routing The drive of the output pins on a network.
RPM
RTL A resistor is a device that provides resistance.

Read Only Memory (ROM) is a static memory structure that retains a
state indefinitely, even when the power is turned off. It can be part of
a function generator.

Routing is the process of assigning logical nets to physical wire
segments in the FPGA that interconnect logic cells.

A Relationally Placed Macro (RPM) defines the spatial relationship of
the primitives that constitute its logic. An indivisible block of logic
elements that are placed as a unit into a design.

Register Transfer Level

S

schematic

A schematic is a hierarchical drawing representing a design in terms
of user and library components.

script

A script is a series of commands that automatically execute a complex
operation such as the steps in a design flow.

SDF (standard delay format)

Standard Delay Format (SDF) is an industry-standard file format for
specifying timing information. It is usually used for simulation.

seed

A seed is a random number that determines the order of the cells in the
design to be placed.

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set/reset

This operation is made possible by the asynchronous set/reset
property. This function is also implemented by the Global Reset
STARTUP primitive.

shift register

A shift register is a register in which data is loaded in parallel and
shifted out of the register again. It refers to a chain of flip-flops
connected in cascade.

signal

A signal is a wire or a net. See “net.”

simulation

Simulation is the process of verifying the logic and timing of a design.

skew

Skew is clock delay. See clock skew.

slew rate

The slew rate is the speed with which the output voltage level
transitions from +5 V to 0 V or vice-versa. The slew rate determines
how fast the transistors on the outputs change states.

slice

Two slices form a CLB within Virtex and Spartan-II families.

SmartGuide

Instructs MAP and PAR to use results from a previous implementation
to guide the current implementation.

speed

Speed is a function of net types, CLB density, switching matrices, and
architecture.

STARTUP symbol

The STARTUP symbol is a symbol used to set/reset all CLB and IOB
flip-flops.

state

A state is the set of values stored in the memory elements of a device
(flip-flops, RAMs, CLB outputs, and IOBs) that represent the state of
that device at a particular point of the readback cycle. To each state
there corresponds a specific set of logical values.

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state machine

A state machine is a set of combinatorial and sequential logic elements
arranged to operate in a predefined sequence in response to specified
inputs. The hardware implementation of a state machine design is a
set of storage registers (flip-flops) and combinatorial logic, or gates.
The storage registers store the current state, and the logic network
performs the operations to determine the next state.

static timing analysis

A static timing analysis is a point-to-point delay analysis of a design
network.

T

TAEngine

A program that performs static timing analysis on a successfully
implemented Xilinx CPLD design (VM6).

Tcl

Tool Command Language (Tcl) is an easy to use scripting language
and an industry standard popular in the electronic design automation
(EDA) industry.

TEKHEX (Tektronix)

TEKHEX (Tektronix) is a PROM format supported by Xilinx. Its
maximum address is 65 536. This format supports PROM files of up to
(8 x 65 536) = 524 288 bits.

testbench

An HDL netlist containing test vectors to drive a simulation.

threshold

The threshold is the crossover point when something occurs or is
observed or indicated. The CMOS threshold and TTL threshold are
examples.

timing

Timing is the process that calculates the delays associated with each of
the routed nets in the design.

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timing simulation

This type of simulation takes place after the HDL design has been
synthesized and placed and routed. The purpose of this simulation is
to check the dynamic timing behavior of the HDL design in the target
technology.

Use the block and routing delay information from the routed design to
assess the circuit behavior under worst-case conditions.

timing specifications

Timing specifications define the maximum allowable delay on any
given set of paths in a design. Timing specifications are entered on the
schematic.

TRACE

Provides static timing analysis of a design based on input timing
constraints.

trace information

Trace information is a list of nodes and vectors to be simulated in
functional and timing simulation. This information is defined at the
schematic level.

transistor

A transistor is a three-terminal semiconductor device that switches or
amplifies electrical current. It acts like a switch: On is equal to 1, and
Off is equal to 0.

trimming

Trimming is the process of removing unconnected or unused logic.

tristate (3-state)

A 3-state, or 3-state buffer, is a buffer that places an output signal in a
high-impedance state to prevent it from contending with another
output signal.

tristate (3-state) condition

A 3-state condition is a high-impedance state. A 3-state can act also as
a normal output; i.e. it can be on, off, or not connected.

truth table

A truth table defines the behavior for a block of digital logic. Each line
of a truth table lists the input signal values and the resulting output
value.

TSIM

A program that formats implemented CPLD design (VM6) files into a
format usable by the NetGen timing simulation flow.

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TTL

TTL, or transistor-transistor logic, is a technology with specific
interchange (communication of digital signals) voltages and currents.
Other technologies include ECL, MOS, and CMOS. These types of
logic are used as criteria to classify digital integrated circuits.

U

unbonded

Unbonded describes an IOB used for internal logic only. This element
does not have an external package pin.

Unified Libraries

A set of logic macros and functions that are used to define the logic of
a design. The elements are compatible across families and schematic
and HDL editors.

V

VCC pin

The VCC pin is Power (5 volts). It is the supply voltage.

verification

Verification is the process of reading back the configuration data of a
device and comparing it to the original design to ensure that all of the
design was correctly received by the device.

Verilog

Verilog is a commonly used Hardware Description Language (HDL)
that can be used to model a digital system at many levels of
abstraction ranging from the algorithmic level to the gate level. It is
IEEE standard 1364-1995. Verilog was originally developed by
Cadence Design Systems and is now maintained by OVI.

A Verilog file has a .v extension.

VHDL

VHDL is an acronym for VHSIC Hardware Description Language
(VHSIC an acronym for Very High-Speed Integrated Circuits). It can
be used to describe the concurrent and sequential behavior of a digital
system at many levels of abstraction ranging from the algorithmic
level to the gate level. VHDL is IEEE standard 1076-1993.

A VHDL file has a .vhd or .vhdl extension.

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R VITAL

W VITAL is an acronym for VHDL Intitiative Toward ASIC Libraries. It
X is a VHDL-library standard (IEEE 1076.4) that defines standard
constructs for simulation modeling, accelerating, and improving the
performance of VHDL simulators.

wire

A wire is a net or a signal. See net.

xtclsh

Xilinx Tcl Shell (xtclsh), which presents the xtclsh prompt used for
running scripts and using the Xilinx Tcl commands.

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