Modern Computer Architecture and Organisation (2020)

528 Index

memory management unit (MMU) Moore's law
about 186 about 12-15, 370, 371
functions 188, 189 developing techniques 371, 372

memory-mapped I/O 83 mouse 113, 114
memory pools Moving Picture Experts Group

about 185 (MPEG) 159
non-paged pool 185 mov instruction 254
paged pool 185 MPX instructions 261
memory protection extensions (MPX) 261 MS-DOS 249
memory protection unit (MPU) 243 multi-booting
memory subsystem 90
message queue 148 versus boot priority order 130
metal-oxide-semiconductor multi-core processors 141
multilevel feedback queue 138
field-effect transistor (MOSFET) multilevel processor caches 196, 197
about 91 multipath 112
digital switching circuits 91-93 multiple-input-multiple-
used, for constructing
output (MIMO) 112
DRAM circuits 94 multiple instruction, multiple
metal-oxide-semiconductor (MOS) 89
micro-operations 215 data (MIMD) 141, 218
miscellaneous instructions 261 multiply-accumulate (MAC) 152, 311
Mistral 344 multiprocessing computer 141
modern computer system multiprogramming 177
multitasking 146
specifications 115, 117 mutual exclusion 146
modern processors virtualization
N
about 332
ARM processor virtualization 334 nanometers (nm) 14
RISC-V processor nanoseconds (ns) 45
natural boundary 250
virtualization 334, 335 natural language processing (NLP) 361
x86 hardware virtualization 333, 334 near-field communication (NFC) 166
x86 processor virtualization 332, 333 Negative sign flag 21
Mod field 263 nested interrupt 79
modified Harvard architecture nested virtualization 322
network interface
153, 175, 176
ModR/M byte 262 about 111
monitor 81 Ethernet 111
Monsoon 344

Index 529

Wi-Fi 112, 113 operating system virtualization 321, 322
network virtualization 323 out-of-order instruction
neural network architecture 361
neural network processor for execution (OOO) 214
output layer 163
inference (NNP-I) 364 overclocking 115
neural network processor for Overflow flag 21
oversubscribed 357
training (NNP-T) 361
neuron 162 P
N extension 307
nibble 281 page 178
NMI (Non-Maskable Interrupt) 75 Page Directory Base Register (PDBR) 181
NNP-I, form factors paged pool 185
paged virtual memory 180-182
M.2 card 364 page fault 182
PCIe card 364 page frame
NNP T-1000 processor configurations
features 364 about 180
non-maskable interrupt 79, 80 states 186
non-paged pool 185 page frame number (PFN) 186
non-preemptive scheduling 136 page status bits 184, 185
non-real-time operating systems page swapping 178
versus real-time operating systems 133 page table 180
nonvolatile memory (NVM) 127 page table directory 180
NOP instruction 78 parallel data buses 101-103
null pointer exception 189 parallel port 121-123
Nvidia GeForce RTX 2080 paravirtualization 328
PCIe device drivers 123, 124
Ti GPU 349, 350 PCI Express (PCIe) 104, 105, 123, 160
perceptron 349
O Peripheral Component Interconnect

object-oriented programming (OOP) 312 (PCI) 104, 121
offset 276 personal computer architecture
Olimex ARM-TINY-USB-H debugger
about 348
reference link 312 Alienware Aurora Ryzen Edition
opcode 22, 57
Open Compute Project (OCP) 361 gaming desktop 348, 349
operands 60 Alienware Aurora Ryzen
operating system 132
operating system kernel 133 Edition subsystems 352

530 Index prefetching 100, 101
Nvidia GeForce RTX 2080 priority inheritance 147
Ti GPU 349, 350 privileged processor modes
Ryzen 9 3950X branch prediction 349
about 224
petabytes (PB) 162 hardware exceptions, handling 225-227
P extension 307 hardware interrupts, handling 225-227
PHA instruction 22 protection rings 228-231
Phase-locked loop (PLL) 47 supervisor mode 231
physical memory 176, 177 system calls 232
pipeline bubble 213 user mode 231
pipeline hazards 213, 214 process
pipelining about 134
states 135
about 208-211 process control block (PCB) 135
conditional branches 216, 217 process identifier (PID) 135
decode 208 processor cache write policies
execute 209 about 205, 206
fetch 208 write-back policy 205
micro-operations 214 write-through policy 205
register renaming 215 processor context 136
superpipelining 212 processor flag instructions 77
writeback 209 processor instruction and data caches 195
PLA instruction 22 processor technology
pointer 189 capabilities 370
polyvinyl chloride (PVC) 30 processor virtualization, categories
Portable Operating System about 324
binary translation 328
Interface (POSIX) 322 hardware emulation 329
port-mapped I/O 83 paravirtualization 328
port map sections 52 trap-and-emulate virtualization 325-327
port numbers 83 process priority 139, 140
positive edge-triggered D flip-flop 40 Program Counter (PC) 57
post-quantum cryptography 378 programmed I/O 84
power management programming language exceptions 228
propagation delay 44, 46
about 239 protected mode instructions 261
dynamic voltage frequency pseudo-instructions 299, 301

scaling (DVFS) 240
Power-On Self-Test (POST) 126
predication 281
preemptive scheduling 136

Q Index 531
versus non-real-time operating
QEMU
about 338 systems 133
URL 329 recurrent network 163
reduced instruction set computer
Q extension 306
Qisket (RISC) 66, 252
register 21, 42, 43, 65-67, 276
about 380 register renaming 215
reference link 380 register set 56
quantum 374 register-to-register data transfer
quantum behavior
reference link 386 instructions 74
quantum bit (qubit) 15, 376 register-transfer level (RTL) 313
quantum computing 376-380 reg/opcode field 263
quantum cryptography 377 relative addressing mode 77
quantum decoherence 380 ring counter 41
quantum entanglement 377 ripple carry adder 44
quantum-error correction 380 RISC-V
Quantum mechanics 373
Quantum physics 374 about 291
quantum superposition 376 features 292-295
quantum supremacy 379 implementing, in FPGA 310-315
queue 148 RISC-V 32-bit integer instruction

R set (RV32I) 303
RISC-V A extension 304
R-2R ladder 150 RISC-V architecture
rack-based servers 356-358
Random Access Memory about 292-295
privilege levels 302, 303
(RAM) 20, 143, 310 RISC-V assembly language
rate-monotonic scheduling (RMS) 138 examples 309, 310
Read inputs 145 RISC-V base instruction set
Read-Only Memory (ROM) 21, 126, 311 about 296
real mode 249 computational instructions 296
real-time computing 144, 145 control flow instructions 297
real-time operating system (RTOS) memory access instructions 297, 298
pseudo-instructions 299, 301
about 132, 145, 146 system instructions 298, 299
RISC-V C extension
implementing 305

532 Index

RISC-V extensions S
about 303
additional extensions 306, 307 safer mode extensions (SMX) 261
A extension 304 sample-and-hold circuit 150
C extension 305 sandbox 320
M extension 304 SBC command 23
RISC-V F and D extensions 306 SBC instruction

RISC-V F and D extensions 306 about 23, 75
RISC-V M extension 304 versus CMP instruction 75
RISC-V processor virtualization 334, 335 scaled register 276
R/M field 263 scheduler 135
ROL instruction 76 scheduling
ROR instruction 76 algorithms 137, 138
round-robin scheduling 137 SEC instruction 77
RTI instruction 79 sector 106
RTOS, features Secure Boot 129
security technologies, examples
critical section 148 device memory protection 243
deadlock 147 internal encryption engine
mutex 146
priority inversion 147 with key storage 243
queue 148 password-protected hardware
semaphore 148
thread preemption 146 debugger interface 243
RTS instruction 77, 79 SED instruction 77
RTX 2080 Ti, features SEI instruction 77
6 graphics-processing clusters 351 sequential logic 47
11 GB of GDDR6 memory 351 Serial AT Attachment (SATA) 105
36 texture-processing clusters 351 serial data buses 101-103
72 streaming multiprocessors 351 set
DisplayPort 1.4a video outputs 351
HDMI 2.0b port 351 versus clear 18
Nvidia Scalable Link Interface (SLI) 351 set associative cache 203, 204
PCIe 3.0 x16 interface 351 Set-Reset (SR latch) 37
VirtualLink USB C port 351 sextillion 92
RV32E architecture 306 shadow page tables 331
Ryzen 9 3950X branch prediction 349 shift register 41
Shors algorithm 378
signal-to-noise ratio (SNR) 154

SIMD instructions 261 Index 533
SIMD processing 218, 219
simultaneous multithreading 217 power analysis 244
single data rate (SDR) 98 power disruption 244
single instruction, multiple data timing analysis 244
static RAM (SRAM) 197, 198
(SIMD) 12, 141, 218, 307 std_logic 50
small outline DIMM (SODIMM) 97 stopband suppression 156
smartphone architecture 343 storage virtualization 323
SMX instructions 261 store architecture 273
snooping 206 Streaming SIMD Extensions (SSE) 219
soft fault 183 string manipulation instructions 260
soft real-time system 144 subroutine call and return instructions 77
solid-state drive (SSD) 106, 345 successive approximation 151
spatial locality 195 superpipelining 212
specialized architectures Supervisor call (svc) 280
supervisor mode 231
examples 164, 166 swap file 178
specialized architectures, configurations switch 112
symmetric multiprocessing 141
business desktop computer 165 synapses 162
cloud compute server 164 synchronous circuit 41
high--end smartphone 166 synchronous DRAM (SDRAM) 98
high-performance gaming synchronous logic 47
system instructions 298, 299
computer 165 system-on-chip (SoC) 272, 345, 372
specialized processing technologies 372 system security management
spectrum analyzers 158 about 241-244
spintronics 374, 376 business information 242
spin valve 375 government information 242
split cache 199 personal information 242
square wave 46
stack instructions 75 T
stack manipulation instructions 257
stack pointer 22 task 146
standard digitized analog data formats TechCrunch

example 152 URL 383
standard RISC-V temporal locality 195
tensor 363
configurations 308, 309 TensorFlow 350
standard security techniques

emission analysis 244
physical alteration 244

534 Index

tensor processor clusters (TPCs) 363 U
terabytes (TB) 128, 162, 267, 302
teraflops 161 UEFI
terminate and stay resident (TSR) 177 about 128
test-and-set instruction 147 supported features 128, 129
T extension 307
thread 134, 146 UEFI applications 128
thread control block (TCB) 136 UEFI boot 130, 131
Thumb (T32) 272 unipolar transistor 91
Thunderbolt 107 Universal Serial Bus (USB) 106, 312
tile-based deferred rendering (TBDR) 344 University of California Berkeley
time-slicing 134
TNW (UC Berkeley) 292
user mode 231
URL 384 U.S. News & World Report
Tom's Hardware
reference link 385
URL 383
training set 362 V
transactional synchronization
V bit 335
extensions (TSX) 262 vector 152
transistor 31, 33 Very High Speed Integrated
Transistor-Transistor Logic (TTL) 121
transition band 156 Circuits (VHSIC) 311
translation lookaside buffer V extension 307
VHSIC Hardware Description
(TLB) 187, 194
operation 188 Language (VHDL) 49-53, 311
trap-and-emulate virtualization 325-327 Video Graphics Array (VGA) 109
truth table 33 Virtual Address Extension (VAX) 179
TSX instructions 262 Virtual Box 336
twisted pairs 102 virtualization
two's complement 19
two's complement arithmetic 19 about 320, 338
TXA instruction in cloud-computing 339
executing 60 virtualization, challenges
TXS instruction 74 about 330
type 1 hypervisor 321 security 331
type 2 hypervisor 321 shadow page tables 331
unsafe instructions 330

Index 535

virtualization tools WSC hardware 354, 355
about 335 WSC, multilevel information cache 360
kernel-based virtual machine water hammer arrestors function 94
(KVM) 337 web browser caches 195
QEMU 338 web crawler 358
Virtual Box 336 weighting factor (w1-w3) 163
VMware ESXi 337 wide area network (WAN) 111
VMware Workstation 336 Wi-Fi 112, 113
Xen 337 Wi-Fi Protected Access 2 (WPA2) 113
Windows Boot Manager 131
virtualization, types Wine
about 321 URL 322
application virtualization 322, 323 Wired
network virtualization 323 URL 383
operating system virtualization 321, 322 word length 20
storage virtualization 323, 324 workloads 337
Write outputs 145
virtual local area networks (VLANs) 323 WSC hardware
virtual machine extensions (VMX) 262 about 354, 355
virtual machine monitor 321 approaches 354
virtual memory 178, 179 attributes 354
Virtual Memory System (VMS) 179
virtual supervisor (VS) mode 335 X
virtual user (VU) mode 335
VMware ESXi 337 x64 266
VMware Workstation 336 x64 architecture
VMX instructions 262
von Neumann architecture 172 about 266, 267
von Neumann bottleneck 153, 173 features 267
x64 assembly language 269-272
W x64 instruction categories 269
x64 instruction formats 269
warehouse-scale computer (WSC) x64 instruction set 266, 267
about 353 x64 register set 268
multilevel information cache 360 x86 248
x86-64 266
warehouse-scale computing architecture x86 addressing modes
about 353 about 254
electrical power consumption 359 based indexed addressing 255
hardware fault management 359
rack-based servers 356-358

536 Index flag manipulation instructions 260
based indexed addressing, input/output instructions 260
with scaling 256 miscellaneous instructions 261
direct memory addressing 255 protected mode instructions 261
immediate addressing 254 string manipulation instructions 260
implied addressing 254 x86 instruction formats
indexed addressing 255 about 262, 263
register addressing 254 address displacement bytes 263
register indirect addressing 255 immediate value bytes 263
ModR/M byte 263
x86 architecture opcode bytes 262
about 248-250 prefix bytes 262
data types 250 x86 instruction patterns 262
x86 instruction set 248-250
x86 assembly language 263-266 x86 processor virtualization 332, 333
x86 flags register x86 register set 250-252
Xen 337
functions 252
x86 general-purpose registers Z

arithmetic and logic Zero flag 22
instructions 258, 259 zero-page addressing mode 73
Zicsr extension 307
stack manipulation instructions 257 Zifencei extension 307
x86 hardware virtualization 333, 334
x86 instruction categories

about 256-261
control flow instructions 259, 260
conversion instructions 259
data movement instructions 257