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CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 939 Fig. 1. Polycrystalline silicon panel used in this paper.

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938 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND ...

CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 939 Fig. 1. Polycrystalline silicon panel used in this paper.

938 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015

Modeling, Fabrication, and Reliability of Through
Vias in Polycrystalline Silicon Panels

Qiao Chen, Hao Lu, Venky Sundaram, and Rao R. Tummala, Fellow, IEEE

Abstract— Silicon interposers with through-silicon vias (TSVs) simulations of the stress distribution in TSVs. These models
have been developed in single-crystalline silicon wafer to address showed that the stresses at the Cu/SiO2 interface and in the
the high I/O density requirements between high performance SiO2 layer lead to potential failure mechanisms in TSVs,
logic, memory, graphic, and other devices. However, single- such as liner delamination and cracking, both of which are
crystalline silicon interposers suffer from many shortcomings confirmed by the characterization of fabricated TSVs after
such as high cost, low electrical performance, and reliability. thermal cycling. Cassidy et al. [10] reported similar results
To overcome these shortcomings of traditional silicon interposers, by identifying the localized stresses around the TSV sidewalls.
an entirely different approach using polycrystalline silicon panels It was also pointed out that the thin oxide liner was susceptible
with polymer liners and through-package-vias (TPVs) is proposed to problems such as leakage and dielectric breakdown.
by Georgia Tech Packaging Research Center. This paper, for
the first time, focuses on the reliability of TPVs in polycrys- Georgia Tech Packaging Research Center proposed an
talline silicon interposers fabricated from panels. Mechanical alternative to silicon interposer with through-package
simulations were carried out that show lower stresses in TPVs in vias (TPVs) to interconnect logic memory for high bandwidth
polycrystalline silicon lined with thick polymer liners, compared in the short term and entire systems in the long run with the
with TSVs in traditional single-crystalline silicon with thin system-on-package concept technology [11]. This interposer
SiO2 layers. TPVs were fabricated for thermal cycling tests, technology is a panel-based polycrystalline silicon with TPVs
resistance monitoring, and scanning electron microscope imaging. lined with thick polymers, aimed at lowering the total cost
The reliability characterization results showed good mechanical of fabricating the interposer with high performance and high
reliability of TPVs in polycrystalline silicon panels. reliability [12]–[14].

Index Terms— Fracture strength, polycrystalline silicon panel, Due to its lower purity level, polycrystalline silicon material
reliability characterization, silicon interposer. presents a much lower resistivity (∼0.5 · cm) than the
traditional wafer. Hence, addressing this higher loss and yet
I. INTRODUCTION achieve higher performance is one of the major challenges.
This issue can be addressed with the introduction of low loss
T HE rapid development of microelectronic systems, such and thick polymer liners for insulating the lossy silicon. The
as smartphones and tablets, has fueled a growing interest electrical simulation results in [14] confirmed that TPVs with
in advancing packaging technologies to smaller pitch and polymer liners present superior electrical performance, such
lower cost [1]. One of these advanced packaging technologies as lower insertion loss, than the TSVs with thin SiO2 layers.
is the development of interposers for interconnecting
3-D IC stacks with through-silicon vias (TSVs) [2]. Traditional This paper focuses on the reliability of these TPVs.
silicon interposers, based on TSV techniques, however, suffer To address the reliability challenges due to the coefficient of
from high production cost because of expensive CMOS tools thermal expansion (CTE) mismatch between Cu and silicon,
and processes and small wafer sizes. They also suffer from thick, and low cost polymer liners with low modulus are
high electrical loss in spite of thin SiO2 layers [3], [4]. proposed to act as stress buffer, replacing SiO2 and barrier
In addition, the thin SiO2 layers can also lead to reliability layer in TSVs. This paper starts with the introduction of
problems. Liu et al. [5], [7]–[9] and Chen et al. [6] have polycrystalline silicon panels followed by a study of handling
extensively reported the finite-element modeling (FEM) and such thin panels during processing (Section II). Following
Section II, Section III presents the mechanical modeling
Manuscript received March 26, 2015; revised June 15, 2015; results, showing the stress comparisons between TPVs in
accepted June 15, 2015. Date of current version July 15, 2015. polycrystalline silicon interposers and TSVs in traditional
This work was supported by the Silicon and Glass Interposer silicon interposers. Parametric studies were also performed
through the Consortium of Georgia Tech Packaging Research Center. with in-via liner thicknesses. Section IV summaries the
Recommended for publication by Associate Editor A. Chandra upon fabrication of TPVs. Reliability characterization of TPVs is
evaluation of reviewers’ comments. presented in Section V with thermal cycling tests, resistance
monitoring, and scanning electron microscope (SEM) imaging.
Q. Chen, H. Lu, and V. Sundaram are with the School of Electrical
and Computer Engineering, Georgia Institute of Technology, Atlanta, II. POLYCRYSTALLINE SILICON PANELS
GA 30332 USA (e-mail: [email protected]; [email protected];
[email protected]). The top view of the 200-μm thick polycrystalline
silicon panel used in this paper is shown in Fig. 1.
R. R. Tummala is with the School of Electrical and Computer Engineering,
School of Materials Science and Engineering, Georgia Institute of Technology,
Atlanta, GA 30332 USA (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCPMT.2015.2446435

2156-3950 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information

CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 939

Fig. 1. Polycrystalline silicon panel used in this paper. Fig. 2. Four-point bend test to evaluate fracture strength.

Polycrystalline silicon panels have been widely used in Fig. 3. Schematic of fixture setup for four-point bending test.
photovoltaic industry as the substrate material for solar-cell
applications [15]–[18], but not as substrates for interposer using the following [19]:
demonstrations. Polycrystalline silicon panel is cheaper to
fabricate than the single-crystalline wafer, and can be scaled to σ = 3P(L − Li) (1)
large sizes. More importantly, the larger size substrates yield 2bd 2
more numbers of interposers, thus promising to lower the cost
of single-unit interposers. where σ is the stress due to applied load, P is the applied load,

However, polycrystalline silicon is a brittle material, and L outer span, Li is the inner span, b is the sample width, and
therefore, one of the fundamental challenges is the high d is the sample thickness.
fracture rate caused by handling during the TPV liner
formation and metallization process steps. These challenges Consistent with the hypothesis about the randomness of the
get exacerbated when moving to thinner and larger panel
sizes. To overcome these panel breakage challenges, surface defects, strength data were generated with a large amount of
polymer liners on both sides of the panel were introduced. The
surface liner not only minimizes the damage, improves the scatter, due to many variables such as defect locations, grain
strength, and enables handling of the thin silicon panels, but
also functions as an electrical insulator to isolate signals from sizes, and orientations. Therefore, statistical treatment of the
leaking into the lossy silicon. The surface liner was deposited
by vacuum lamination of thin dry film polymer dielectrics strength data was necessary with Weibull plots. Weibull theory
during TPV liner fabrication process [14].
of brittle fracture is based on the fact that failure of the whole
The fracture strength of any brittle material, such as
polysilicon, is controlled by the existence of critical body depends on a combination of survival probabilities of
defects, which act as the origins of the final failure. Unlike
single-crystalline silicon, defects are distributed randomly the individual volume elements. For a given test, the Weibull
in the polycrystalline silicon panels, due to different crystal
orientations and grain boundaries. Different grain orientations equation can be written as [20]
can be clearly observed in the top view detail of the as-cut
polycrystalline silicon panel made by directional solidification, σ m
shown in Fig. 1. Therefore, it is inaccurate to evaluate the σθ
fracture strength of the sample by carrying out the experiment P f = 1 − exp − (2)
on an entire large panel. Hence, to quantify the fracture
strength of the stack consisting of the silicon panel with where P f is the probability of failure due to applied stress
polymer liners, three types of samples were prepared, σ , σθ is the characteristic strength when 62.5% of the sample
including raw silicon panels, silicon panels laminated fails, and m is the Weibull modulus.
with 22.5-μm thick polymer liners on both sides, and silicon
panels laminated with 40-μm thick polymer liners on both In general, the Weibull plots can be obtained by assigning
sides. Each test sample was diced into 24 rectangular pieces, P f to each strength point. The two important factors σθ
each having a length of 37.5 mm and a width of 25 mm, and (usually used as a reference for the fracture strength of the
mechanically tested by four-point bending tests (Fig. 2).
The schematic of testing fixture, with the sample sample) and m (Weibull modulus describing the variation of
mounted, is shown in Fig. 3. The stress was calculated the data) are achieved by plotting ln(1/ln(1 − P f )) versus
ln(σ ) followed by a linear regression analysis.

940 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015

Fig. 5. Schematic cross-sectional drawing of TPV for mechanical modeling.

Fig. 4. Weibull plots of fracture strength for silicon panels with and without
polymer liners.

TABLE I
PARAMETER VALUES FOR FRACTURE STRENGTH

AFTER LINEAR REGRESSION

The Weibull plots for three types of test samples are Fig. 6. Schematic cross-sectional drawings and meshed models for
compared in Fig. 4 with critical factors obtained from (a) TPV and (b) TSV.
linear regression summarized in Table I. It can be concluded
from Fig. 4 and Table I that surface polymer liners significantly TABLE II
improve the fracture strength and thus the handling of the thin MATERIAL PROPERTIES USED IN MECHANICAL MODELING
polycrystalline panels. The thicker polymer led to even higher
fracture strength. The comparison between Weibull modulus
from different sets of data suggests that the variations were
small enough and were similar in each data set, confirming
the validity of the tests. These results proved the hypothesis
that surface liners on both sides of the panel help improve the
handling of the substrate and thus mitigate the panel breakage
problem.

III. MECHANICAL MODELING OF TPVs bottom surfaces and 3-μm-thick via sidewall liner, compared
with 1-μm-thick SiO2 liner on the top and bottom surfaces
In this section, FEM was performed using Ansoft Ansys of silicon and 1-μm-thick via sidewall liner for TSVs. The
to simulate the proposed TPV structure with polymer liners, effect of the very thin diffusion barrier was neglected in
in comparison with TSVs with thin SiO2 liners. A 2-D TSV modeling.
axisymmetric model was built to generate and analyze both
the interfacial shear and first principal stresses due to thermal The material properties used in the simulations are given
loading. Parametric studies were also performed with sidewall in Table II. The polymer presents moderate CTE and
liner thickness. The schematic cross section (one-fourth via) much lower modulus than SiO2. The nonlinear model of
is presented in Fig. 5 with geometry values. The Cu via size
was 30 μm with a height of 200 μm. The diameter of the pad
was 50 μm and the thickness was 10 μm.

Fig. 6 compares the schematic cross section and meshed
models for TPVs and TSVs. In this paper, TPVs were
simulated with 3-μm-thick polymer liner on the top and

CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 941

TABLE IV
STRESS COMPARISONS FOR TPV WITH DIFFERENT

SIDEWALL LINER THICKNESSES

Fig. 7. Thermal loading curve for mechanical modeling.

Fig. 8. Contour plots for the (a) first principal stress in Si and (b) shear stress localizations in TSV structures can be attributed to the
stress. higher CTE mismatch of SiO2 with Cu vias. This makes
it more susceptible to delamination failures compared with
TABLE III TPV structures.
STRESS COMPARISONS IN TSV WITH SiO2 LINER
Based on the above discussions, thick polymer liners in
AND TPV WITH POLYMER LINER TPVs act as buffer layers, absorbing stresses, and can reduce
the risk of failures in both substrate cracking and interface
Cu was used based on [5]. A standard thermal load cycle delamination. On the other hand, TSVs show higher stress
of −55 °C–125 °C (Fig. 7) was used in the analysis with a in spite of the thinner layer of SiO2. Furthermore, due to
dwelling time of 15 min at both extreme temperatures. higher stiffness of SiO2, the TSV structures are more prone
to cohesive cracks in liners compared with TPV structures.
The contour plots of the first principal stress in Si and It is also expected that TSV structures would experience
shear stress are shown in Fig. 8. Stress localizations occur additional stresses during the backgrinding processes required
at the interfaces of different materials due to CTE mismatch. for fabricating these structures.
Table III summaries the maximum first principal stress in
Si substrate and the maximum shear stress for TPVs and Parametric studies are also performed with varying sidewall
TSVs at 125 °C. It can be observed that the maximum first liner thickness, since this analysis can provide important
principal stress in silicon is significantly reduced in TPV guidelines for the reliability of TPVs. Three different cases,
(164 MPa) compared with TSV (259 MPa). This is due to 5-, 10-, and 15-μm in-via liners, were studied and compared.
the low modulus and cushion effect [22] of the polymer The substrate thickness in each case was 200 μm and the
material. The much smaller stress in TPV can mitigate the diameter of the via (Cu filled) was 30 μm. The surface
possibility of silicon crack and thus result in better reliability. liner was 15-μm-thick. As presented in Table IV, when the
Similarly, TSV shows larger (137 MPa) maximum shear stress in-via liner becomes thicker (5, 10, and 15 μm), the maximum
than the TPV (85 MPa). The relatively higher interfacial shear first principal stress at 125 °C gradually decreases
(111, 52, and 21 MPa). Hence, at elevated temperature,
larger polymer liner thicknesses absorb the stresses more
effectively and lead to less first principal stresses in silicon
and thus less risk of cohesive cracking in the substrate. It can
also be summarized from Table IV that the maximum shear
stresses for TPVs are 82, 80, and 79 MPa for TPVs with
5-, 10-, and 15-μm liners, respectively. As expected, the
shear stresses localize at material interfaces and larger liner
thicknesses also help to reduce the shear stresses, thus leading
to a smaller possibility of delamination failures.

IV. FABRICATION OF TPVs

Following the simulation results from Section III, this
section discusses the fabrication of test vehicles to evaluate
the thermomechanical reliability of TPVs in polycrystalline
silicon panels. These test vehicles consisted of two metal
wiring layers and TPV transitions with daisy chain structures.

942 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015

Fig. 10. Top view of the fabricated test structures.

Fig. 9. Fabrication process flow for test vehicle with TPVs and two metal and void-free filling process for the TPVs. In addition, such
layers. a double-side process can help to mitigate any potential
warpage of the thin silicon panel generated by the heating
In addition, four-point probe pads (kelvin structures) were and cooling cycles in the lamination process. A short hot
included in the design, which are able to exclude any errors press cycle was performed at 120 °C with 1-ton force for
from probe contact resistances and wire resistances. better planarity by eliminating any dimples resulting from the
filling process, followed by a thermal curing to complete the
The fabrication process used is presented in Fig. 9. The polymerization reactions. Then, a second UV laser ablation
process started with the cleaning of the 150-mm as-cut process step was applied to form 50-μm diameter through
polycrystalline silicon panel with acetone, methanol, holes in the polymer, leading to 15-μm TPV sidewall liners.
isopropanol, and deionized water. Then, TPVs were drilled Precise alignment of the laser beam to the TPV locations was
by 355-nm UV laser ablation with via entrance diameters necessary to ensure that the ablation process happened in the
of 80 μm. UV lasers were used for the best combination center of the vias in silicon and to maintain sufficient polymer
of via size reduction, cost, and throughput. The panels then liner thickness on the side walls. The TPV metallization
underwent a plasma cleaning step to remove impurities, and redistribution layer fabrication required an electroless
followed by a surface treatment with silane solutions copper seed layer, in contrast to sputtered seed for TSVs.
(3-aminopropyltrimethoxy silane). This silane treatment was Prior to such a process, a chemical desmear process was
meant to form covalent bonds at the interfaces between silicon performed to roughen the polymer liner surface to improve
and the applied polymer films to improve adhesion [23]. Cu-to-polymer adhesion. The panel was then patterned by
40-μm-thick polymer dry films were laminated on both sides a double-sided lithography process. This process consisted
to insulate the surface and fill the via. This step was achieved of several steps, starting with dry-film photoresist lamination
using a vacuum laminator at 95 °C. This vacuum-assisted using a hot roll laminator, followed by an UV exposure, and
process removed the air inside the via, leading to a faster photoresist development by dilute sodium carbonate solution
in a spray tool. Subsequently, electrolytic copper plating
using a semiadditive process method was carried out, varying
both the current density as well as the plating time to control
the final Cu thickness. The photoresist was then stripped by
potassium hydroxide and the Cu seed layer was etched by
dilute CuCl2 solution. The top view of the fabricated test
structures is shown in Fig. 10.

V. RELIABILITY CHARACTERIZATION OF TPVs

The test vehicles were first subjected to a 24-h bake at
125 °C, followed by accelerated moisture sensitivity level 3
preconditioning (60 °C and 60% RH for 40 h), followed
by three times reflow at a peak temperature of 260 °C, to
simulate the lead-free solder board assembly processes. The
test vehicles were then subjected to thermal cycles between
−55 °C and 125 °C with a dwelling time of 15 min at each
temperature extreme, as described in JEDEC JESD22-A104
condition B test standard. The samples were taken out
at 100, 200, 500 cycles, and every 500 cycles thereafter,
and the daisy chain resistances were measured to detect

CHEN et al.: MODELING, FABRICATION, AND RELIABILITY OF THROUGH VIAS IN POLYCRYSTALLINE SILICON PANELS 943

Fig. 11. Resistance measurement of reliability samples. Fig. 13. SEM image of Si/polymer liner interface.

low modulus and moderate CTE that effectively absorbed the
stresses from CTE mismatch between copper and silicon.

VI. CONCLUSION

This paper presents, for the first time, the modeling,
fabrication, and reliability of TPVs in polycrystalline silicon
panels. The reliability test vehicles with metalized TPVs and
daisy chain structures were successfully demonstrated. Both
mechanical modeling and reliability characterization results
indicate that TPVs in polycrystalline silicon panels can achieve
high reliability due to the thick sidewall polymer liners with
low modulus and moderate CTE.

Fig. 12. SEM image of Cu/polymer liner interface. ACKNOWLEDGMENT

TPV failures, as shown in Fig. 11. No significant resistance The authors would like to thank the Silicon and Glass
changes were observed during the tests. All the TPV daisy Interposer Consortium of Georgia Tech Packaging Research
chains survived 4000 thermal shock cycles with a stable Center for their support. The authors would also like to
resistance value of 0.13 , confirming the thermomechanical thank Y. Suzuki from Zeon Corporation for polymer process
reliability of TPVs in polycrystalline silicon panels. guidance, and Micron Laser for their support.

To characterize the samples after thermal cycling tests, SEM REFERENCES
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944 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 5, NO. 7, JULY 2015

[8] X. Liu et al., “Reliability assessment of through-silicon vias in Hao Lu received the B.S. and M.S. degrees in
multi-die stack packages,” IEEE Trans. Device Mater. Rel., vol. 12, no. 2, Mechanical Engineering from the Huazhong Univer-
pp. 263–271, Jun. 2012. sity of Science and Technology, Wuhan, China. He is
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“Failure analysis of through-silicon vias in free-standing wafer under Institute of Technology (Georgia Tech), Atlanta,
thermal-shock test,” Microelectron. Rel., vol. 53, no. 1, pp. 70–78, GA, USA.
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He is a Graduate Research Assistant with the 3D
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Mater. Rel., vol. 12, no. 2, pp. 285–295, Jun. 2012. His main research interests include the multilayer
redistribution layer design, fabrication, and signal
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tion of the Entire System. New York, NY, USA: McGraw-Hill, 2008.
Venky Sundaram received the B.S. degree from IIT
[12] Q. Chen et al., “Design and demonstration of low cost, panel-based Mumbai, Mumbai, India, and the M.S. and Ph.D.
polycrystalline silicon interposer with through-package-vias (TPVs),” degrees in materials science and engineering from
in Proc. IEEE 61st Electron. Compon. Technol. Conf. (ECTC), the Georgia Institute of Technology (Georgia Tech),
Lake Buena Vista, FL, USA, May/Jun. 2011, pp. 855–860. Atlanta, GA, USA.

[13] V. Sundaram, Q. Chen, Y. Suzuki, G. Kumar, F. Liu, and R. Tummala, He is currently the Director of Research and
“Low-cost and low-loss 3D silicon interposer for high bandwidth logic- Industry Relations with the 3-D Systems Packaging
to-memory interconnections without TSV in the logic IC,” in Proc. Research Center, Georgia Tech. He is the Program
IEEE 62nd Electron. Compon. Technol. Conf. (ECTC), May/Jun. 2012, Director of the Low-Cost Interposer and Packages
pp. 292–297. Industry Consortium with over 25 active global
industry members. He is a globally recognized
[14] Q. Chen, Y. Suzuki, G. Kumar, V. Sundaram, and R. R. Tummala, expert in packaging technology, and the Co-Founder of Jacket Micro Devices,
“Modeling, fabrication, and characterization of low-cost and high- Livonia, MI, USA, and a RF/wireless startup acquired by AVX Corporation,
performance polycrystalline panel-based silicon interposer with through Fountain Inn, SC, USA. He has authored over 100 publications and
vias and redistribution layers,” IEEE Trans. Compon., Packag., Manuf. holds 15 patents. His current research interests include system-on-package
Technol., vol. 4, no. 12, pp. 2035–2041, Dec. 2014. technology, 3-D packaging and integration, ultrahigh-density interposers,
embedded components, and systems integration research.
[15] A. F. B. Braga, S. P. Moreira, P. R. Zampieri, J. M. G. Bacchin, Dr. Sundaram is the Co-Chairman of the IEEE Components, Packaging and
and P. R. Mei, “New processes for the production of solar-grade Manufacturing Technology Technical Committee on High Density Substrates
polycrystalline silicon: A review,” Solar Energy Mater. Solar Cells, and the Director of Education Programs with the Executive Council of the
vol. 92, no. 4, pp. 418–424, 2008. International Microelectronics and Packaging Society. He has received several
best paper awards.
[16] J. Degoulange, I. Périchaud, C. Trassy, and S. Martinuzzi, “Multicrys-
talline silicon wafers prepared from upgraded metallurgical feedstock,” Rao R. Tummala (F’93) received the B.S. degree
Solar Energy Mater. Solar Cells, vol. 92, no. 10, pp. 1269–1273, 2008. from the Indian Institute of Science (IIS),
Bangalore, India, and the Ph.D. degree from
[17] S. Pizzini, “Towards solar grade silicon: Challenges and benefits for the University of Illinois at Urbana–Champaign,
low cost photovoltaics,” Solar Energy Mater. Solar Cells, vol. 94, no. 9, Champaign, IL, USA.
pp. 1528–1533, 2010.
He was an IBM Fellow, pioneering the first plasma
[18] A. A. Istratov, T. Buonassisi, M. D. Pickett, M. Heuer, and E. R. Weber, display and multichip electronics for mainframes
“Control of metal impurities in ‘dirty’ multicrystalline silicon for solar and servers. He is currently a Distinguished and
cells,” Mater. Sci. Eng. B, vol. 134, nos. 2–3, pp. 282–286, 2006. Endowed Chair Professor and the Founding Director
of the National Science Foundation’s Engineering
[19] C. Yang, F. Mess, K. Skenes, S. Melkote, and S. Danyluk, “On the Research Center with the Georgia Institute of
residual stress and fracture strength of crystalline silicon wafers,” Appl. Technology (Georgia Tech), Atlanta, GA, USA, pioneering Moore’s Law
Phys. Lett., vol. 102, no. 2, p. 021909, 2013. for system integration. He has authored over 500 technical papers, the
first modern book entitled Microelectronics Packaging Handbook, the first
[20] X. F. Brun and S. N. Melkote, “Analysis of stresses and breakage of undergrad textbook entitled Fundamentals of Microsystems Packaging, and
crystalline silicon wafers during handling and transport,” Solar Energy the first book introducing the system-on-package technology, and holds
Mater. Solar Cells, vol. 93, no. 8, pp. 1238–1247, Aug. 2009. 74 patents and inventions.
Prof. Tummala is a member of the National Academy of Engineering.
[21] M. J. Madou, Fundamentals of Microfabrication: The Science of He has received many industry, academic, and professional society awards,
Miniaturization, 2nd ed. Boca Raton, FL, USA: CRC Press, Mar. 2002. including the Industry Week’s Award for improving the U.S. competitiveness,
the IEEE David Sarnoff and Dan Hughes Awards from the International
[22] X. Liu et al., “Dimension and liner dependent thermomechanical strain Microelectronics and Packaging Society, the Engineering Materials Award
characterization of through-silicon vias using synchrotron X-ray diffrac- from ASM, and the Total Excellence in Manufacturing Award from the
tion,” J. Appl. Phys., vol. 114, no. 6, p. 06490, 2013. Society of Manufacturing Engineers. He was a recipient of the Distinguished
Alumni Awards from the University of Illinois, IIS, and Georgia Tech, and
[23] K. L. Mittal, Silanes and Other Coupling Agents, vol. 4. Boca Raton, the Technovisionary Award from the Indian Semiconductor Association and
FL, USA: CRC Press, 2007. the IEEE Field Award for his contributions in electronics systems integration
and cross-disciplinary education in 2011. He was the President of the IEEE
Qiao Chen received the B.S. and M.S. degrees in Components, Packaging and Manufacturing Technology and the International
materials science and engineering from Tsinghua Microelectronics and Packaging Society.
University, Beijing, China, in 2006 and 2008,
respectively, and the Ph.D. degree in electrical and
computer engineering from the Georgia Institute of
Technology, Atlanta, GA, USA, in 2015.

His current research interests include the mod-
eling, design, demonstration, and characterization
of through-silicon-via and silicon interposers for
3-D integration.


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