State Table Verification - ohio.edu

State Table Verification State Table Verification
for Sequential Circuit for Sequential Circuit

Moore Theorem : Given the state table of a sequential machine,
find an input /output sequence pair (X,Z) such
For any reduced strongly connected (no equivalent that the response to X will be Z iff machine
states & any state reachable from another state) is fault free. Then (X,Z) is calledchecking
n-state sequential machine M, there is an sequence and test is calledchecking
input-output sequence pair that can be generated experiment
by M but can not be generated by any other
sequential machine with n or fewer states

This sequence is called checking sequence

State Table Verification State Table Verification
for Sequential Circuit for Sequential Circuit

In order to find “initial state” we use a “homing” Example : Homing sequence is x=101
or a “distinguishing” sequence since the final state can be
State table uniquely defined:
Definition : homing sequence present input
is such an input X that the final state can be state x=0 x=1 initial state state/output final state
uniquely determined ( by observing its output only)
A C,1 D,0 A D,0 C,0 C,1
B D,0 B,1 B B,1 D,0 A,0
C B,0 C,1 C C,1 B,0 B,1
D C,0 A,0 D A,0 C,1 C,1

State Table Verification State Table Verification
for Sequential Circuit
for Sequential Circuit
Definition : Distinguishing sequence
is such an input sequence X that will produce • Uncertainty is a collection of sates which is known
different output sequence for each initial state to contain the present state.
(so the initial state can be distinguished)
• A successor tree is a structure which displays
Every distinguishing sequence is a homing successor uncertainties for all input sequences xi
sequence but not opposite
• A collection of uncertainties is an uncertainty
vector

• An uncertainty vector whose components contain a
single state, each is trivial

• A vector whose components contain single states or
identical repeated states is homogeneous

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State table verification State Table Verification
for sequential circuit for Sequential Circuit

Algorithm to generate homing sequence: Example : Consider FSM

Homing sequence - path from root to trivial or State table
homogenous vector. present input
Homing tree is a successor tree in which a node state x=0 x=1
becomes terminal if :
A B,0 D,0
1. Non-homogenous components in an uncertainty B A,0 B,0
vector are the same as on the previous level C D,1 A,0
D D,1 C,0
2. Uncertainty vector is trivial or homogeneous

State table Homing Sequence Algorithm to generate a
distinguishing sequence
present input
Distinguishing sequence - path from root to trivial
state x=0 x=1 Example : vector. A distinguishing tree is a successor tree in
A B,0 D,0 which a node becomes terminal if
(ABCD)
B A,0 B,0 1. Non-homogenous components in an uncertainty
C D,1 A,0 01 vector are the same as on the previous level
D D,1 C,0
(AB(DD) (ABCD) 2. Uncertainty vector contains a homogeneous
non-trivial component (does not have to be
01 a homogeneous vector)

(AB)(DD) (BD)(CC) 3. Uncertainty vector istrivial

01

(A)(D)(DD) (BC)(AA) same

homing 01

(A)(D)(BB) (AB)(DD)

State table verification present input
for sequential circuit
state x=0 x=1 A successor tree
Example : Consider the following state table
A A,0 C,1

ECBxample : BAF,i,01ndiDCng,,01dis(tAinBgCuDis)hing sequence
D D,0 B,00 1
present input
state x=0 x=1 (ABD)(A) (BC)(CD)
A A,0 C,1
B B,0 D,1 01 01
C A,1 C,0
D D,0 B,0 (A)(ABD) (B)(CD)(C) (B)(A)(A)(D) (D)(C)(BC)

01 01

(B)(A)(D)(A) (D)(CB)(C) (D)(A)(B)(A) (B)(C)(D)(C)

01

(D)(A)(B)(A) (B)(C)(D)(C)

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State table verification Distinguishing Sequence
for sequential circuit

Example : Consider FSM Example : Consider FSM, different output vectors

for different initial state Input sequence X = 1,0

State table (ABCD) State table initial input
present input 01 present input state x=1 x=0
state x=0 x=1 (AB)(DD) (ABCD) state x=0 x=1
Homogeneous component A C,1 A,1
A B,0 D,0 A A,0 C,1 B D,1 D,0
B A,0 B,0 No distinguishing sequence B B,0 D,1 C C,0 A,1

C D,1 A,0 C A,1 C,0 D B,0 B,0
D D,1 C,0
D D,0 B,0 so X=1,0 distinguishing

Transfer Sequence Transfer Sequence

Transfer sequence - takes machine from one state Example : Consider the following FSM
to another
Example : Consider previous FSM (no transfer sequence) State table
present input
B state x=0 x=1
01
BD A B,1 C,0
B A,0 D,1
01 C B,0 A,0
DB D C,1 A,1
Not strongly connected FSM

Transfer Tree State table verification
for sequential circuit
Example :
Synchronizing sequence takes machine to the
we get the transfer tree 0/1 specific final state regardless of the output or
initial state - does not always exists
A B
0/0 Example :
Algorithm to generate synchronizing sequence :
B 1/1 1/0 0/0 Consider the previous machine with synchronizing
01 1/1 sequence x= 1,1,0

A D 1/0
01 01 DC
0/1

B CC A

To get to C we can select x = 1,0

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Synchronizing Sequence

Example : (ABCD)

01

(ABC) (ACD)

01 01

(AB) (ACD) (BC) (AC)
0
01 1 01

(AB) (CD) (AB) (AD) (B) (AC)

Designing checking experiments Designing checking experiments

Machine must be strongly connected & diagnosable Example : Consider FSM
( i.e. have a distinguishing sequence)
1. Initialization (take it to a fixed state[s]) State table 1. Initialization:
present input Successor tree
a) Apply homing sequence & identify the table x=0 x=1
current state (ABCD)
A B,1 C,0
b) Transfer current state to S B A,0 D,1 01
2. Identification (make machine to visit each state C B,0 A,0
(BC)(AB) (AC)(AD)
and display response) D C,1 A,1
3. Transition verification (make every state transition 01

result checked by distinguishing sequence) (AB)(A)(B) (A)(C)(D)(D)

Found homing sequence x = 0,1

Designing checking experiments Designing checking State table
experiments present input
Example (cont.) : After applying homing sequence 0 1 table x=0 x=1
2. Identification:
State table Initial Input final Visit each state and A B,1 C,0
present input states 0 1 states analyze the results
table x=0 x=1 B A,0 D,1
A B,1 D,1 D C B,0 A,0
A B,1 C,0 D C,1 A,1
B A,0 D,1 B A,0 C,0 C
C B,0 A,0 C B,0 D,1 D time 1 2 3 4 5 6 7 8 9 10 11
D C,1 A,1 D C,1 A,0 A input 0 1 0 1 0 0 1 0 1 0 1
state A D A B C D A
output 1 1 1 0 1 0 0 0 1 1 0

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Designing checking experiments Designing checking experiments

3. Transition verification: Example : Check transition from C to B with
input 0 and from C to A with input 1, and so on.
Check transition from A to B with input 0, then The entire checking test

apply distinguishing sequence 01 time 1 2 3 4 5 6 7 8 9 10 11
input 0 0 1 0 0 1 1 0 1 0 0
State table state A B C B C A D C
output 1 0 0 0 0 0 0 1 1 1 0
time 123 present input
input 00 1 table x=0 x=1

A B,1 C,0

state A B C B A,0 D,1

output 1 0 0 C B,0 A,0
D C,1 A,1

Designing checking experiments
(cont)

time 12 13 14 15 16 17 18 19 20 21
input
state 11010 10001
output
DA D BA

11 11 1 0 1 0 1 1

time 22 23 24 25 26 27 28 29 30 31
input
state 11010 10101
output
DA C D BD A

1001101110

DFT for sequential circuits DFT for sequential circuits

Critical testability problems Checking experiments can not be applied for
FSM without a distinguishing sequence
1. Noninitializable design - change design to have
a synchronizing sequence Modification procedure for such FSM:
I. Construct testing table
2. Effects of component delays - check for hazard &
races in simulation upper part contains states & input/output pairs
lower part contains products of present & next
3. Nondetected logic redundant faults -do not use states with the rule that (state)*(-) = (-)
logic redundancy II. Construct testing graph

4. Existence of illegal states - avoid add transition
to normal states

5. Oscillating circuit - add extra logic to control
oscillations

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DFT for sequential circuits DFT for sequential circuits

Example: Testing table for machine II . Construct testing graph

state table present input/output An edge Xp/Zp exists directed from present state
SiSj to next states SkSl if SkSl (k ≠ l) is present in
present input state 0/0 0/1 1/0 1/1 row SiSj under Xp/Zp
state x=0 x=1
A A,0 B,0 A A- B -
B A,0 C,0
C A,1 D,0 B A- C -
D A,1 A,0
C -AD - Example:
for our machine
D -AA - we have: 1/0
AB BC
AB AA - BC - 1/0 1/0 AC
1/0 1/0
AC - - BD -

AD - - AB -

BC - - CD - BD

BD - - AC - AD CD
1/0
CD - AA AD -

DFT for sequential circuits DFT for sequential circuits

A machine isdefinitely diagnosable if its testing Example: (with added output)
graph has no loops and there are no repeated states
(i.e. no circled states in testing table) – so the present input Testing graph
example machine is not definitely diagnosable state x=0 x=1 1/01

In order to make machine definitely diagnosable A A,00 B,01 AD BA
additional outputs (up to k = log (# states ) ) are B A,01 C,00
required C A,10 D,00 1/00
D A,11 A,01 BC CD

After machine is modified to have distinguishing
sequence apply checking experiment procedure
to test it.

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