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Blade –A Timing Violation Resilient Asynchronous Template Dylan Hand∗, Matheus Trevisan Moreira∗†, Hsin-Ho Huang∗, Danlei Chen∗, Frederico Butzke ...

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Published by , 2017-05-15 04:50:03

Blade A Timing Violation Resilient Asynchronous Template

Blade –A Timing Violation Resilient Asynchronous Template Dylan Hand∗, Matheus Trevisan Moreira∗†, Hsin-Ho Huang∗, Danlei Chen∗, Frederico Butzke ...

Blade – A Timing V
Asynchronou

Dylan Hand∗, Matheus Trevisa
Danlei Chen∗, Frederico Butzke‡,
Melvin Breuer∗, Ney Laert Vilar C

May 4th

* University of Southern California, Los A
† Pontifícia Universidade Católica do Rio
‡ Universidade de Santa Cruz do Sul, S

Violation Resilient
us Template

an Moreira∗†, Hsin-Ho Huang∗,
, Zhichao Li∗, Matheus Gibiluka†,
Calazans†, and Peter A. Beerel∗

h, 2015

Angeles, CA
o Grande do Sul, Porto Alegre, Brazil
Santa Cruz do Sul, Brazil

Delay Overheads

Cycle time of
clocked logic

Logic Time PVT m
Clock m
Logic gates Flip-flop alig

Traditional synchronous design
• Worse at low and near-thres

margin
margin
gnment

[Dreslinksi et al., IEEE Proc. 2010]

suffers from increased margins
shold regions

MOTIVATION | 2

Data Dependent De Number of Operations

Cycle time of
clocked logic

Logic Time

Logic gates Worst-Case
Data

Delay variation due to data is rarely

elays

Data delay in Plasma CPU

Delay Slower

y exploited in traditional designs

MOTIVATION | 3

Data Dependent De Number of Operations

Cycle time of
clocked logic

Logic Time

Logic gates Worst-Case
Data

Delay variation due to data is rarely

elays

Worst-Case Delay

Data delay in Plasma CPU

Delay Slower

y exploited in traditional designs

MOTIVATION | 3

Data Dependent De Number of Operations

Cycle time of
clocked logic

Logic Time

Logic gates Worst-Case
Data

Delay variation due to data is rarely

elays

Average Delay Worst-Case Delay

Data delay in Plasma CPU

Delay Slower

y exploited in traditional designs

MOTIVATION | 3

Resilient Design

CLK = 0

Sequential
Gate

Shadow De
Sequential

Allow and detect timing errors in
• Correct via architectural rep

Logic Next Pipeline
Stage

Error To Control Logic
etection

n datapath
play or gating/pausing clock

RESILIENT DESIGN | 4

Resilient Design

CLK = 0

Sequential
Gate

Shadow De
Sequential

Allow and detect timing errors in
• Correct via architectural rep

Logic Next Pipeline
Stage

Error To Control Logic
etection

n datapath
play or gating/pausing clock

RESILIENT DESIGN | 4

Resilient Design

CLK = 1

Sequential
Gate

Shadow De
Sequential

Allow and detect timing errors in
• Correct via architectural rep

Logic Next Pipeline
Stage

Error 0
etection To Control Logic

n datapath
play or gating/pausing clock

RESILIENT DESIGN | 4

Resilient Design

CLK = 1

Sequential
Gate

Shadow De
Sequential

Allow and detect timing errors in
• Correct via architectural rep

Effective approaches have been

Logic Next Pipeline
Stage

Error 1
etection To Control Logic

n datapath
play or gating/pausing clock

n elusive!

RESILIENT DESIGN | 4

LatchMetastability Issue

Shadow CLK
FF
The Problem [Beer et al, 2014]
• Flop metastability can propa
• Metastability in control path

Logic Next Pipeline Stage

To Control Logic

[Bubble Razor, Fojtik, 2013]

agate to ERR signal
can cause system failure

RESILIENT DESIGN | 5

LatchMetastability Issue

Shadow CLK
FF
The Problem [Beer et al, 2014]
• Flop metastability can propa
• Metastability in control path

Logic Next Pipeline Stage

To Control Logic

[Bubble Razor, Fojtik, 2013]

agate to ERR signal
can cause system failure

RESILIENT DESIGN | 5

LatchMetastability Issue

Shadow CLK
FF
X

The Problem [Beer et al, 2014]
• Flop metastability can propa
• Metastability in control path

Logic Next Pipeline Stage

X
To Control Logic

[Bubble Razor, Fojtik, 2013]

agate to ERR signal
can cause system failure

RESILIENT DESIGN | 5

Handling Metastabi

CLK

Latch

Transition
Detector

Transition detector may exhibit m

• Error signal must go through sync
• Uses architectural replay to recov

ility

Logic Next Pipeline Stage

To Control Logic

[RazorII, Das, 2009]

metastability

chronizer, increasing delay

ver from errors

RESILIENT DESIGN | 6

Handling Metastabi

CLK

Latch

Transition X
Detector

Transition detector may exhibit m

• Error signal must go through sync
• Uses architectural replay to recov

ility

Logic Next Pipeline Stage

To Control Logic

[RazorII, Das, 2009]

metastability

chronizer, increasing delay

ver from errors

RESILIENT DESIGN | 6

Handling Metastabi

CLK

Latch

Transition X
Detector S

Transition detector may exhibit m

• Error signal must go through sync
• Uses architectural replay to recov

ility

Logic Next Pipeline Stage

FF FF To Control Logic

Synchronizer [RazorII, Das, 2009]

metastability

chronizer, increasing delay

ver from errors

RESILIENT DESIGN | 6

Handling Metastabi

CLK

Latch

Transition
Detector

S

Transition detector may exhibit m

• Error signal must go through sync
• Uses architectural replay to recov

ility

Logic Next Pipeline Stage

1 or 0
FF FF To Control Logic

Synchronizer [RazorII, Das, 2009]

metastability

chronizer, increasing delay

ver from errors

RESILIENT DESIGN | 6

Hold Time Concern

Ring O
Clock G

Data In
In Comb. F
Logic

Internal Data

Relies on latch for error correc
Hold times are problematic

ns

Oscillator STOP
Generator

CLK

MS
Detector

FF

Out

Latch

[SafeRazor, Cannizzaro, 2014]

ction

RESILIENT DESIGN | 7

Hold Time Concern

Ring O
Clock G

Data In
In Comb. F
Logic

Internal Data

Relies on latch for error correc
Hold times are problematic

ns

Oscillator
Generator

STOP

MS Out
Detector

FF
CLK = 1

Latch

[SafeRazor, Cannizzaro, 2014]

ction

RESILIENT DESIGN | 7

Resiliency Landsca

Design Sync / MTBF
Template Async Safe

Bubble Sync No
Razor Sync Yes
Yes*
Razor II

SafeRazor Async

ape

Avoids Hold Low Error
Replay Time Penalty
Logic Robust

Yes Yes Yes

No No No
Yes No Yes

RESILIENT DESIGN | 8

Resiliency Landsca

Design Sync / MTBF
Template Async Safe

Bubble Sync No
Razor Sync
Yes
Razor II Yes*
Yes
SafeRazor Async
Blade Async

Blade combines the best featur

ape

Avoids Hold Low Error
Replay Time Penalty
Logic Robust

Yes Yes Yes

No No No
Yes No Yes
Yes Yes Yes

res of past resiliency schemes

RESILIENT DESIGN | 8

Outline

Our proposed resilient s
Case study – 3-stage Pl

• Automated flow
• Area efficiency features
• Results and comparison

Conclusions and future

solution – Blade
lasma CPU

ns

work

OUTLINE | 21

Blade Template

LE.req
LE.ack

L.ack
L.req

δ

Reconfigurable Dela

L.data Combinational
Logic

Blade Stage
Single Rail Datapa

Asynchronous
Controller

Blade RE.req
Controller RE.ack

Δ R.ack
R.req
Err
ay Lines CLK
Sample 2

EDL R.data

Error Detection Logic Error Detecting
Latch

ath

BLADE TEMPLATE | 10

CLKBlade Template Op

Sample Controller
A

Δ

Err

Co

EDL

Error Detection Logic

Send request speculatively befo
Timing errors delay handshakin

peration Controller
B
δ
Δ

Err
CLK

Sample

ombinational EDL
Logic
Error Detection Logic

ore data is guaranteed stable
ng signals

BLADE TEMPLATE | 11

CLKBlade Template Op

Sample Controller
A

Δ

Err

Co

EDL

Error Detection Logic

Send request speculatively befo
Timing errors delay handshakin

peration Controller
B
δ
Δ

Err
CLK

Sample

ombinational EDL
Logic
Error Detection Logic

ore data is guaranteed stable
ng signals

BLADE TEMPLATE | 11

CLKBlade Template Op

Sample Controller
A

Δ

Err

Co

EDL

Error Detection Logic

Send request speculatively befo
Timing errors delay handshakin

peration Controller
B
δ
Δ

Err
CLK

Sample

ombinational EDL
Logic
Error Detection Logic

ore data is guaranteed stable
ng signals

BLADE TEMPLATE | 11


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